![(please configure the [header_logo] section in trac.ini)](/trac/coach/chrome/site/your_project_logo.png){kind=logo}
Changeset 99 for anr/section-4.1.tex
- Timestamp:
- Feb 8, 2010, 12:11:05 AM (14 years ago)
- File:
-
- 1 edited
-
anr/section-4.1.tex (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
anr/section-4.1.tex
r65 r99 17 17 In figures, the dotted boxes are the softwares or formats that COACH 18 18 has to provide and to support. 19 \ vspace*{.75ex}\par19 \parlf 20 20 For the system generation presented in figure~\ref{archi-csg}, the conductor 21 21 is the tool \verb!CSG! (COACH System Generator). Its inputs are a process … … 35 35 FPGA device\footnote{Additional partial bitstreams are generated in case of 36 36 dynamic partial reconfiguration}. 37 \\38 37 %To proove CSG that COACH is open and CSG is really configurable, COACH will 39 38 %basically support 3 architecture template (the COACH template based on a 40 39 %MIPS processors and a VCI token ring, the Altera template based on the NIOS 41 %and AVALON bus, the Xilinx template based on the MICROBLAZE and OPB bus)40 %and AVALON bus, the Xilinx template based on the MICROBLAZE and PLB bus) 42 41 %and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced 43 42 %by the \mustbecompleted{FIXME:zied} contribution that consists in … … 46 45 %Finally, it is important to notice that this work is a strong 47 46 %enhancement of the SocLib software. 48 \ vspace*{.75ex}\par47 \parlf 49 48 The software architecture for HAS is presented in figure~\ref{archi-hls}. 50 49 The input is a single task of the process network. The HAS tools do not work … … 61 60 Furthermore, the back-end tools uses a macro-cell library (functional and memory 62 61 unit). 63 \ vspace*{.75ex}\par62 \parlf 64 63 In addition to digital system design, HPC requires a supplementary 65 64 partitioning step presented in figure~\ref{archi-hpc}. The designer … … 70 69 simulator. Once the partitioning is validated, the design of the FPGA part 71 70 is done through \verb!CSG! (figure~\ref{archi-csg}). 72 \vspace*{.75ex}\par73 71 \mustbecompleted{FIXME == MODIFICATION DE LA FIGURE} 74 The project is split into 8 tasks numbered from 0 to 7. 75 The first task (task 0) is the project management, the last one (task 7) is 76 the dissemination the other task are listed below: 77 \begin{enumerate} 78 \item\textbf{\Backbone:} This task tackles the fundamental points of the 72 \parlf 73 The project is split into 8 tasks numbered from 1 to 8. There are described 74 bellow and detailled in section \ref{task-description}. 75 \begin{description} 76 \item[Task-1: \textit{Project management}] 77 This task relies to the monitoring of the COACH project. 78 \item[Task-2: \textit{\Backbone}] This task tackles the fundamental points of the 79 79 project such as the defintion of the COACH inputs and outputs, 80 80 the internal formats (e.g. \xcoach), the architectural templates and 81 81 the design flow. 82 \item \textbf{System generation:}This task addresses the prototyping and82 \item[task-3: \textit{System generation}] This task addresses the prototyping and 83 83 the generation of digital system. Apart from HAS that belong to the task 3 84 84 and 4, its components are those presented figure~\ref{archi-csg} 85 85 (e.g. \verb!CSG!, operating systems). 86 \item \textbf{HAS front-end:}This task mainly focusses on four functionalities:86 \item[Task-4: \textit{HAS front-end}] This task mainly focusses on four functionalities: 87 87 optimization of the memory usage, parallelism enhancement through loop 88 88 transformations, coarse grain parallelization and ASIP generation. 89 \item \textbf{HAS back-end:}This task groups two functionalities:89 \item[Task-5: \textit{HAS back-end}] This task groups two functionalities: 90 90 High-Level Synthesis of data dominated description and HLS of control 91 91 dominated description. … … 93 93 that will allow the coprocessors to respect the processor \& the bus 94 94 frequency. 95 \item \textbf{Communication between PC \& FPGA-SoC:}95 \item[Task-6: \textit{PC/FPGA communication middleware}] 96 96 This task pools the features dedicated to HPC. The main are the 97 97 partitioning validation (see figure~\ref{archi-hpc}), the sytem drivers for 98 98 both PC and FPGA-SoC sides, the hardware communication components and 99 99 support for dynamic partial reconfiguration. 100 \item \textbf{Demonstrators:}100 \item[Task-7: \textit{Industrial demonstrators}] 101 101 This task groups the demonstrators of the COACH project. 102 \mustbecompleted{FIXME} 103 \end{enumerate} 102 Most of them are industrial applications that will be developped with the COACH 103 framework. 104 Others consist in integrating COACH framework as a driver of industrial proprietary 105 design tools. 106 \item{Task 8: \textit{Dissemination}} 107 This task relies to the diffusion of the project results. 108 It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!, 109 \verb!T0+24! and \verb!T0+36!) 110 and the publication on a WEB site of a tutorial. 111 \end{description} 104 112 % 105 113 \begin{figure}\leavevmode\center … … 109 117 \end{figure} 110 118 Figure~\ref{dependence-task} presents the tasks dependencies. 111 "$ task-N \longrightarrow task-M$" means that $task-N$ impacts the $task-M$.119 "$T_N \longrightarrow T_M$" means that $T_N$ impacts the $T_M$. 112 120 The more bold is the arrow, the more important is the dependency. 113 121 The graph shows: 114 122 \begin{itemize} 115 \item Even that $T 3$ and $T4$ functionalities are complementary, their123 \item Even that $T4$ and $T5$ functionalities are complementary, their 116 124 developments are independent (thanks to \xcoach internal format). 117 \item $T 2$ slightly depends on $T3$ and $T4$. Indeed, $T2$ may works118 without $T 3$ and $T4$ if we limit to digital systems without hardware125 \item $T3$ slightly depends on $T4$ and $T5$. Indeed, $T3$ may works 126 without $T4$ and $T5$ if we limit to digital systems without hardware 119 127 accellerators. 120 \item $T 2$ strongly impacts on $T5$ but, $T2$ does not depend at all on121 $T 5$. So demonstrators ($T6$) of embedded system would not be impacted if122 $T 5$ would fail.123 \item $T 1$ drives all the tasks ($T2$, $T3$, $T4$, $T5$) at the heart of128 \item $T3$ strongly impacts on $T6$ but, $T3$ does not depend at all on 129 $T6$. So demonstrators ($T7$) of embedded system would not be impacted if 130 $T6$ would fail. 131 \item $T2$ drives all the tasks ($T3$, $T4$, $T5$, $T6$) at the heart of 124 132 the COACH project. 125 \item The demonstrators developped in $T 6$, of course, strongly depends on the achievements126 of the prvious tasks ($T 1$, $T2$, $T3$, $T4$, $T5$).127 \item $T 7$ and $T0$ respectively depends on and impacts all the other tasks.133 \item The demonstrators developped in $T7$, of course, strongly depends on the achievements 134 of the prvious tasks ($T2$, $T3$, $T4$, $T5$, $T6$). 135 \item $T8$ and $T1$ respectively depends on and impacts all the other tasks. 128 136 \end{itemize} 129 137 This organisation offers enough robustness to insure the success of the 130 project except for the specification task $T 1$.131 132 The only critical task in this chart is T1. \label{xcoach-problem}138 project except for the specification task $T2$. 139 \\ 140 The only critical task in this chart is $T2$. \label{xcoach-problem} 133 141 However, the partners met 134 142 10 times (a one day meeting per month) during the last year to prepare the 135 143 specification and the project proposal. This gives us a degree of confidence 136 that T1will be completed in time.144 that $T2$ will be completed in time.
Note: See TracChangeset
for help on using the changeset viewer.
