Opened 18 years ago
Closed 18 years ago
#10 closed task (fixed)
Flushed Mwmr fifos
Reported by: | Nicolas Pouillon | Owned by: | Nicolas Pouillon |
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Priority: | major | Milestone: | Fin stage sept 2006 |
Component: | muteks | Version: | |
Keywords: | Cc: |
Description
Implement flush-based mwmrs and deprecate prefetch memory
Change History (2)
comment:1 Changed 18 years ago by
comment:2 Changed 18 years ago by
Resolution: | → fixed |
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Status: | new → closed |
This is controlled by some compile time switch, we are now waiting on soclib implementation and conformance for reg CP0,16 and CACHE instruction, but this this Mips4, and not compatible with other instructions
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Best way to handle this is to have access to cache caracteristics from software.
We could implement CP0/16 (Config1) register in Mips