Changes between Version 1 and Version 2 of MwmrCoprocCreation


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Timestamp:
Mar 13, 2009, 10:52:38 AM (15 years ago)
Author:
Nicolas Pouillon
Comment:

--

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  • MwmrCoprocCreation

    v1 v2  
    44 * It handles packets of 64 values, representing a block of 8*8 coefficients
    55 * It has one input and one output fifo
    6  * It handles 16-bit values
     6 * Input is 32-bit coefficients, output is 8-bit pixels
    77
    88== Coprocessor ==
    99
    10 First we'll write the coprocessor in Caba [wiki:SystemC].
     10First we'll write the coprocessor in Caba [wiki:SystemC SystemC].
    1111
    12 {{{
    13 
    14 }}}
     12see [browser:trunk/dsx/lib/soclib/modules/fifo_idct/caba]
    1513
    1614== Declaration for SocLib code generation ==
    1715
    18 We have to declare this component to DSX:
     16We have to declare this component to soclib build system, see [anrsoclib:wiki:SoclibDesc]:
    1917
     18in [browser:trunk/dsx/lib/soclib/modules/fifo_idct/caba/metadata/fifo_idct.sd]:
    2019{{{
    21 #!python
    22 class HwIdct(MwmrCoproc):
    23     def __init__(self, name, **d):
    24         MwmrCoproc.__init__(self, name, ['input'], ['output'], **d)
     20Module('caba:fifo_idct',
     21           classname = 'dsx::caba::FifoIdct',
     22           header_files = [
     23        "../source/include/fifo_idct.h",
     24        "../../include/fifo_idct.h",
     25        ],
     26           implementation_files = [
     27                "../source/src/fifo_idct.cpp",
     28                ],
     29           ports = [
     30        Port('caba:fifo_output', 'p_to_ctrl'),
     31        Port('caba:fifo_input', 'p_from_ctrl'),
     32        Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
     33        Port('caba:clock_in', 'p_clk', auto = 'clock'),
     34        ],
     35           uses = [
     36                Uses('caba:base_module'),
     37                ],
     38           instance_parameters = [
     39        parameter.Int('latency'),
     40        ],
     41           tmpl_parameters = [
     42        parameter.Type('word_t'),
     43        ],
     44)
    2545}}}
    26 
    27 And register a Caba driver for this component:
    28 
    29 {{{
    30 #!python
    31 
    32 # Heritage from MwmrCoprocCabaDriver is important
    33 class idctgen(MwmrCoprocCabaDriver):
    34     # Here goal is to map between TaskModel fifo names and actual component's fifos
    35     namemap = {'output':'OUT', 'input':'IN'}
    36     # For all below, see [1]
    37     headers = 'hw_components/hw_idct.h',
    38     def __init__(self, node):
    39         MwmrCoprocCabaDriver.__init__(self, node)
    40         self.plugmap['output'] = "OUT"
    41         self.plugmap['input'] = "IN"
    42     def genType(self, driver):
    43         return 'HW_IDCT'
    44     def genDecl(self, driver):
    45         return '("%s")'%(self.node.name)
    46 Caba.register(HwIdct, idctgen)
    47 }}}
    48 
    49 Notes:
    50  1. CabaDriver
    5146
    5247== Task declaration ==
    5348
     49Now we define a task, with a software implementation, and a mwmr coprocessor implementation:
     50
     51in `idct.task`:
    5452{{{
    55 #!python
     53TaskModel(
     54    'hw_idct',
     55    ports = {
     56             'input':MwmrInput(64*4),
     57             'output':MwmrOutput(64),
     58             },
     59    impls = [
     60        SwTask( 'idct',
     61            stack_size = 4096,
     62            sources = [ 'idct.c' ],
     63            defines = [ 'WIDTH', 'HEIGHT' ] ),
     64        MwmrCoproc(
     65            module = 'caba:fifo_idct',
     66            from_coproc = [ 'output:to_ctrl' ],
     67            to_coproc = [ 'input:from_ctrl' ],
     68            config = [],
     69            status = [],
     70            latency = 128,
     71            word_t = 'uint32_t' )
     72    ] )
     73}}}
    5674
    57 idct = TaskModel(
    58     'idct',
    59     infifos = [ 'input' ],
    60     outfifos = [ 'output' ],
    61     impl = [ SwTask( 'idct',
    62                      stack_size = 1024,
    63                      sources = [ 'src/idct.c' ] ),
    64              HwTask( HwIdct )
    65            ] )
     75== Creating the coprocessor in the netlist ==
     76
     77In our netlist, we now have to create the coprocessor and its controller. There is a helper function to do this:
     78
     79{{{
     80    # The helper function needs the task implementation: get the task model
     81    idct = dsx.TaskModel.getByName('hw_idct').getImpl(soclib.HwTask)
     82
     83    # The we can call the helper function, it returns the controller
     84    # and the coprocessor components freshly instanciated
     85
     86    # first argument is your current platform (the one from soclib.Architecture()
     87    # second argument is base name, coprocessor will use "NAME", and controller "NAME_ctrl"
     88    ctrl, coproc = idct.instanciate(arch, 'idct0') # here names are "idct0" and "idct0_ctrl"
     89
     90    # Connections between the controller and the coprocessor has been completed (fifos, config, status)
     91    # Anything else is to be done by the designer.
     92    # For instance, connecting the controller to the interconnect, and assigning a segment to the controller.
     93
     94    ctrl.addSegment('idct0_ctrl', 0x70400000, 0x100, False)
     95    ctrl.vci_initiator // vgmn.to_initiator.new()
     96    ctrl.vci_target // vgmn.to_target.new()
    6697}}}
    6798
    6899== That's all ==
    69100
    70 Now we can map this coprocessor as an hardware task
     101Now we can map this coprocessor as an hardware task:
     102
     103{{{
     104tcg = Tcg(
     105    ....
     106    Task( 'idct0', 'hw_idct', ... ),
     107    ....
     108    )
     109
     110....
     111
     112mapper.map( "idct0",
     113            coprocessor = "idct0",
     114            controller = "idct0_ctrl")
     115}}}