Version 19 (modified by 17 years ago) (diff) | ,
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A) Interconnects
A.1) Vgmn
- functionality : a generic VCI compliant micro-network
- Arguments:
instance name
min_latency
(one-way)fifo_size
- Example:
my_vgmn = arch.create('caba:vci_vgmn', "my_vgmn", min_latency = 10, fifo_size = 8)
- Defined ports:
to_initiator.new()
andto_target.new()
: local ports, allocated on demand
A.2) LocalCrossbar
- functionality : a VCI compliant crossbar interconnect
- Arguments:
instance name
- Example:
my_lc = arch.create('caba:vci_local_crossbar', "lc0")
- Defined ports:
to_initiator.new()
andto_target.new()
: local ports, allocated on demand
B) VCI Initiators
B.1) Xcache
- functionality: a direct mapping cache controler (separated instruction & data cache)
- Arguments:
instance name
dcache_lines
: number of lines in data cachedcache_words
: number of words per line in data cacheicache_lines
: number of lines in instruction cacheicache_words
: number of words per line in instruction cache
- Example:
my_cache = arch.create('caba:vci_vgmn', "my_cache", dcache_lines = 32, dcache_words = 8, icache_lines = 32, icache_words = 8 )
- Defined ports:
dcache
: to the CPUicache
: to the CPUvci
: to the VCI micro-network
C) Processors
C.1) Mips
This component is special as it is in fact a wrapped ISS.
- Functionality : a MIPS R3000 micro-processor
- Arguments:
name
ident
: cpu id
- Example:
my_proc = arch.create('caba:iss_wrapper', "my_proc", iss_t = 'common:mipsel', ident = 0 )
- Defined ports:
dcache
: to the cache's dcache porticache
: to the cache's icache portirq[n]
: interrupt line (0 <= n < 6)
D) VCI Targets
D.1) MultiRam
- !Mandatory arguments:
name
- Example:
my_ram = arch.create('caba:vci_ram', "my_ram")
- Defined ports:
vci
: to the micro-network
- Adding a segment:
- Arguments: name, base address, size, cacheability
my_ram.addSegment( 'boot', 0xbfc00000, 0x100, true )
- Arguments: name, base address, size, cacheability
D.2) MultiTty
- functionality: a TTY controler
- Mandatory arguments:
instance name
- a list of names
- Example:
my_tty = arch.create('caba:vci_multi_tty', "my_tty_controler", ["TTY0", "TTY1", "TT2"])
- Defined ports:
vci
: to the micro-networkirq[n]
: interrupt line (0 <= n < nb of ttys)