source: soft/giet_vm/giet_drivers/sdc_driver.h @ 787

Last change on this file since 787 was 563, checked in by alain, 10 years ago

1) Introduce a new driver "sdc_driver" for SD Card uding directly the 4 bits SD bus.
2) Improve the debug for all IOC drivers (debug activated only if _get_time() > GIET_DEBUG_IOC_DRIVER).

File size: 8.4 KB
Line 
1///////////////////////////////////////////////////////////////////////////////////
2// File     : sdc_driver.h
3// Date     : 31/08/2012
4// Author   : cesar fuguet
5// Copyright (c) UPMC-LIP6
6///////////////////////////////////////////////////////////////////////////////////
7// The sdc_driver.c and sdc_driver.h files are part ot the GIET-VM kernel.
8// This driver supports the SocLib VciAhciSdc component, that is a single channel,
9// block oriented, SD card contrÃŽler, respecting the AHCI standard.
10//
11// 1. This driver supports only SD Cards V2 and higher, and the block
12//    size must be 512 bytes.
13//
14// 2. The VciAhciSdc component supports several simultaneous commands,
15//    and each command can be split in several physical memory buffers,
16//    but this driver supports only commands containing one single buffer.
17//
18// 3. The "command list" can contain up to 32 independant commands, posted
19//    by different user tasks. These independant transfers are handled
20//    by the AHCI_SDC device in the same order as they have been written by the
21//    driver(s) in the command list. There is no global lock protecting the
22//    the HBA device, but the command list being a shared structure, the driver
23//    must use an atomic_increment() to get a slot in the command list,
24//    and increment the write pointer.
25//
26// 4. This driver implements two operating mode:
27//    - In synchronous mode, the calling task poll the   AHCI_PXCI register to
28//    detect the command completion (busy waiting).
29//    - In descheduling mode, the calling task is descheduled, and must be
30//    restart when the command is completed.
31//
32// 5. As several user tasks can concurrently register commands in the command
33//    list, and there is only one HBA interrupt, this interrupt is not linked
34//    to a specific task. In descheduling mode, the HBA IRQ is a "global" IRQ
35//    that is statically routed to processor P[x_io,y_io,0] in cluster_io.
36//    The associated global   AHCI_ISR send a WAKUP WTI to all tasks that have
37//    a completed command. This   AHCI_ISR uses a read pointer on the command
38//    to identify the first expected command completion. The incrementation
39//    of this read pointer does not require atomic_increment as there is
40//    no concurrent access for this pointer.
41//
42// The SEG_IOC_BASE virtual address must be defined in the hard_config.h file.
43///////////////////////////////////////////////////////////////////////////////////
44
45#ifndef _GIET_SDC_DRIVER_H_
46#define _GIET_SDC_DRIVER_H_
47
48/////////////////////////////////////////////////////////////////////////////
49//    SDC Addressable Registers (up to 64 registers)
50/////////////////////////////////////////////////////////////////////////////
51
52enum SoclibSdcRegisters
53{
54    SDC_PERIOD       = 32,          // system cycles       / Write-Only
55    SDC_CMD_ID       = 33,          // command index       / Write-Only
56    SDC_CMD_ARG      = 34,          // command argument    / Write-Only
57    SDC_RSP_STS      = 35,          // response status     / Read-Only
58};
59
60/////////////////////////////////////////////////////////////////////////////
61//    Software supported SDC commands
62/////////////////////////////////////////////////////////////////////////////
63
64enum SoclibSdcCommands
65{
66    SDC_CMD0         = 0,           // Soft reset
67    SDC_CMD3         = 3,           // Relative Card Address
68    SDC_CMD7         = 7,           // Toggle mode
69    SDC_CMD8         = 8,           // Voltage info
70    SDC_CMD41        = 41,          // Operation Condition
71};
72
73enum SoclibSdcErrorCodes
74{
75    SDC_ERROR_LBA    = 0x40000000,  // LBA larger tnan SD card capacity
76    SDC_ERROR_CRC    = 0x00800000,  // CRC error reported by SD card
77    SDC_ERROR_CMD    = 0x00400000,  // command notsupported by SD card
78};
79           
80///////////////////////////////////////////////////////////////////////////////
81//      Various SD Card constants
82///////////////////////////////////////////////////////////////////////////////
83
84#define SDC_CMD8_ARGUMENT   0x00000155  // VHS = 2.7-3.6 V / check = 0x55
85#define SDC_CMD41_ARGUMENT  0x40000000  // High Capacity Host Support
86#define SDC_CMD41_RSP_BUSY  0x80000000  // Card Busy when 0     
87#define SDC_CMD41_RSP_CCS   0x40000000  // High Capacity when 1
88 
89/////////////////////////////////////////////////////////////////////////////
90//    AHCI Addressable Registers
91/////////////////////////////////////////////////////////////////////////////
92
93enum SoclibAhciRegisters
94{
95    AHCI_PXCLB       = 0,           // command list base address 32 LSB bits
96    AHCI_PXCLBU      = 1,           // command list base address 32 MSB bits
97    AHCI_PXIS        = 4,           // interrupt status
98    AHCI_PXIE        = 5,           // interrupt enable
99    AHCI_PXCMD       = 6,           // run
100    AHCI_PXCI        = 14,          // command bit-vector     
101};
102
103/////////////////////////////////////////////////////////////////////////////
104// AHCI structures for Command List
105/////////////////////////////////////////////////////////////////////////////
106
107/////// command descriptor  ///////////////////////
108typedef struct ahci_cmd_desc_s  // size = 16 bytes
109{
110    unsigned char       flag[2];    // W in bit 6 of flag[0]
111    unsigned char       prdtl[2];       // Number of buffers
112    unsigned int        prdbc;          // Number of bytes actually transfered
113    unsigned int        ctba;           // Command Table base address 32 LSB bits
114    unsigned int        ctbau;          // Command Table base address 32 MSB bits
115} ahci_cmd_desc_t;
116
117
118/////////////////////////////////////////////////////////////////////////////
119// AHCI structures for Command Table
120/////////////////////////////////////////////////////////////////////////////
121
122/////// command header  ///////////////////////////////
123typedef struct ahci_cmd_header_s     // size = 16 bytes
124{
125    unsigned int        res0;       // reserved
126    unsigned char           lba0;           // LBA 7:0
127    unsigned char           lba1;           // LBA 15:8
128    unsigned char           lba2;           // LBA 23:16
129    unsigned char           res1;           // reserved
130    unsigned char           lba3;           // LBA 31:24
131    unsigned char           lba4;           // LBA 39:32
132    unsigned char           lba5;           // LBA 47:40
133    unsigned char           res2;           // reserved
134    unsigned int        res3;       // reserved
135} ahci_cmd_header_t;
136
137/////// Buffer Descriptor //////////////////////////
138typedef struct ahci_cmd_buffer_s // size = 16 bytes
139{
140    unsigned int        dba;        // Buffer base address 32 LSB bits
141    unsigned int        dbau;       // Buffer base address 32 MSB bits
142    unsigned int        res0;       // reserved
143    unsigned int        dbc;        // Buffer bytes count
144} ahci_cmd_buffer_t;
145
146/////// command table /////////////////////////////////
147typedef struct ahci_cmd_table_s     // size = 32 bytes
148{
149    ahci_cmd_header_t   header;     // contains LBA value
150    ahci_cmd_buffer_t   buffer;     // contains buffer descriptor
151} ahci_cmd_table_t;
152
153
154///////////////////////////////////////////////////////////////////////////////
155// This function initializes the AHCI_SDC controller and the SD Card.
156// Returns 0 if success, > 0 if failure
157///////////////////////////////////////////////////////////////////////////////
158
159unsigned int _sdc_init();
160
161///////////////////////////////////////////////////////////////////////////////
162// Transfer data between the block device and a memory buffer.
163// - use_irq   : polling strategy when zero
164// - to_mem    : to memory if non zero
165// - lba       : first block index on the block device
166// - buf_vaddr : base address of the memory buffer
167// - count     : number of blocks to be transfered.
168// Returns 0 if success, > 0 if error.
169///////////////////////////////////////////////////////////////////////////////
170
171unsigned int _sdc_access( unsigned int       use_irq, 
172                          unsigned int       to_mem,
173                          unsigned int       lba,
174                          unsigned long long buf_vaddr,
175                          unsigned int       count);
176
177///////////////////////////////////////////////////////////////////////////////
178// This ISR handles the IRQ generated by the AHCI_SDC controler.
179///////////////////////////////////////////////////////////////////////////////
180
181void _sdc_isr( unsigned int irq_type,
182               unsigned int irq_id,
183               unsigned int channel );
184
185#endif
186
187// Local Variables:
188// tab-width: 4
189// c-basic-offset: 4
190// c-file-offsets:((innamespace . 0)(inline-open . 0))
191// indent-tabs-mode: nil
192// End:
193// vim: filetype=c:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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