Ignore:
Timestamp:
May 18, 2015, 6:45:58 PM (9 years ago)
Author:
alain
Message:

1) Introduce a new driver "sdc_driver" for SD Card uding directly the 4 bits SD bus.
2) Improve the debug for all IOC drivers (debug activated only if _get_time() > GIET_DEBUG_IOC_DRIVER).

File:
1 edited

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  • soft/giet_vm/giet_drivers/sdc_driver.h

    r545 r563  
    55// Copyright (c) UPMC-LIP6
    66///////////////////////////////////////////////////////////////////////////////////
     7// The sdc_driver.c and sdc_driver.h files are part ot the GIET-VM kernel.
     8// This driver supports the SocLib VciAhciSdc component, that is a single channel,
     9// block oriented, SD card contrÃŽler, respecting the AHCI standard.
     10//
     11// 1. This driver supports only SD Cards V2 and higher, and the block
     12//    size must be 512 bytes.
     13//
     14// 2. The VciAhciSdc component supports several simultaneous commands,
     15//    and each command can be split in several physical memory buffers,
     16//    but this driver supports only commands containing one single buffer.
     17//
     18// 3. The "command list" can contain up to 32 independant commands, posted
     19//    by different user tasks. These independant transfers are handled
     20//    by the AHCI_SDC device in the same order as they have been written by the
     21//    driver(s) in the command list. There is no global lock protecting the
     22//    the HBA device, but the command list being a shared structure, the driver
     23//    must use an atomic_increment() to get a slot in the command list,
     24//    and increment the write pointer.
     25//
     26// 4. This driver implements two operating mode:
     27//    - In synchronous mode, the calling task poll the   AHCI_PXCI register to
     28//    detect the command completion (busy waiting).
     29//    - In descheduling mode, the calling task is descheduled, and must be
     30//    restart when the command is completed.
     31//
     32// 5. As several user tasks can concurrently register commands in the command
     33//    list, and there is only one HBA interrupt, this interrupt is not linked
     34//    to a specific task. In descheduling mode, the HBA IRQ is a "global" IRQ
     35//    that is statically routed to processor P[x_io,y_io,0] in cluster_io.
     36//    The associated global   AHCI_ISR send a WAKUP WTI to all tasks that have
     37//    a completed command. This   AHCI_ISR uses a read pointer on the command
     38//    to identify the first expected command completion. The incrementation
     39//    of this read pointer does not require atomic_increment as there is
     40//    no concurrent access for this pointer.
     41//
     42// The SEG_IOC_BASE virtual address must be defined in the hard_config.h file.
     43///////////////////////////////////////////////////////////////////////////////////
    744
    845#ifndef _GIET_SDC_DRIVER_H_
    946#define _GIET_SDC_DRIVER_H_
    1047
    11 #include <spi_driver.h>
    12 #include <mapping_info.h>
     48/////////////////////////////////////////////////////////////////////////////
     49//    SDC Addressable Registers (up to 64 registers)
     50/////////////////////////////////////////////////////////////////////////////
     51
     52enum SoclibSdcRegisters
     53{
     54    SDC_PERIOD       = 32,          // system cycles       / Write-Only
     55    SDC_CMD_ID       = 33,          // command index       / Write-Only
     56    SDC_CMD_ARG      = 34,          // command argument    / Write-Only
     57    SDC_RSP_STS      = 35,          // response status     / Read-Only
     58};
     59
     60/////////////////////////////////////////////////////////////////////////////
     61//    Software supported SDC commands
     62/////////////////////////////////////////////////////////////////////////////
     63
     64enum SoclibSdcCommands
     65{
     66    SDC_CMD0         = 0,           // Soft reset
     67    SDC_CMD3         = 3,           // Relative Card Address
     68    SDC_CMD7         = 7,           // Toggle mode
     69    SDC_CMD8         = 8,           // Voltage info
     70    SDC_CMD41        = 41,          // Operation Condition
     71};
     72
     73enum SoclibSdcErrorCodes
     74{
     75    SDC_ERROR_LBA    = 0x40000000,  // LBA larger tnan SD card capacity
     76    SDC_ERROR_CRC    = 0x00800000,  // CRC error reported by SD card
     77    SDC_ERROR_CMD    = 0x00400000,  // command notsupported by SD card
     78};
     79           
     80///////////////////////////////////////////////////////////////////////////////
     81//      Various SD Card constants
     82///////////////////////////////////////////////////////////////////////////////
     83
     84#define SDC_CMD8_ARGUMENT   0x00000155  // VHS = 2.7-3.6 V / check = 0x55
     85#define SDC_CMD41_ARGUMENT  0x40000000  // High Capacity Host Support
     86#define SDC_CMD41_RSP_BUSY  0x80000000  // Card Busy when 0     
     87#define SDC_CMD41_RSP_CCS   0x40000000  // High Capacity when 1
     88 
     89/////////////////////////////////////////////////////////////////////////////
     90//    AHCI Addressable Registers
     91/////////////////////////////////////////////////////////////////////////////
     92
     93enum SoclibAhciRegisters
     94{
     95    AHCI_PXCLB       = 0,           // command list base address 32 LSB bits
     96    AHCI_PXCLBU      = 1,           // command list base address 32 MSB bits
     97    AHCI_PXIS        = 4,           // interrupt status
     98    AHCI_PXIE        = 5,           // interrupt enable
     99    AHCI_PXCMD       = 6,           // run
     100    AHCI_PXCI        = 14,          // command bit-vector     
     101};
     102
     103/////////////////////////////////////////////////////////////////////////////
     104// AHCI structures for Command List
     105/////////////////////////////////////////////////////////////////////////////
     106
     107/////// command descriptor  ///////////////////////
     108typedef struct ahci_cmd_desc_s  // size = 16 bytes
     109{
     110    unsigned char       flag[2];    // W in bit 6 of flag[0]
     111    unsigned char       prdtl[2];       // Number of buffers
     112    unsigned int        prdbc;          // Number of bytes actually transfered
     113    unsigned int        ctba;           // Command Table base address 32 LSB bits
     114    unsigned int        ctbau;          // Command Table base address 32 MSB bits
     115} ahci_cmd_desc_t;
     116
     117
     118/////////////////////////////////////////////////////////////////////////////
     119// AHCI structures for Command Table
     120/////////////////////////////////////////////////////////////////////////////
     121
     122/////// command header  ///////////////////////////////
     123typedef struct ahci_cmd_header_s     // size = 16 bytes
     124{
     125    unsigned int        res0;       // reserved
     126    unsigned char           lba0;           // LBA 7:0
     127    unsigned char           lba1;           // LBA 15:8
     128    unsigned char           lba2;           // LBA 23:16
     129    unsigned char           res1;           // reserved
     130    unsigned char           lba3;           // LBA 31:24
     131    unsigned char           lba4;           // LBA 39:32
     132    unsigned char           lba5;           // LBA 47:40
     133    unsigned char           res2;           // reserved
     134    unsigned int        res3;       // reserved
     135} ahci_cmd_header_t;
     136
     137/////// Buffer Descriptor //////////////////////////
     138typedef struct ahci_cmd_buffer_s // size = 16 bytes
     139{
     140    unsigned int        dba;        // Buffer base address 32 LSB bits
     141    unsigned int        dbau;       // Buffer base address 32 MSB bits
     142    unsigned int        res0;       // reserved
     143    unsigned int        dbc;        // Buffer bytes count
     144} ahci_cmd_buffer_t;
     145
     146/////// command table /////////////////////////////////
     147typedef struct ahci_cmd_table_s     // size = 32 bytes
     148{
     149    ahci_cmd_header_t   header;     // contains LBA value
     150    ahci_cmd_buffer_t   buffer;     // contains buffer descriptor
     151} ahci_cmd_table_t;
     152
    13153
    14154///////////////////////////////////////////////////////////////////////////////
    15 // SD card structure definition
     155// This function initializes the AHCI_SDC controller and the SD Card.
     156// Returns 0 if success, > 0 if failure
    16157///////////////////////////////////////////////////////////////////////////////
    17 struct sdcard_dev
    18 {
    19     // SPI controller pointer
    20     struct spi_dev * spi;
    21158
    22     // block length of the SDCARD
    23     unsigned int block_length;
    24 
    25     // access pointer representing the offset in bytes used to read or write in
    26     // the SDCARD. This driver is for cards SDSD, therefore this offset must be
    27     // multiple of the block length
    28     unsigned int access_pointer;
    29 
    30     // slave ID. This ID represents the number of the slave select signal used
    31     // in the hardware platform (SPI channel)
    32     int slave_id;
    33 
    34     // is the card high capacity ?
    35     int sdhc;
    36 };
    37 
    38 ///////////////////////////////////////////////////////////////////////////////
    39 // This function initializes the SPI controller and call sdc_open to
    40 // initialize  the SD card
    41 // - channel: channel to initialize (only channel 0 supported)
    42 // Returns 0 if success, other value if failure
    43 ///////////////////////////////////////////////////////////////////////////////
    44159unsigned int _sdc_init();
    45160
    46161///////////////////////////////////////////////////////////////////////////////
    47162// Transfer data between the block device and a memory buffer.
    48 // - use_irq   : not used, as DMA is not supported yet
     163// - use_irq   : polling strategy when zero
    49164// - to_mem    : to memory if non zero
    50165// - lba       : first block index on the block device
    … …  
    53168// Returns 0 if success, > 0 if error.
    54169///////////////////////////////////////////////////////////////////////////////
     170
    55171unsigned int _sdc_access( unsigned int       use_irq, 
    56172                          unsigned int       to_mem,
    … …  
    60176
    61177///////////////////////////////////////////////////////////////////////////////
    62 // This ISR handles the IRQ generated by a SDC controler
     178// This ISR handles the IRQ generated by the AHCI_SDC controler.
    63179///////////////////////////////////////////////////////////////////////////////
     180
    64181void _sdc_isr( unsigned int irq_type,
    65182               unsigned int irq_id,
    66183               unsigned int channel );
    67 
    68 ///////////////////////////////////////////////////////////////////////////////
    69 // SD card constants
    70 ///////////////////////////////////////////////////////////////////////////////
    71 
    72 // Number of retries after an unacknowledge command
    73 #define SDCARD_COMMAND_TIMEOUT  100
    74 
    75 // This command is a simple SD commmand
    76 #define SDCARD_CMD              0
    77 
    78 // This is an application specific command
    79 #define SDCARD_ACMD             1
    80 
    81 // The transmition is done in the negative edge of the clock
    82 #define SDCARD_TX_NEGEDGE       0
    83 
    84 // The transmition is done in the positive edge of the clock
    85 #define SDCARD_TX_POSEDGE       1
    86 
    87 // The reception is done in the negative edge of the clock
    88 #define SDCARD_RX_NEGEDGE       0
    89 
    90 // The reception is done in the positive edge of the clock
    91 #define SDCARD_RX_POSEDGE       1
    92 
    93 ///////////////////////////////////////////////////////////////////////////////
    94 // SD card macros
    95 ///////////////////////////////////////////////////////////////////////////////
    96 
    97 ///////////////////////////////////////////////////////////////////////////////
    98 //   SDCARD_CHECK_R1_VALID()
    99 // This macro checks if the SD card response is valid
    100 // - x: SD card response
    101 // Returns 1 if valid and 0 otherwise
    102 ///////////////////////////////////////////////////////////////////////////////
    103 #define SDCARD_CHECK_R1_VALID(x)    (~x & SDCARD_R1_RSP_VALID) ? 1 : 0
    104 
    105 ///////////////////////////////////////////////////////////////////////////////
    106 //   SDCARD_CHECK_R1_ERROR()
    107 // This macro checks if there is an error in SD card response
    108 // - x: SD card response
    109 // Returns 1 if error and 0 otherwise
    110 ///////////////////////////////////////////////////////////////////////////////
    111 #define SDCARD_CHECK_R1_ERROR(x)    ( x & 0x7E)                ? 1 : 0
    112 
    113 // SD card response 1 (R1) format constants
    114 #define SDCARD_R1_IN_IDLE_STATE     ( 1 << 0 ) // R1 bit 0
    115 #define SDCARD_R1_ERASE_RESET       ( 1 << 1 ) // R1 bit 1
    116 #define SDCARD_R1_ILLEGAL_CMD       ( 1 << 2 ) // R1 bit 2
    117 #define SDCARD_R1_COM_CRC_ERR       ( 1 << 3 ) // R1 bit 3
    118 #define SDCARD_R1_ERASE_SEQ_ERR     ( 1 << 4 ) // R1 bit 4
    119 #define SDCARD_R1_ADDRESS_ERR       ( 1 << 5 ) // R1 bit 5
    120 #define SDCARD_R1_PARAMETER_ERR     ( 1 << 6 ) // R1 bit 6
    121 #define SDCARD_R1_RSP_VALID         ( 1 << 7 ) // R1 bit 7
    122184
    123185#endif
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