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source: soft/giet_vm/giet_python/mapping.py @ 345

Last change on this file since 345 was 341, checked in by cfuguet, 11 years ago

giet_python/mapping.py:

bugfix: some peripheral base addresses and sizes were erroneously set during hard_config.h generation.

Property svn:executable set to *

File size: 101.5 KB

Rev	Line
[305]	1	#!/usr/bin/env python
	2
[319]	3	import sys
	4
	5	##########################################################################################
[305]	6	# file : giet_mapping.py
	7	# date : april 2014
	8	# author : Alain Greiner
[319]	9	##########################################################################################
	10	# This file contains the classes required to define a mapping for the GIET_VM.
	11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
	12	# a set of 'Vseg' (kernel virtual segments mapping)
	13	# a set of 'Vspace' (several user applications).
	14	# - A 'Cluster' contains a set of 'Pseg' (all physical segments in cluster)
	15	# a set of 'Proc' (processors in cluster)
	16	# a set of 'Periph' (peripherals in cluster)
	17	# a set of 'Coproc' (coprocessors in cluster)
	18	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments mapping)
	19	# a set of 'Task' (user tasks mapping)
	20	# - A 'Vseg' contains a set of 'Vobj'
	21	# - A 'Periph' contains a set of 'Irq' (only for XCU, ICU and PIC types )
	22	# - A 'Coproc' contains a set of 'Cpports' (one port per MWMR channel)
	23	##########################################################################################
	24	# Implementation Note
	25	# As described above, the various objects are distributed in the PYTHON structure:
	26	# For example the psegs set is split in several subsets (one subset per cluster),
	27	# or the tasks set is split in several subsets (one subset per vspace), etc...
	28	# In the C binary data structure used by the giet_vm, all objects of same type
	29	# are stored in a linear array (one single array for all psegs for example).
	30	# For all objects, we compute and store in the PYTHON object itsel a "global index"
	31	# corresponding to the index in this global array, and this index can be used as
	32	# a pseudo-pointer to identify a specific object of a given type.
	33	##########################################################################################
[305]	34
[319]	35	######################################################################################
	36	# These global lists must be consistent with enums in mapping_info.h or irq_handler.h
	37	######################################################################################
	38	PERIPHTYPES = [
	39	'CMA',
	40	'DMA',
	41	'FBF',
	42	'ICU',
	43	'IOB',
	44	'IOC',
	45	'MMC',
	46	'MWR',
	47	'NIC',
	48	'ROM',
	49	'SIM',
	50	'TIM',
	51	'TTY',
	52	'XCU',
	53	'PIC',
	54	]
	55
	56	PERIPHSUBTYPES = [
	57	'BDV',
	58	'HBA',
	59	'SPI',
	60	'NONE',
	61	]
	62
	63	IRQTYPES = [
	64	'HWI',
	65	'WTI',
	66	'PTI',
	67	]
	68
	69	ISRTYPES = [
	70	'ISR_DEFAULT',
	71	'ISR_TICK',
	72	'ISR_TTY_RX',
	73	'ISR_TTY_TX',
	74	'ISR_BDV',
	75	'ISR_TIMER',
	76	'ISR_WAKUP',
	77	'ISR_NIC_RX',
	78	'ISR_NIC_TX',
	79	'ISR_CMA',
	80	'ISR_MMC',
	81	'ISR_DMA',
	82	'ISR_SPI',
	83	]
	84
	85	VOBJTYPES = [
	86	'ELF',
	87	'BLOB',
	88	'PTAB',
	89	'PERI',
	90	'MWMR',
	91	'LOCK',
	92	'BUFFER',
	93	'BARRIER',
	94	'CONST',
	95	'MEMSPACE',
	96	'SCHED',
	97	]
	98
	99	VSEGMODES = [
	100	'____',
	101	'___U',
	102	'__W_',
	103	'__WU',
	104	'_X__',
	105	'_X_U',
	106	'_XW_',
	107	'_XWU',
	108	'C___',
	109	'C__U',
	110	'C_W_',
	111	'C_WU',
	112	'CX__',
	113	'CX_U',
	114	'CXW_',
	115	'CXWU',
	116	]
	117
	118	PSEGTYPES = [
	119	'RAM',
	120	'ROM', # deprecated => use PERI
	121	'PERI',
	122	]
	123
	124	CP_PORT_DIRS = [
	125	'TO_COPROC',
	126	'FROM_COPROC',
	127	]
	128
	129	##########################################################################################
[305]	130	class Mapping( object ):
[319]	131	##########################################################################################
[305]	132	def __init__( self,
[319]	133	name, # mapping name
	134	x_size, # number of clusters in a row
	135	y_size, # number of clusters in a column
	136	procs_max, # max number of processors per cluster
	137	x_width = 4, # number of bits encoding x coordinate
	138	y_width = 4, # number of bits encoding y coordinate
	139	paddr_width = 40, # number of bits for physical address
	140	coherence = 1, # hardware cache coherence when non-zero
	141	irq_per_proc = 1, # number or IRQs from XCU to processor
	142	use_ramdisk = False, # use ramdisk when true
	143	x_io = 0, # cluster_io x coordinate
	144	y_io = 0, # cluster_io y coordinate
[328]	145	peri_increment = 0x10000, # address increment for globals
[319]	146	reset_address = 0xBFC00000 ): # Processor wired boot_address
[305]	147
[319]	148	self.signature = 0xDACE2014
	149	self.name = name
	150	self.paddr_width = paddr_width
	151	self.coherence = coherence
	152	self.x_size = x_size
	153	self.y_size = y_size
	154	self.x_width = x_width
	155	self.y_width = y_width
	156	self.irq_per_proc = irq_per_proc
	157	self.procs_max = procs_max
	158	self.use_ramdisk = use_ramdisk
	159	self.x_io = x_io
	160	self.y_io = y_io
[328]	161	self.peri_increment = peri_increment
[319]	162	self.reset_address = reset_address
[305]	163
[319]	164	self.total_vspaces = 0
	165	self.total_globals = 0
	166	self.total_psegs = 0
	167	self.total_vsegs = 0
	168	self.total_vobjs = 0
	169	self.total_tasks = 0
	170	self.total_procs = 0
	171	self.total_irqs = 0
	172	self.total_coprocs = 0
	173	self.total_cpports = 0
	174	self.total_periphs = 0
[305]	175
[319]	176	self.clusters = []
	177	self.globs = []
	178	self.vspaces = []
[305]	179
[319]	180	for x in xrange( self.x_size ):
	181	for y in xrange( self.y_size ):
	182	cluster = Cluster( x , y )
	183	cluster.index = (x * self.y_size) + y
	184	self.clusters.append( cluster )
[305]	185
	186	return
	187
[319]	188	########################## add a ram pseg in a cluster
	189	def addRam( self,
	190	name, # pseg name
	191	base, # pseg base address
	192	size ): # pseg length (bytes)
	193
	194	# check coordinates (obtained from the base address)
	195	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
[305]	196	x = cluster_xy >> (self.y_width);
	197	y = cluster_xy & ((1 << self.y_width) - 1)
	198
[319]	199	assert (base & 0xFFF) == 0
	200
	201	assert (x < self.x_size) and (y < self.y_size)
	202
	203	cluster_id = (x * self.y_size) + y
	204
	205	# add one pseg in the mapping
	206	pseg = Pseg( name, base, size, x, y, 'RAM' )
	207	self.clusters[cluster_id].psegs.append( pseg )
	208	pseg.index = self.total_psegs
	209	self.total_psegs += 1
	210
	211	return pseg
	212
	213	############################## add a peripheral and the associated pseg in a cluster
	214	def addPeriph( self,
	215	name, # associated pseg name
	216	base, # associated pseg base address
	217	size, # associated pseg length (bytes)
	218	ptype, # peripheral type
	219	subtype = 'NONE', # peripheral subtype
	220	channels = 1, # number of channels
	221	arg = 0 ): # optional argument (semantic depends on ptype)
	222
	223	# check cluster coordinates (obtained from the base address)
	224	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
[305]	225	x = cluster_xy >> (self.y_width);
	226	y = cluster_xy & ((1 << self.y_width) - 1)
	227
[319]	228	assert (x < self.x_size) and (y < self.y_size)
	229
	230	assert (base & 0xFFF) == 0
	231
	232	assert ptype in PERIPHTYPES
	233
	234	assert subtype in PERIPHSUBTYPES
	235
	236	cluster_id = (x * self.y_size) + y
	237
	238	# add one pseg into mapping
	239	pseg = Pseg( name, base, size, x, y, 'PERI' )
	240	self.clusters[cluster_id].psegs.append( pseg )
	241	pseg.index = self.total_psegs
	242	self.total_psegs += 1
	243
	244	# add one periph into mapping
	245	periph = Periph( pseg, ptype, subtype, channels, arg )
	246	self.clusters[cluster_id].periphs.append( periph )
	247	periph.index = self.total_periphs
	248	self.total_periphs += 1
	249
	250	return periph
	251
	252	################################ add an IRQ in a peripheral
	253	def addIrq( self,
	254	periph, # peripheral containing IRQ (PIC or XCU)
	255	index, # peripheral input port index
	256	isrtype, # ISR type
	257	channel = 0 ): # channel for multi-channels ISR
	258
	259	assert isrtype in ISRTYPES
	260
	261	assert index < 32
	262
	263	# add one irq into mapping
	264	irq = Irq( 'HWI', index , isrtype, channel )
	265	periph.irqs.append( irq )
	266	irq.index = self.total_irqs
	267	self.total_irqs += 1
	268
	269	return irq
	270
	271	########################## add a processor in a cluster
	272	def addProc( self,
	273	x, # cluster x coordinate
	274	y, # cluster y coordinate
	275	p ): # processor local index
	276
	277	assert (x < self.x_size) and (y < self.y_size)
	278
	279	cluster_id = (x * self.y_size) + y
	280
	281	# add one proc into mapping
	282	proc = Processor( x, y, p )
	283	self.clusters[cluster_id].procs.append( proc )
	284	proc.index = self.total_procs
[305]	285	self.total_procs += 1
	286
[319]	287	return proc
	288
	289	############################## add a coprocessor in a cluster
	290	def addCoproc( self,
	291	name, # associated pseg name
	292	base, # associated pseg base address
	293	size ): # associated pseg length
	294
	295	# check cluster coordinates (obtained from the base address)
	296	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
	297	x = cluster_xy >> (self.y_width);
	298	y = cluster_xy & ((1 << self.y_width) - 1)
	299
	300	assert (x < self.x_size) and (y < self.y_size)
	301
	302	cluster_id = (x * self.y_size) + y
	303
	304	# add one pseg into mapping
	305	pseg = Pseg( name, base, size, x, y, 'PERI' )
	306	self.clusters[cluster_id].psegs.append( pseg )
	307	pseg.index = self.total_psegs
	308	self.total_psegs += 1
	309
	310	# add one coproc into mapping
	311	periph = Coproc( pseg )
	312	self.clusters[cluster_id].coprocs.append( coproc )
	313	periph.index = self.total_coprocs
	314	self.total_coprocs += 1
	315
	316	return coproc
	317
	318	################################## add a port in a coprocessor
	319	def addPort( self,
	320	coproc, # coprocessor containing the port
	321	direction, # direction (TO_COPROC / FROM_COPROC)
	322	vspacename, # name of vspace using the coproc
	323	mwmrname ): # name of the vobj defining the MWMR channel
	324
	325	assert direction in CP_PORT_DIRS
	326
	327	# add one cpport into mapping
	328	port = Cpport( direction, vspacename, mwmrname )
	329	coproc.ports.append( port )
	330	port.index = self.total_cpports
	331	self.total_cpports += 1
	332
	333	return port
	334
	335	############################ add one (or several) global vseg into mapping
	336	def addGlobal( self,
	337	name, # vseg name
	338	vbase, # virtual base address
	339	size, # vobj length (bytes)
	340	mode, # CXWU flags
	341	vtype, # vobj type
	342	x, # destination x coordinate
	343	y, # destination y coordinate
	344	pseg, # destination pseg name
	345	identity = False, # identity mapping required if true
	346	binpath = '' ): # pathname for binary code
	347
	348	assert mode in VSEGMODES
	349
	350	assert vtype in VOBJTYPES
	351
	352	assert (vbase & 0xFFF) == 0
	353
	354	assert (x < self.x_size) and (y < self.y_size)
	355
[328]	356	# add one vseg into mapping
	357	vseg = Vseg( name, vbase, mode, x, y, pseg, identity )
	358	self.globs.append( vseg )
	359	self.total_globals += 1
	360	vseg.index = self.total_vsegs
	361	self.total_vsegs += 1
[319]	362
[328]	363	# add one vobj into mapping
	364	vobj = Vobj( name, size, vtype, binpath, 0, 0 )
	365	vseg.vobjs.append( vobj )
	366	vobj.index = self.total_vobjs
	367	self.total_vobjs += 1
[319]	368
[305]	369	return
	370
[319]	371	################################ add a vspace into mapping
	372	def addVspace( self,
	373	name, # vspace name
	374	startname ): # name of vobj containing start_vector
	375
	376	# add one vspace into mapping
	377	vspace = Vspace( name, startname )
[305]	378	self.vspaces.append( vspace )
[319]	379	vspace.index = self.total_vspaces
	380	self.total_vspaces += 1
	381
	382	return vspace
[305]	383
[319]	384	################################# add a private vseg and a vobj in a vspace
	385	def addVseg( self,
	386	vspace, # vspace containing the vseg
	387	name, # vseg name
	388	vbase, # virtual base address
	389	size, # vobj length (bytes)
	390	mode, # CXWU flags
	391	vtype, # vobj type
	392	x, # destination x coordinate
	393	y, # destination y coordinate
	394	pseg, # destination pseg name
	395	binpath = '', # pathname for binary code
	396	align = 0, # alignment required
	397	init = 0 ): # initial value
	398
	399	assert mode in VSEGMODES
	400
	401	assert vtype in VOBJTYPES
	402
	403	assert (x < self.x_size) and (y < self.y_size)
	404
	405	# add one vseg into mapping
	406	vseg = Vseg( name, vbase, mode, x, y, pseg )
	407	vspace.vsegs.append( vseg )
	408	vseg.index = self.total_vsegs
	409	self.total_vsegs += 1
	410
	411	# add one vobj into mapping
	412	vobj = Vobj( name, size, vtype, binpath, align, init )
	413	vseg.vobjs.append( vobj )
	414	vobj.index = self.total_vobjs
	415	self.total_vobjs += 1
	416
	417	return vseg
	418
	419	################################ add a vobj in a private vseg
	420	def addVobj( self,
	421	vseg, # vseg containing vobj
	422	name, # vobj name
	423	size, # vobj length (bytes)
	424	vtype, # vobj type
	425	binpath = '', # pathname to binary
	426	align = 0, # alignment constraint
	427	init = 0 ): # initial value
	428
	429	assert vtype in VOBJTYPES
	430
	431	# add one vobj into mapping
	432	vobj = Vobj( name, size, vtype, binpath, align, init )
	433	vseg.vobjs.append( vobj )
	434	vobj.index = self.total_vobjs
	435	self.total_vobjs += 1
	436
	437	return vobj
	438
	439	################################ add a task in a vspace
	440	def addTask( self,
	441	vspace, # vspace containing task
	442	name, # task name
	443	trdid, # task index in vspace
	444	x, # destination x coordinate
	445	y, # destination y coordinate
	446	lpid, # destination processor local index
	447	stackname, # name of vobj containing stack
	448	heapname, # name of vobj containing heap
	449	startid, # index in start_vector
	450	usetty = False, # request a private TTY channel
	451	usenic = False, # request a private NIC channel
	452	usecma = False, # request a private CMA channel
	453	usehba = False, # request a private HBA channel
	454	usetim = False ): # request a private TIM channel
	455
	456	assert (x < self.x_size) and (y < self.y_size)
	457
	458	assert lpid < self.procs_max
	459
	460	# add one task into mapping
	461	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid,
	462	usetty, usenic, usecma, usehba, usetim )
	463	vspace.tasks.append( task )
	464	task.index = self.total_tasks
	465	self.total_tasks += 1
	466
	467	return task
	468
	469	#################################
	470	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
	471
	472	byte_stream = bytearray()
	473	length = len( s )
	474	if length < (nbytes - 1):
	475	for b in s:
	476	byte_stream.append( b )
	477	for x in xrange(nbytes-length):
	478	byte_stream.append( '\0' )
	479	else:
	480	print 'error in str2bytes() string %s too long' % s
	481	sys.exit(1)
	482
	483	return byte_stream
	484
	485	###################################
	486	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
	487
	488	byte_stream = bytearray()
	489	for n in xrange( nbytes ):
	490	byte_stream.append( (val >> (n<<3)) & 0xFF )
	491
	492	return byte_stream
	493
	494	################
	495	def xml( self ): # xml file generation for mapping
	496
[305]	497	s = '<?xml version="1.0"?>\n\n'
[319]	498	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
[305]	499	s += ' name = "%s"\n' % (self.name)
	500	s += ' x_size = "%d"\n' % (self.x_size)
	501	s += ' y_size = "%d"\n' % (self.y_size)
	502	s += ' x_width = "%d"\n' % (self.x_width)
	503	s += ' y_width = "%d"\n' % (self.y_width)
	504	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
[319]	505	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
[305]	506	s += ' x_io = "%d"\n' % (self.x_io)
	507	s += ' y_io = "%d" >\n' % (self.y_io)
[319]	508	s += '\n'
	509
[305]	510	s += ' <clusterset>\n'
	511	for x in xrange ( self.x_size ):
	512	for y in xrange ( self.y_size ):
[319]	513	cluster_id = (x * self.y_size) + y
	514	s += self.clusters[cluster_id].xml()
[305]	515	s += ' </clusterset>\n'
[319]	516	s += '\n'
	517
[305]	518	s += ' <globalset>\n'
[319]	519	for vseg in self.globs: s += vseg.xml()
[305]	520	s += ' </globalset>\n'
[319]	521	s += '\n'
	522
[305]	523	s += ' <vspaceset>\n'
[319]	524	for vspace in self.vspaces: s += vspace.xml()
[305]	525	s += ' </vspaceset>\n'
[319]	526
[305]	527	s += '</mapping_info>\n'
	528	return s
[319]	529
	530	#########################
	531	def cbin( self, verbose ): # C binary structure generation for mapping
	532
	533	byte_stream = bytearray()
	534
	535	# header
	536	byte_stream += self.int2bytes(4, self.signature)
	537	byte_stream += self.int2bytes(4, self.x_size)
	538	byte_stream += self.int2bytes(4, self.y_size)
	539	byte_stream += self.int2bytes(4, self.x_width)
	540	byte_stream += self.int2bytes(4, self.y_width)
	541	byte_stream += self.int2bytes(4, self.x_io)
	542	byte_stream += self.int2bytes(4, self.y_io)
	543	byte_stream += self.int2bytes(4, self.irq_per_proc)
	544	byte_stream += self.int2bytes(4, self.use_ramdisk)
	545	byte_stream += self.int2bytes(4, self.total_globals)
	546	byte_stream += self.int2bytes(4, self.total_vspaces)
	547	byte_stream += self.int2bytes(4, self.total_psegs)
	548	byte_stream += self.int2bytes(4, self.total_vsegs)
	549	byte_stream += self.int2bytes(4, self.total_vobjs)
	550	byte_stream += self.int2bytes(4, self.total_tasks)
	551	byte_stream += self.int2bytes(4, self.total_procs)
	552	byte_stream += self.int2bytes(4, self.total_irqs)
	553	byte_stream += self.int2bytes(4, self.total_coprocs)
	554	byte_stream += self.int2bytes(4, self.total_cpports)
	555	byte_stream += self.int2bytes(4, self.total_periphs)
	556	byte_stream += self.str2bytes(32, self.name)
	557
	558	if ( verbose ):
	559	print '\n'
	560	print 'name = %s' % self.name
	561	print 'signature = %x' % self.signature
	562	print 'x_size = %d' % self.x_size
	563	print 'y_size = %d' % self.y_size
	564	print 'x_width = %d' % self.x_width
	565	print 'y_width = %d' % self.y_width
	566	print 'x_io = %d' % self.x_io
	567	print 'y_io = %d' % self.y_io
	568	print 'irq_per_proc = %d' % self.irq_per_proc
	569	print 'use_ramdisk = %d' % self.use_ramdisk
	570	print 'total_globals = %d' % self.total_globals
	571	print 'total_psegs = %d' % self.total_psegs
	572	print 'total_vsegs = %d' % self.total_vsegs
	573	print 'total_vobjs = %d' % self.total_vobjs
	574	print 'total_tasks = %d' % self.total_tasks
	575	print 'total_procs = %d' % self.total_procs
	576	print 'total_irqs = %d' % self.total_irqs
	577	print 'total_coprocs = %d' % self.total_coprocs
	578	print 'total_cpports = %d' % self.total_cpports
	579	print 'total_periphs = %d' % self.total_periphs
	580	print '\n'
	581
	582	# clusters array
	583	index = 0
	584	for cluster in self.clusters:
	585	byte_stream += cluster.cbin( self, verbose, index )
	586	index += 1
	587
	588	if ( verbose ): print '\n'
	589
	590	# psegs array
	591	index = 0
	592	for cluster in self.clusters:
	593	for pseg in cluster.psegs:
	594	byte_stream += pseg.cbin( self, verbose, index, cluster )
	595	index += 1
	596
	597	if ( verbose ): print '\n'
	598
	599	# vspaces array
	600	index = 0
	601	for vspace in self.vspaces:
	602	byte_stream += vspace.cbin( self, verbose, index )
	603	index += 1
	604
	605	if ( verbose ): print '\n'
	606
	607	# vsegs array
	608	index = 0
	609	for vseg in self.globs:
	610	byte_stream += vseg.cbin( self, verbose, index )
	611	index += 1
	612	for vspace in self.vspaces:
	613	for vseg in vspace.vsegs:
	614	byte_stream += vseg.cbin( self, verbose, index )
	615	index += 1
	616
	617	if ( verbose ): print '\n'
	618
	619	# vobjs array
	620	index = 0
	621	for vseg in self.globs:
	622	for vobj in vseg.vobjs:
	623	byte_stream += vobj.cbin( self, verbose, index )
	624	index += 1
	625	for vspace in self.vspaces:
	626	for vseg in vspace.vsegs:
	627	for vobj in vseg.vobjs:
	628	byte_stream += vobj.cbin( self, verbose, index )
	629	index += 1
	630
	631	if ( verbose ): print '\n'
	632
	633	# tasks array
	634	index = 0
	635	for vspace in self.vspaces:
	636	for task in vspace.tasks:
	637	byte_stream += task.cbin( self, verbose, index, vspace )
	638	index += 1
	639
	640	if ( verbose ): print '\n'
	641
	642	# procs array
	643	index = 0
	644	for cluster in self.clusters:
	645	for proc in cluster.procs:
	646	byte_stream += proc.cbin( self, verbose, index )
	647	index += 1
	648
	649	if ( verbose ): print '\n'
	650
	651	# irqs array
	652	index = 0
	653	for cluster in self.clusters:
	654	for periph in cluster.periphs:
	655	for irq in periph.irqs:
	656	byte_stream += irq.cbin( self, verbose, index )
	657	index += 1
	658
	659	if ( verbose ): print '\n'
	660
	661	# coprocs array
	662	index = 0
	663	for cluster in self.clusters:
	664	for coproc in cluster.coprocs:
	665	byte_stream += coproc.cbin( self, verbose, index )
	666	index += 1
	667
	668	if ( verbose ): print '\n'
	669
	670	# cpports array
	671	index = 0
	672	for cluster in self.clusters:
	673	for coproc in cluster.coprocs:
	674	for port in coproc.ports:
	675	byte_stream += port.cbin( self, verbose, index )
	676	index += 1
	677
	678	if ( verbose ): print '\n'
	679
	680	# periphs array
	681	index = 0
	682	for cluster in self.clusters:
	683	for periph in cluster.periphs:
	684	byte_stream += periph.cbin( self, verbose, index )
	685	index += 1
	686
	687	return byte_stream
	688	# end of cbin()
	689
	690	#######################
	691	def giet_vsegs( self ): # compute string for giet_vsegs.ld file
	692	# required by giet_vm compilation
	693
	694	# search the vsegs required for the giet_vsegs.ld
	695	boot_code_found = False
	696	boot_data_found = False
	697	kernel_uncdata_found = False
	698	kernel_data_found = False
	699	kernel_code_found = False
	700	kernel_init_found = False
	701	for vseg in self.globs:
	702	if ( vseg.name == 'seg_boot_code' ):
	703	boot_code_vbase = vseg.vbase
	704	boot_code_size = vseg.vobjs[0].length
	705	boot_code_found = True
	706
	707	if ( vseg.name == 'seg_boot_data' ):
	708	boot_data_vbase = vseg.vbase
	709	boot_data_size = vseg.vobjs[0].length
	710	boot_data_found = True
	711
	712	if ( vseg.name == 'seg_kernel_uncdata' ):
	713	kernel_uncdata_vbase = vseg.vbase
	714	kernel_uncdata_size = vseg.vobjs[0].length
	715	kernel_uncdata_found = True
	716
	717	if ( vseg.name == 'seg_kernel_data' ):
	718	kernel_data_vbase = vseg.vbase
	719	kernel_data_size = vseg.vobjs[0].length
	720	kernel_data_found = True
	721
	722	if ( vseg.name == 'seg_kernel_code' ):
	723	kernel_code_vbase = vseg.vbase
	724	kernel_code_size = vseg.vobjs[0].length
	725	kernel_code_found = True
	726
	727	if ( vseg.name == 'seg_kernel_init' ):
	728	kernel_init_vbase = vseg.vbase
	729	kernel_init_size = vseg.vobjs[0].length
	730	kernel_init_found = True
	731
	732	# check if all required vsegs have been found
	733	if ( boot_code_found == False ):
	734	print 'error in giet_vsegs() : seg_boot_code vseg missing'
	735	sys.exit()
	736
	737	if ( boot_data_found == False ):
	738	print 'error in giet_vsegs() : seg_boot_data vseg missing'
	739	sys.exit()
	740
	741	if ( kernel_data_found == False ):
	742	print 'error in giet_vsegs() : seg_kernel_data vseg missing'
	743	sys.exit()
	744
	745	if ( kernel_uncdata_found == False ):
	746	print 'error in giet_vsegs() : seg_kernel_uncdata vseg missing'
	747	sys.exit()
	748
	749	if ( kernel_code_found == False ):
	750	print 'error in giet_vsegs() : seg_kernel_data vseg missing'
	751	sys.exit()
	752
	753	if ( kernel_init_found == False ):
	754	print 'error in giet_vsegs() : seg_kernel_init vseg missing'
	755	sys.exit()
	756
	757	# build string
[327]	758	s = '/* Generated by genmap for %s */\n' % self.name
[319]	759	s += '\n'
	760
	761	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
	762	s += 'boot_code_size = 0x%x;\n' % boot_code_size
	763	s += '\n'
	764	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
	765	s += 'boot_data_size = 0x%x;\n' % boot_data_size
	766	s += '\n'
	767	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
	768	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
	769	s += '\n'
	770	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
	771	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
	772	s += '\n'
	773	s += 'kernel_uncdata_vbase = 0x%x;\n' % kernel_uncdata_vbase
	774	s += 'kernel_uncdata_size = 0x%x;\n' % kernel_uncdata_size
	775	s += '\n'
	776	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
	777	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
	778	s += '\n'
	779
	780	return s
	781
	782	########################
	783	def hard_config( self ): # compute string for hard_config.h file required by
	784	# - top.cpp compilation
	785	# - giet_vm compilation
	786	# - tsar_preloader compilation
	787
	788	nb_total_procs = 0
	789
	790	# for each peripheral type, define default values
	791	# for pbase address, size, number of components, and channels
	792	nb_cma = 0
	793	cma_channels = 0
	794	seg_cma_base = 0xFFFFFFFF
	795	seg_cma_size = 0
	796
	797	nb_dma = 0
	798	dma_channels = 0
	799	seg_dma_base = 0xFFFFFFFF
	800	seg_dma_size = 0
	801
	802	nb_fbf = 0
	803	fbf_channels = 0
[328]	804	fbf_arg = 0
[319]	805	seg_fbf_base = 0xFFFFFFFF
	806	seg_fbf_size = 0
	807
	808	nb_icu = 0
	809	icu_channels = 0
	810	seg_icu_base = 0xFFFFFFFF
	811	seg_icu_size = 0
	812
	813	nb_iob = 0
	814	iob_channels = 0
	815	seg_iob_base = 0xFFFFFFFF
	816	seg_iob_size = 0
	817
	818	nb_ioc = 0
	819	ioc_channels = 0
	820	seg_ioc_base = 0xFFFFFFFF
	821	seg_ioc_size = 0
	822
	823	nb_mmc = 0
	824	mmc_channels = 0
	825	seg_mmc_base = 0xFFFFFFFF
	826	seg_mmc_size = 0
	827
	828	nb_mwr = 0
	829	mwr_channels = 0
	830	seg_mwr_base = 0xFFFFFFFF
	831	seg_mwr_size = 0
	832
	833	nb_nic = 0
	834	nic_channels = 0
	835	seg_nic_base = 0xFFFFFFFF
	836	seg_nic_size = 0
	837
	838	nb_pic = 0
	839	pic_channels = 0
	840	seg_pic_base = 0xFFFFFFFF
	841	seg_pic_size = 0
	842
	843	nb_rom = 0
	844	rom_channels = 0
	845	seg_rom_base = 0xFFFFFFFF
	846	seg_rom_size = 0
	847
	848	nb_sim = 0
	849	sim_channels = 0
	850	seg_sim_base = 0xFFFFFFFF
	851	seg_sim_size = 0
	852
	853	nb_tim = 0
	854	tim_channels = 0
	855	seg_tim_base = 0xFFFFFFFF
	856	seg_tim_size = 0
	857
	858	nb_tty = 0
	859	tty_channels = 0
	860	seg_tty_base = 0xFFFFFFFF
	861	seg_tty_size = 0
	862
	863	nb_xcu = 0
	864	xcu_channels = 0
[328]	865	xcu_arg = 0
[319]	866	seg_xcu_base = 0xFFFFFFFF
	867	seg_xcu_size = 0
	868
	869	use_bdv = False
	870	use_spi = False
	871	use_hba = False
	872
	873	# get peripherals attributes
	874	for cluster in self.clusters:
	875	for periph in cluster.periphs:
	876	if ( periph.ptype == 'CMA' ):
	877	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
	878	seg_cma_size = periph.pseg.size
	879	cma_channels = periph.channels
	880	nb_cma +=1
	881
	882	elif ( periph.ptype == 'DMA' ):
	883	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
	884	seg_dma_size = periph.pseg.size
	885	dma_channels = periph.channels
	886	nb_dma +=1
	887
	888	elif ( periph.ptype == 'FBF' ):
	889	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
	890	seg_fbf_size = periph.pseg.size
	891	fbf_channels = periph.channels
[328]	892	fbf_arg = periph.arg
[319]	893	nb_fbf +=1
	894
	895	elif ( periph.ptype == 'ICU' ):
	896	seg_icu_base = periph.pseg.base & 0xFFFFFFFF
	897	seg_icu_size = periph.pseg.size
	898	icu_channels = periph.channels
	899	nb_icu +=1
	900
	901	elif ( periph.ptype == 'IOB' ):
	902	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
	903	seg_iob_size = periph.pseg.size
	904	iob_channels = periph.channels
	905	nb_iob +=1
	906
	907	elif ( periph.ptype == 'IOC' ):
	908	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
	909	seg_ioc_size = periph.pseg.size
	910	ioc_channels = periph.channels
	911	nb_ioc += 1
	912	if ( periph.subtype == 'BDV' ): use_bdv = True
	913	elif ( periph.subtype == 'HBA' ): use_hba = True
	914	elif ( periph.subtype == 'SPI' ): use_spi = True
	915
	916	elif ( periph.ptype == 'MMC' ):
	917	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
	918	seg_mmc_size = periph.pseg.size
	919	mmc_channels = periph.channels
	920	nb_mmc +=1
	921
	922	elif ( periph.ptype == 'MWR' ):
	923	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
	924	seg_wmr_size = periph.pseg.size
	925	mwr_channels = periph.channels
	926	nb_mwr +=1
	927
	928	elif ( periph.ptype == 'ROM' ):
	929	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
	930	seg_rom_size = periph.pseg.size
	931	rom_channels = periph.channels
	932	nb_rom +=1
	933
	934	elif ( periph.ptype == 'SIM' ):
	935	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
	936	seg_sim_size = periph.pseg.size
	937	sim_channels = periph.channels
	938	nb_sim +=1
	939
	940	elif ( periph.ptype == 'NIC' ):
	941	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
	942	seg_nic_size = periph.pseg.size
	943	nic_channels = periph.channels
	944	nb_nic +=1
	945
	946	elif ( periph.ptype == 'PIC' ):
	947	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
	948	seg_pic_size = periph.pseg.size
	949	pic_channels = periph.channels
	950	nb_pic +=1
	951
	952	elif ( periph.ptype == 'TIM' ):
	953	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
	954	seg_tim_size = periph.pseg.size
	955	tim_channels = periph.channels
	956	nb_tim +=1
	957
	958	elif ( periph.ptype == 'TTY' ):
	959	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
	960	seg_tty_size = periph.pseg.size
	961	tty_channels = periph.channels
	962	nb_tty +=1
	963
	964	elif ( periph.ptype == 'XCU' ):
	965	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
	966	seg_xcu_size = periph.pseg.size
	967	xcu_channels = periph.channels
[328]	968	xcu_arg = periph.arg
[319]	969	nb_xcu +=1
	970
	971	# don't mix ICU and XCU
	972	assert ( nb_icu*nb_xcu == 0 )
	973
	974	# no more than two access to external peripherals
	975	assert ( nb_fbf <= 2 )
	976	assert ( nb_cma <= 2 )
	977	assert ( nb_ioc <= 2 )
	978	assert ( nb_nic <= 2 )
	979	assert ( nb_tim <= 2 )
	980	assert ( nb_tty <= 2 )
	981	assert ( nb_pic <= 2 )
	982
	983	# one and only one type of IOC controller
	984	assert ( use_hba or use_bdv or use_spi )
	985	assert ( (use_hba and use_bdv) == False )
	986	assert ( (use_hba and use_spi) == False )
	987	assert ( (use_bdv and use_spi) == False )
	988
	989	# Compute total number of processors
	990	for cluster in self.clusters:
	991	nb_total_procs += len( cluster.procs )
	992
	993	# Compute physical addresses for BOOT vsegs
	994	boot_mapping_found = False
	995	boot_code_found = False
	996	boot_data_found = False
	997	boot_buffer_found = False
	998	boot_stack_found = False
	999
	1000	for vseg in self.globs:
	1001	if ( vseg.name == 'seg_boot_mapping' ):
	1002	boot_mapping_base = vseg.vbase
	1003	boot_mapping_size = vseg.vobjs[0].length
	1004	boot_mapping_ident = vseg.ident
	1005	boot_mapping_found = True
	1006
	1007	if ( vseg.name == 'seg_boot_code' ):
	1008	boot_code_base = vseg.vbase
	1009	boot_code_size = vseg.vobjs[0].length
	1010	boot_code_ident = vseg.ident
	1011	boot_code_found = True
	1012
	1013	if ( vseg.name == 'seg_boot_data' ):
	1014	boot_data_base = vseg.vbase
	1015	boot_data_size = vseg.vobjs[0].length
	1016	boot_data_ident = vseg.ident
	1017	boot_data_found = True
	1018
	1019	if ( vseg.name == 'seg_boot_buffer' ):
	1020	boot_buffer_base = vseg.vbase
	1021	boot_buffer_size = vseg.vobjs[0].length
	1022	boot_buffer_ident = vseg.ident
	1023	boot_buffer_found = True
	1024
	1025	if ( vseg.name == 'seg_boot_stack' ):
	1026	boot_stack_base = vseg.vbase
	1027	boot_stack_size = vseg.vobjs[0].length
	1028	boot_stack_ident = vseg.ident
	1029	boot_stack_found = True
	1030
[328]	1031	# check that BOOT vsegs are found and identity mapping
[319]	1032	if ( (boot_mapping_found == False) or (boot_mapping_ident == False) ):
	1033	print 'error in hard_config() : seg_boot_mapping missing or not ident'
	1034	sys.exit()
	1035
	1036	if ( (boot_code_found == False) or (boot_code_ident == False) ):
	1037	print 'error in hard_config() : seg_boot_code missing or not ident'
	1038	sys.exit()
	1039
	1040	if ( (boot_data_found == False) or (boot_data_ident == False) ):
	1041	print 'error in hard_config() : seg_boot_data missing or not ident'
	1042	sys.exit()
	1043
	1044	if ( (boot_buffer_found == False) or (boot_buffer_ident == False) ):
	1045	print 'error in hard_config() : seg_boot_buffer missing or not ident'
	1046	sys.exit()
	1047
	1048	if ( (boot_stack_found == False) or (boot_stack_ident == False) ):
	1049	print 'error in giet_vsegs() : seg_boot_stack missing or not ident'
	1050	sys.exit()
	1051
	1052	# Search RAMDISK global vseg if required
	1053	seg_rdk_base = 0xFFFFFFFF
	1054	seg_rdk_size = 0
	1055	seg_rdk_found = False
	1056
	1057	if self.use_ramdisk:
	1058	for vseg in self.globs:
	1059	if ( vseg.name == 'seg_ramdisk' ):
	1060	seg_rdk_base = vseg.vbase
	1061	seg_rdk_size = vseg.vobjs[0].length
	1062	seg_rdk_found = True
	1063
	1064	if ( seg_rdk_found == False ):
	1065	print 'Error in hard_config() "seg_ramdisk" not found'
	1066	sys.exit(1)
	1067
	1068	# build string
[327]	1069	s = '/* Generated by genmap for %s */\n' % self.name
[319]	1070	s += '\n'
	1071	s += '#ifndef HARD_CONFIG_H\n'
	1072	s += '#define HARD_CONFIG_H\n'
	1073	s += '\n'
	1074
	1075	s += '/* General platform parameters */\n'
	1076	s += '\n'
	1077	s += '#define X_SIZE %d\n' % self.x_size
	1078	s += '#define Y_SIZE %d\n' % self.y_size
	1079	s += '#define X_WIDTH %d\n' % self.x_width
	1080	s += '#define Y_WIDTH %d\n' % self.y_width
	1081	s += '#define X_IO %d\n' % self.x_io
	1082	s += '#define Y_IO %d\n' % self.y_io
	1083	s += '#define NB_PROCS_MAX %d\n' % self.procs_max
	1084	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
	1085	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
	1086	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
	1087	s += '\n'
	1088
	1089	s += '/* Peripherals */\n'
	1090	s += '\n'
	1091	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
	1092	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
	1093	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
	1094	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
	1095	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
	1096	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
	1097	s += '\n'
	1098	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
	1099	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
	1100	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
	1101	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
	1102	s += '\n'
	1103	s += '#define USE_IOC_BDV %d\n' % use_bdv
	1104	s += '#define USE_IOC_SPI %d\n' % use_spi
	1105	s += '#define USE_IOC_HBA %d\n' % use_hba
	1106	s += '\n'
	1107	s += '#define USE_RAMDISK %d\n' % self.use_ramdisk
	1108	s += '\n'
[328]	1109	s += '#define FBUF_X_SIZE %d\n' % fbf_arg
	1110	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg
	1111	s += '\n'
	1112	s += '#define XCU_NB_INPUTS %d\n' % xcu_arg
	1113	s += '\n'
[319]	1114
	1115	s += '/* physical base addresses for peripherals */\n'
	1116	s += '\n'
	1117	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
	1118	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
	1119	s += '\n'
	1120	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
[341]	1121	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
[319]	1122	s += '\n'
	1123	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
[341]	1124	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
[319]	1125	s += '\n'
	1126	s += '#define SEG_ICU_BASE 0x%x\n' % seg_icu_base
[341]	1127	s += '#define SEG_ICU_SIZE 0x%x\n' % seg_icu_size
[319]	1128	s += '\n'
	1129	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
[341]	1130	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
[319]	1131	s += '\n'
	1132	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
	1133	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
	1134	s += '\n'
	1135	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
	1136	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
	1137	s += '\n'
	1138	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
	1139	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
	1140	s += '\n'
	1141	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
	1142	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
	1143	s += '\n'
	1144	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
	1145	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
	1146	s += '\n'
	1147	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
	1148	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
	1149	s += '\n'
	1150	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
	1151	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
	1152	s += '\n'
	1153	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
	1154	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
	1155	s += '\n'
	1156	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
	1157	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
	1158	s += '\n'
	1159	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
	1160	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
	1161	s += '\n'
	1162	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
	1163	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
	1164	s += '\n'
[328]	1165	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
[319]	1166	s += '\n'
	1167
[326]	1168	s += '/* physical base addresses for identity mapped vsegs */\n'
	1169	s += '/* used by the GietVM OS */\n'
[319]	1170	s += '\n'
	1171	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
	1172	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
	1173	s += '\n'
	1174	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
	1175	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
	1176	s += '\n'
	1177	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
	1178	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
	1179	s += '\n'
	1180	s += '#define SEG_BOOT_BUFFER_BASE 0x%x\n' % boot_buffer_base
	1181	s += '#define SEG_BOOT_BUFFER_SIZE 0x%x\n' % boot_buffer_size
	1182	s += '\n'
	1183	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
	1184	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
	1185	s += '#endif\n'
	1186
	1187	return s
	1188
	1189	# end of hard_config()
	1190
	1191	#######################
	1192	def netbsd_dts( self ): # compute string for netbsd.dts file generation,
	1193	# used for netbsd configuration
	1194	# header
	1195	s = '/dts-v1/;\n'
	1196	s += '\n'
	1197	s += '/{\n'
	1198	s += ' #address-cells = <2>;\n'
	1199	s += ' #size-cells = <1>;\n'
	1200
	1201	# cpus (for each cluster)
	1202	s += ' cpus {\n'
	1203	s += ' #address-cells = <1>;\n'
	1204	s += ' #size-cells = <0>;\n'
	1205
	1206	for cluster in self.clusters:
	1207	for proc in cluster.procs:
	1208	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + proc.lpid
	1209
	1210	s += ' Mips,32@0x%x {\n' % proc_id
	1211	s += ' device_type = "cpu";\n'
	1212	s += ' icudev_type = "cpu:mips";\n'
	1213	s += ' name = "Mips,32";\n'
	1214	s += ' reg = <0x%x>;\n' % proc_id
	1215	s += ' };\n'
	1216	s += '\n'
	1217
	1218	s += ' };\n'
	1219
	1220	# rams (for each cluster)
	1221	for cluster in self.clusters:
	1222	for pseg in cluster.psegs:
	1223
	1224	if ( pseg.segtype == 'RAM' ):
	1225	msb = pseg.base >> 32
	1226	lsb = pseg.base & 0xFFFFFFFF
	1227	size = pseg.size
	1228
	1229	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
	1230	s += ' cached = <1>;\n'
	1231	s += ' device_type = "memory";\n'
	1232	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1233	s += ' };\n'
	1234
	1235	# peripherals (for each cluster)
	1236	for cluster in self.clusters:
	1237
	1238	# research XCU component
	1239	found_xcu = False
	1240	for periph in cluster.periphs:
	1241	if ( (periph.ptype == 'XCU') ):
	1242	found_xcu = True
	1243	xcu = periph
	1244	msb = periph.pseg.base >> 32
	1245	lsb = periph.pseg.base & 0xFFFFFFFF
	1246	size = periph.pseg.size
	1247
	1248	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1249	s += ' device_type = "soclib:xicu:root";\n'
	1250	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1251	s += ' input_lines = <%d>;\n' % periph.arg1
	1252	s += ' ipis = <%d>;\n' % periph.arg2
	1253	s += ' timers = <%d>;\n' % periph.arg3
	1254
	1255	output_id = 0 # output index from XCU
	1256	for lpid in xrange ( len(cluster.procs) ): # destination processor index
	1257	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
	1258	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + lpid
	1259	s += ' out@%d {\n' % output_id
	1260	s += ' device_type = "soclib:xicu:filter";\n'
	1261	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
	1262	s += ' output_line = <%d>;\n' % output_id
	1263	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1264	s += ' };\n'
	1265
	1266	output_id += 1
	1267
	1268	s += ' };\n'
	1269
	1270	# research PIC component
	1271	found_pic = False
	1272	for periph in cluster.periphs:
	1273	if ( periph.ptype == 'PIC' ):
	1274	found_pic = True
	1275	pic = periph
	1276	msb = periph.pseg.base >> 32
	1277	lsb = periph.pseg.base & 0xFFFFFFFF
	1278	size = periph.pseg.size
	1279
	1280	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1281	s += ' device_type = "soclib:pic:root";\n'
	1282	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1283	s += ' input_lines = <%d>;\n' % periph.channels
	1284	s += ' };\n'
	1285
	1286	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
	1287	print 'error in netbsd_dts() : No XCU/PIC in cluster(%d,%d)' % (cluster.x, cluster.y)
	1288	sys.exit(1)
	1289
	1290	if ( found_pic == True ): irq_tgt = pic
	1291	else: irq_tgt = xcu
	1292
	1293	# get all others peripherals in cluster
	1294	for periph in cluster.periphs:
	1295	msb = periph.pseg.base >> 32
	1296	lsb = periph.pseg.base & 0xFFFFFFFF
	1297	size = periph.pseg.size
	1298
	1299	# research DMA component
	1300	if ( periph.ptype == 'DMA' ):
	1301
	1302	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1303	s += ' device_type = "soclib:dma";\n'
	1304	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1305	s += ' channel_count = <%d>;\n' % periph.channels
	1306
	1307	# multi-channels : get HWI index (to XCU) for each channel
	1308	for channel in xrange( periph.channels ):
	1309	hwi_id = 0xFFFFFFFF
	1310	for irq in xcu.irqs:
	1311	if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ):
	1312	hwi_id = irq.srcid
	1313	if ( hwi_id == 0xFFFFFFFF ):
	1314	print 'error in netbsd.dts() ISR_DMA channel %d not found' % channel
	1315	sys.exit(1)
	1316
	1317	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
	1318	s += ' irq@%d{\n' % channel
	1319	s += ' device_type = "soclib:periph:irq";\n'
	1320	s += ' output_line = <%d>;\n' % channel
	1321	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1322	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1323	s += ' };\n'
	1324
	1325	s += ' };\n'
	1326
	1327	# research MMC component
	1328	elif ( periph.ptype == 'MMC' ):
	1329
	1330	# get irq line index associated to MMC in XCU
	1331	irq_in = 0xFFFFFFFF
	1332	for irq in xcu.irqs:
	1333	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
	1334	if ( irq_in == 0xFFFFFFFF ):
	1335	print 'error in netbsd.dts() ISR_MMC not found'
	1336	sys.exit(1)
	1337
	1338	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1339	s += ' device_type = "soclib:mmc";\n'
	1340	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1341	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1342	s += ' };\n'
	1343
	1344	# research FBF component
	1345	elif ( periph.ptype == 'FBF' ):
	1346
	1347	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1348	s += ' device_type = "soclib:framebuffer";\n'
	1349	s += ' mode = <32>;\n' # bits par pixel
	1350	s += ' width = <%d>;\n' % periph.arg1
	1351	s += ' height = <%d>;\n' % periph.arg2
	1352	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1353	s += ' };\n'
	1354
	1355	# research IOC component
	1356	elif ( periph.ptype == 'IOC' ):
	1357
	1358	if ( periph.subtype == 'BDV' ):
	1359
	1360	# get irq line index associated to bdv
	1361	irq_in = 0xFFFFFFFF
	1362	for irq in irq_tgt.irqs:
	1363	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
	1364	if ( irq_in == 0xFFFFFFFF ):
	1365	print 'error in netbsd.dts() ISR_BDV not found'
	1366	sys.exit(1)
	1367
	1368	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1369	s += ' device_type = "soclib:blockdevice";\n'
	1370	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1371	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1372	s += ' };\n'
	1373
	1374	elif ( periph.subtype == 'HBA' ):
	1375	print 'error in netbsd_dts() : HBA peripheral not supported by NetBSD'
	1376	sys.exit(1)
	1377
	1378	elif ( periph.subtype == 'SPI' ):
	1379
	1380	# get irq line index associated to spi
	1381	irq_in = 0xFFFFFFFF
	1382	for irq in irq_tgt.irqs:
	1383	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
	1384	if ( irq_in == 0xFFFFFFFF ):
	1385	print 'error in netbsd.dts() ISR_SPI not found'
	1386	sys.exit(1)
	1387
	1388	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1389	s += ' device_type = "soclib:spi";\n'
	1390	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1391	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1392	s += ' };\n'
	1393
	1394	# research ROM component
	1395	elif ( periph.ptype == 'ROM' ):
	1396
	1397	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1398	s += ' device_type = "rom";\n'
	1399	s += ' cached = <1>;\n'
	1400	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1401	s += ' };\n'
	1402
	1403	# research SIM component
	1404	elif ( periph.ptype == 'SIM' ):
	1405
	1406	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1407	s += ' device_type = "soclib:simhelper";\n'
	1408	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1409	s += ' };\n'
	1410
	1411	# research TTY component
	1412	elif ( periph.ptype == 'TTY' ):
	1413
	1414	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1415	s += ' device_type = "soclib:tty";\n'
	1416	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1417	s += ' channel_count = < %d >;\n' % periph.channels
	1418
	1419	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1420	for channel in xrange( periph.channels ):
	1421	hwi_id = 0xFFFFFFFF
	1422	for irq in irq_tgt.irqs:
	1423	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
	1424	hwi_id = irq.srcid
	1425	if ( hwi_id == 0xFFFFFFFF ):
	1426	print 'error in netbsd.dts() ISR_TTY_RX channel %d not found' % channel
	1427	sys.exit(1)
	1428
	1429	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1430	s += ' irq@%d{\n' % channel
	1431	s += ' device_type = "soclib:periph:irq";\n'
	1432	s += ' output_line = <%d>;\n' % channel
	1433	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1434	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1435	s += ' };\n'
	1436
	1437	s += ' };\n'
	1438
	1439	# research IOB component
	1440	elif ( periph.ptype == 'IOB' ):
	1441
	1442	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1443	s += ' device_type = "soclib:iob";\n'
	1444	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1445	s += ' };\n'
	1446
	1447	# research NIC component
	1448	elif ( periph.ptype == 'NIC' ):
	1449
	1450	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1451	s += ' device_type = "soclib:nic";\n'
	1452	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1453	s += ' channel_count = < %d >;\n' % periph.channels
	1454
	1455	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
	1456	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
	1457	for channel in xrange( periph.channels ):
	1458	hwi_id = 0xFFFFFFFF
	1459	for irq in irq_tgt.irqs:
	1460	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
	1461	hwi_id = irq.srcid
	1462	if ( hwi_id == 0xFFFFFFFF ):
	1463	print 'error in netbsd.dts() ISR_NIC_RX channel %d not found' % channel
	1464	sys.exit(1)
	1465
	1466	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1467	s += ' irq_rx@%d{\n' % channel
	1468	s += ' device_type = "soclib:periph:irq";\n'
	1469	s += ' output_line = <%d>;\n' % (2*channel)
	1470	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1471	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1472	s += ' };\n'
	1473
	1474	hwi_id = 0xFFFFFFFF
	1475	for irq in irq_tgt.irqs:
	1476	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
	1477	hwi_id = irq.srcid
	1478	if ( hwi_id == 0xFFFFFFFF ):
	1479	print 'error in netbsd.dts() ISR_NIC_TX channel %d not found' % channel
	1480	sys.exit(1)
	1481
	1482	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1483	s += ' irq_tx@%d{\n' % channel
	1484	s += ' device_type = "soclib:periph:irq";\n'
	1485	s += ' output_line = <%d>;\n' % (2*channel + 1)
	1486	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1487	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1488	s += ' };\n'
	1489
	1490	s += ' };\n'
	1491
	1492	# research CMA component
	1493	elif ( periph.ptype == 'CMA' ):
	1494
	1495	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1496	s += ' device_type = "soclib:cma";\n'
	1497	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1498	s += ' channel_count = < %d >;\n' % periph.channels
	1499
	1500	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1501	for channel in xrange( periph.channels ):
	1502	hwi_id = 0xFFFFFFFF
	1503	for irq in irq_tgt.irqs:
	1504	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
	1505	hwi_id = irq.srcid
	1506	if ( hwi_id == 0xFFFFFFFF ):
	1507	print 'error in netbsd.dts() ISR_CMA channel %d not found' % channel
	1508	sys.exit(1)
	1509
	1510	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1511	s += ' irq@%d{\n' % channel
	1512	s += ' device_type = "soclib:periph:irq";\n'
	1513	s += ' output_line = <%d>;\n' % channel
	1514	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1515	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1516	s += ' };\n'
	1517
	1518	s += ' };\n'
	1519
	1520	# research TIM component
	1521	elif ( periph.ptype == 'TIM' ):
	1522
	1523	print 'error in netbsd_dts() : TIM peripheral not supported by NetBSD'
	1524	sys.exit(1)
	1525
	1526	# research MWR component
	1527	elif ( periph.ptype == 'MWR' ):
	1528
	1529	print 'error in netbsd_dts() : MWR peripheral not supported by NetBSD'
	1530	sys.exit(1)
	1531
	1532	# research ICU component
	1533	elif ( periph.ptype == 'ICU' ):
	1534	print 'error in netbsd_dts() : ICU peripheral not supported by NetBSD'
	1535	sys.exit(1)
	1536
	1537	# topology
	1538	s += '\n'
	1539	s += ' topology {\n'
	1540	s += ' #address-cells = <2>;\n'
	1541	s += ' #size-cells = <0>;\n'
	1542	for cluster in self.clusters:
	1543	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
	1544	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
	1545	s += ' devices = <\n'
	1546
	1547	offset = ((cluster.x << self.y_width) + cluster.y) * self.procs_max
	1548	for proc in cluster.procs:
	1549	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
	1550	for periph in cluster.periphs:
	1551	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
	1552
	1553	s += ' >;\n'
	1554	s += ' };\n'
	1555	s += ' };\n'
	1556	s += '};\n'
	1557
	1558	return s
	1559	# end netbsd_dts( )
	1560
	1561	###########################
	1562	def almos_archinfo( self ): # compute string for arch.info file generation,
	1563	# used for almos configuration
	1564	# header
[327]	1565	s = '# arch.info file generated by genmap for %s\n' % self.name
[319]	1566	s += '\n'
	1567	s += '[HEADER]\n'
	1568	s += ' REVISION=1\n'
	1569	s += ' ARCH=%s\n' % self.name
	1570	s += ' XMAX=%d\n' % self.x_size
	1571	s += ' YMAX=%d\n' % self.y_size
	1572	s += ' CPU_NR=%d\n' % self.procs_max
	1573	s += '\n'
	1574
	1575	# clusters
	1576	cluster_id = 0
	1577	for cluster in self.clusters:
	1578
	1579	ram = None
	1580	nb_cpus = len( cluster.procs )
	1581	nb_devs = len( cluster.periphs )
	1582	if ( len( cluster.coprocs ) != 0 ):
	1583	print 'Error in almos_archinfo() coprocessors not supported yet'
	1584	sys.exit(1)
	1585
	1586	# search a RAM
	1587	for pseg in cluster.psegs:
	1588	if ( pseg.segtype == 'RAM' ):
	1589	ram = pseg
	1590	nb_devs += 1
	1591
	1592	# search XCU to get IRQs indexes if cluster contains peripherals
	1593	if ( len( cluster.periphs ) != 0 ):
	1594	tty_irq_id = None
	1595	bdv_irq_id = None
	1596	dma_irq_id = None
	1597
	1598	for periph in cluster.periphs:
	1599	if ( periph.ptype == 'XCU' ):
	1600	# scan irqs
	1601	for irq in periph.irqs:
	1602	if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid
	1603	if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid
	1604	if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid
	1605
	1606	# Build the cluster description
	1607	s += '[CLUSTER]\n'
	1608	s += ' CID=%d\n' % cluster_id
	1609	s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y)
	1610	s += ' CPU_NR=%d\n' % nb_cpus
	1611	s += ' DEV_NR=%d\n' % nb_devs
	1612
	1613
	1614	# Handling RAM when cluster contain a RAM
	1615	if (ram != None ):
	1616	base = ram.base
	1617	size = ram.size
	1618	irqid = -1
	1619	s += ' DEVID=RAM'
	1620	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1621
	1622	# Handling peripherals
	1623	for periph in cluster.periphs:
	1624	base = periph.pseg.base
	1625	size = periph.pseg.size
	1626
	1627	if ( periph.ptype == 'XCU' ):
	1628
	1629	s += ' DEVID=XICU'
	1630	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1631
	1632	elif ( (periph.ptype == 'TTY')
	1633	and (tty_irq_id != None) ):
	1634
	1635	s += ' DEVID=TTY'
	1636	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id )
	1637
	1638	elif ( (periph.ptype == 'DMA')
	1639	and (dma_irq_id != None) ):
	1640
	1641	s += ' DEVID=DMA'
	1642	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id )
	1643
	1644	elif ( periph.ptype == 'FBF' ):
	1645
	1646	s += ' DEVID=FB'
	1647	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1648
	1649	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
	1650	and (bdv_irq_id != None) ):
	1651
	1652	s += ' DEVID=BLKDEV'
	1653	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id )
	1654
	1655	elif ( periph.ptype == 'PIC' ):
	1656
	1657	s += ' DEVID=IOPIC'
	1658	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1659
	1660	else:
	1661	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
	1662	% (cluster.x, cluster.y)
	1663	print '# peripheral type %s/%s not supported yet\n' \
	1664	% ( periph.ptype, periph.subtype )
	1665
	1666	cluster_id += 1
	1667
	1668	return s
	1669
	1670	# end of almos_archinfo()
	1671
	1672
	1673
	1674
	1675
	1676
	1677
	1678
	1679	###########################################################################################
	1680	class Cluster ( object ):
	1681	###########################################################################################
	1682	def __init__( self,
	1683	x,
	1684	y ):
	1685
	1686	self.index = 0 # global index (set by Mapping constructor)
	1687	self.x = x # x coordinate
	1688	self.y = y # y coordinate
	1689	self.psegs = [] # filled by addRam() or addPeriph()
	1690	self.procs = [] # filled by addProc()
	1691	self.coprocs = [] # filled by addCoproc()
	1692	self.periphs = [] # filled by addPeriph()
	1693
	1694	return
	1695
	1696	################
	1697	def xml( self ): # xml for a cluster
	1698
	1699	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
	1700	for pseg in self.psegs: s += pseg.xml()
	1701	for proc in self.procs: s += proc.xml()
	1702	for copr in self.coprocs: s += copr.xml()
	1703	for peri in self.periphs: s += peri.xml()
	1704	s += ' </cluster>\n'
	1705
	1706	return s
	1707
	1708	#############################################
	1709	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
	1710
	1711	if ( verbose ):
	1712	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
	1713
	1714	# check index
	1715	if (self.index != expected):
	1716	print 'error in Cluster.cbin() : cluster global index = %d / expected = %d' \
	1717	% (self.index, expected )
	1718	sys.exit(1)
	1719
	1720	# compute global index for first pseg
	1721	if ( len(self.psegs) > 0 ):
	1722	pseg_id = self.psegs[0].index
	1723	else:
	1724	pseg_id = 0
	1725
	1726	# compute global index for first proc
	1727	if ( len(self.procs) > 0 ):
	1728	proc_id = self.procs[0].index
	1729	else:
	1730	proc_id = 0
	1731
	1732	# compute global index for first coproc
	1733	if ( len(self.coprocs) > 0 ):
	1734	coproc_id = self.coprocs[0].index
	1735	else:
	1736	coproc_id = 0
	1737
	1738	# compute global index for first periph
	1739	if ( len(self.periphs) > 0 ):
	1740	periph_id = self.periphs[0].index
	1741	else:
	1742	periph_id = 0
	1743
	1744	byte_stream = bytearray()
	1745	byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate
	1746	byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate
	1747	byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number of psegs in cluster
	1748	byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index
	1749	byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number of procs in cluster
	1750	byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index
	1751	byte_stream += mapping.int2bytes( 4 , len( self.coprocs ) ) # number of coprocs in cluster
	1752	byte_stream += mapping.int2bytes( 4 , coproc_id ) # first coproc global index
	1753	byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number of periphs in cluster
	1754	byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index
	1755
	1756	if ( verbose ):
	1757	print 'nb_psegs = %d' % len( self.psegs )
	1758	print 'pseg_id = %d' % pseg_id
	1759	print 'nb_procs = %d' % len( self.procs )
	1760	print 'proc_id = %d' % proc_id
	1761	print 'nb_coprocs = %d' % len( self.coprocs )
	1762	print 'coproc_id = %d' % coproc_id
	1763	print 'nb_periphs = %d' % len( self.periphs )
	1764	print 'periph_id = %d' % periph_id
	1765
	1766	return byte_stream
	1767
	1768	###########################################################################################
[305]	1769	class Vspace( object ):
[319]	1770	###########################################################################################
	1771	def __init__( self,
	1772	name,
	1773	startname ):
	1774
	1775	self.index = 0 # global index ( set by addVspace() )
	1776	self.name = name # vspace name
[305]	1777	self.startname = startname # name of vobj containing the start_vector
[319]	1778	self.vsegs = []
[305]	1779	self.tasks = []
	1780
	1781	return
	1782
[319]	1783	################
	1784	def xml( self ): # xml for one vspace
	1785
[305]	1786	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
[319]	1787	for vseg in self.vsegs: s += vseg.xml()
	1788	for task in self.tasks: s += task.xml()
[305]	1789	s += ' </vspace>\n'
[319]	1790
[305]	1791	return s
	1792
[319]	1793	#############################################
	1794	def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace
	1795
	1796	if ( verbose ):
	1797	print '*** cbin for vspace %s' % (self.name)
	1798
	1799	# check index
	1800	if (self.index != expected):
	1801	print 'error in Vspace.cbin() : vspace global index = %d / expected = %d' \
	1802	% (self.index, expected )
	1803	sys.exit(1)
	1804
	1805	# compute global index for vobj containing start_vector
	1806	vobj_start_id = 0xFFFFFFFF
	1807	for vseg in self.vsegs:
	1808	if ( vseg.vobjs[0].name == self.startname ):
	1809	vobj_start_id = vseg.vobjs[0].index
	1810	if ( vobj_start_id == 0xFFFFFFFF ):
	1811	print 'error in Vspace.cbin() : startname %s not found for vspace %s' \
	1812	% ( self.startname, self.name )
	1813	sys.exit(1)
	1814
	1815	# compute first vseg, vobj, task global index
	1816	first_vseg_id = self.vsegs[0].index
	1817	first_vobj_id = self.vsegs[0].vobjs[0].index
	1818	first_task_id = self.tasks[0].index
	1819
	1820	# compute number of vobjs, tasks, vsegs
	1821	nb_vsegs = len( self.vsegs )
	1822	nb_tasks = len( self.tasks )
	1823	nb_vobjs = 0
	1824	for vseg in self.vsegs:
	1825	nb_vobjs += len( vseg.vobjs )
	1826
	1827	byte_stream = bytearray()
	1828	byte_stream += mapping.str2bytes( 32, self.name ) # vspace name
	1829	byte_stream += mapping.int2bytes( 4, vobj_start_id ) # vobj start_vector
	1830	byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs
	1831	byte_stream += mapping.int2bytes( 4, nb_vobjs ) # number of vobjs
	1832	byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks
	1833	byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index
	1834	byte_stream += mapping.int2bytes( 4, first_vobj_id ) # first vobj global index
	1835	byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index
	1836
	1837	if ( verbose ):
	1838	print 'start_id = %d' % vobj_start_id
	1839	print 'nb_vsegs = %d' % nb_vsegs
	1840	print 'nb_vobjs = %d' % nb_vobjs
	1841	print 'nb_tasks = %d' % nb_tasks
	1842	print 'vseg_id = %d' % first_vseg_id
	1843	print 'vobj_id = %d' % first_vobj_id
	1844	print 'task_id = %d' % first_task_id
	1845
	1846	return byte_stream
	1847
	1848	###########################################################################################
[305]	1849	class Task( object ):
[319]	1850	###########################################################################################
	1851	def __init__( self,
	1852	name,
	1853	trdid,
	1854	x,
	1855	y,
	1856	p,
	1857	stackname,
	1858	heapname,
	1859	startid,
	1860	usetty = False,
	1861	usenic = False,
	1862	usecma = False,
	1863	usehba = False,
	1864	usetim = False ):
	1865
	1866	self.index = 0 # global index value set by addTask()
	1867	self.name = name # tsk name
	1868	self.trdid = trdid # task index (unique in vspace)
	1869	self.x = x # cluster x coordinate
	1870	self.y = y # cluster y coordinate
	1871	self.p = p # processor local index
	1872	self.stackname = stackname # name of vobj containing the stack
	1873	self.heapname = heapname # name of vobj containing the heap
	1874	self.startid = startid # index in start_vector
	1875	self.usetty = usetty # request a private TTY channel
	1876	self.usenic = usenic # request a private NIC channel
	1877	self.usecma = usecma # request a private CMA channel
	1878	self.usehba = usehba # request a private HBA channel
	1879	self.usetim = usetim # request a private TIM channel
[305]	1880	return
	1881
[319]	1882	################
	1883	def xml( self ): # xml for one task
	1884
	1885	s = ' <task name="%s"' % self.name
	1886	s += ' trdid="%d"' % self.trdid
	1887	s += ' x="%d"' % self.x
	1888	s += ' y="%d"' % self.y
	1889	s += ' p="%d"' % self.p
	1890	s += ' stackname="%s"' % self.stackname
	1891	s += ' heapname="%s"' % self.heapname
	1892	s += ' startid="%d"' % self.startid
	1893	if self.usetty != 0: s += ' usetty="1"'
	1894	if self.usenic != 0: s += ' usenic="1"'
	1895	if self.usecma != 0: s += ' usehba="1"'
	1896	if self.usehba != 0: s += ' usehba="1"'
	1897	if self.usetim != 0: s += ' usehba="1"'
[305]	1898	s += ' />\n'
[319]	1899
[305]	1900	return s
	1901
[319]	1902	#####################################################
	1903	def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task
	1904
	1905	if ( verbose ):
	1906	print '*** cbin for task %s in vspace %s' % (self.name, vspace.name)
	1907
	1908	# check index
	1909	if (self.index != expected):
	1910	print 'error in Task.cbin() : task global index = %d / expected = %d' \
	1911	% (self.index, expected )
	1912	sys.exit(1)
	1913
	1914	# compute cluster global index
	1915	cluster_id = (self.x * mapping.y_size) + self.y
	1916
	1917	# compute vobj local index for stack
	1918	vobj_stack_id = 0xFFFFFFFF
	1919	for vseg in vspace.vsegs:
	1920	if ( vseg.vobjs[0].name == self.stackname ):
	1921	vobj_stack_id = vseg.vobjs[0].index
	1922	if ( vobj_stack_id == 0xFFFFFFFF ):
	1923	print 'error in Task.cbin() : stackname %s not found for task %s in vspace %s' \
	1924	% ( self.stackname, self.name, vspace.name )
	1925	sys.exit(1)
	1926
	1927	# compute vobj local index for heap
	1928	vobj_heap_id = 0xFFFFFFFF
	1929	for vseg in vspace.vsegs:
	1930	if ( vseg.vobjs[0].name == self.heapname ):
	1931	vobj_heap_id = vseg.vobjs[0].index
	1932	if ( vobj_heap_id == 0xFFFFFFFF ):
	1933	print 'error in Task.cbin() : heapname %s not found for task %s in vspace %s' \
	1934	% ( self.heapname, self.name, vspace.name )
	1935	sys.exit(1)
	1936
	1937	byte_stream = bytearray()
	1938	byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace
	1939	byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index
	1940	byte_stream += mapping.int2bytes( 4, self.p ) # processor local index in cluster
	1941	byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace
	1942	byte_stream += mapping.int2bytes( 4, vobj_stack_id ) # stack vobj local index
	1943	byte_stream += mapping.int2bytes( 4, vobj_heap_id ) # heap vobj local index
	1944	byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector
	1945	byte_stream += mapping.int2bytes( 4, self.usetty ) # TTY channel required
	1946	byte_stream += mapping.int2bytes( 4, self.usenic ) # NIC channel required
	1947	byte_stream += mapping.int2bytes( 4, self.usecma ) # CMA channel required
	1948	byte_stream += mapping.int2bytes( 4, self.usehba ) # IOC channel required
	1949	byte_stream += mapping.int2bytes( 4, self.usetim ) # TIM channel required
	1950
	1951	if ( verbose ):
	1952	print 'clusterid = %d' % cluster_id
	1953	print 'lpid = %d' % self.p
	1954	print 'trdid = %d' % self.trdid
	1955	print 'stackid = %d' % vobj_stack_id
	1956	print 'heapid = %d' % vobj_heap_id
	1957	print 'startid = %d' % self.startid
	1958
	1959	return byte_stream
	1960
	1961	###########################################################################################
[305]	1962	class Vseg( object ):
[319]	1963	###########################################################################################
	1964	def __init__( self,
	1965	name,
	1966	vbase,
	1967	mode,
	1968	x,
	1969	y,
	1970	psegname,
	1971	ident = False ):
[305]	1972
[319]	1973	assert mode in VSEGMODES
	1974
	1975	self.index = 0 # global index ( set by addVseg() )
	1976	self.name = name # vseg name
	1977	self.vbase = vbase & 0xFFFFFFFF # virtual base address in vspace
	1978	self.mode = mode # CXWU access rights
	1979	self.x = x # x coordinate of destination cluster
	1980	self.y = y # y coordinate of destination cluster
	1981	self.psegname = psegname # name of pseg in destination cluster
	1982	self.ident = ident # identity mapping required
	1983	self.vobjs = []
[305]	1984	return
	1985
[319]	1986	################
	1987	def xml( self ): # xml for one vseg
	1988
	1989	s = ' <vseg name="%s" vbase="0x%x" mode="%s" x="%d" y="%d" psegname="%s"' \
	1990	% ( self.name, self.vbase, self.mode, self.x, self.y, self.psegname )
	1991	if ( self.ident ): s += ' ident="1" >\n'
	1992	else: s += ' >\n'
	1993	for vobj in self.vobjs: s += vobj.xml()
	1994	s += ' </vseg>\n'
	1995
[305]	1996	return s
	1997
[319]	1998	#############################################
	1999	def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg
	2000
	2001	if ( verbose ):
	2002	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
	2003
	2004	# check index
	2005	if (self.index != expected):
	2006	print 'error in Vseg.cbin() : vseg global index = %d / expected = %d' \
	2007	% (self.index, expected )
	2008	sys.exit(1)
	2009
	2010	# compute pseg_id
	2011	pseg_id = 0xFFFFFFFF
	2012	cluster_id = (self.x * mapping.y_size) + self.y
	2013	cluster = mapping.clusters[cluster_id]
	2014	for pseg in cluster.psegs:
	2015	if (self.psegname == pseg.name):
	2016	pseg_id = pseg.index
	2017	if (pseg_id == 0xFFFFFFFF):
	2018	print 'error in Vseg.cbin() : psegname %s not found for vseg %s in cluster %d' \
	2019	% ( self.psegname, self.name, cluster_id )
	2020	sys.exit(1)
	2021
	2022	# compute numerical value for mode
	2023	mode_id = 0xFFFFFFFF
	2024	for x in xrange( len(VSEGMODES) ):
	2025	if ( self.mode == VSEGMODES[x] ):
	2026	mode_id = x
	2027	if ( mode_id == 0xFFFFFFFF ):
	2028	print 'error in Vseg.cbin() : undefined vseg mode %s' % self.mode
	2029	sys.exit(1)
	2030
	2031	# compute vobj_id
	2032	vobj_id = self.vobjs[0].index
	2033
	2034	byte_stream = bytearray()
	2035	byte_stream += mapping.str2bytes( 32, self.name ) # vseg name
	2036	byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address
	2037	byte_stream += mapping.int2bytes( 8, 0 ) # physical base address
	2038	byte_stream += mapping.int2bytes( 4, 0 ) # vseg size (bytes)
	2039	byte_stream += mapping.int2bytes( 4, pseg_id ) # physical segment global index
	2040	byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags
	2041	byte_stream += mapping.int2bytes( 4, len(self.vobjs) ) # number of vobjs in vseg
	2042	byte_stream += mapping.int2bytes( 4, vobj_id ) # first vobj global index
	2043	byte_stream += mapping.int2bytes( 4, 0 ) # linked list of vsegs on same pseg
	2044	byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero
	2045	byte_stream += mapping.int2bytes( 1, self.ident ) # identity mapping when non zero
	2046	byte_stream += mapping.int2bytes( 2, 0 ) # reserved (padding)
	2047
	2048	if ( verbose ):
	2049	print 'vbase = %x' % self.vbase
	2050	print 'pseg_id = %d' % pseg_id
	2051	print 'mode = %s' % self.mode
	2052	print 'nb_vobjs = %d' % len(self.vobjs)
	2053	print 'vobj_id = %d' % vobj_id
	2054
	2055	return byte_stream
	2056
	2057	###########################################################################################
[305]	2058	class Vobj( object ):
[319]	2059	###########################################################################################
	2060	def __init__( self,
	2061	name,
	2062	length,
	2063	vtype,
	2064	binpath = '',
	2065	align = 0,
	2066	init = 0 ):
	2067
[305]	2068	assert vtype in ['ELF','BLOB','PTAB','PERI','MWMR','LOCK', \
	2069	'BUFFER','BARRIER','CONST','MEMSPACE','SCHED']
[319]	2070
	2071	assert (vtype != 'ELF') or (binpath != '')
	2072
	2073	self.index = 0 # global index ( set by addVobj() )
	2074	self.name = name # vobj name (unique in vspace)
	2075	self.vtype = vtype # vobj type (defined in mapping_info.h)
	2076	self.length = length # vobj size (bytes)
	2077	self.binpath = binpath # pathname for (ELF type)
	2078	self.align = align # required alignment (logarithm of 2)
	2079	self.init = init # initialisation value (for BARRIER or MWMR types)
	2080
[305]	2081	return
	2082
[319]	2083	################
	2084	def xml( self ): # xml for a vobj
	2085
[305]	2086	s = ' <vobj name="%s" type="%s" length="0x%x"' \
	2087	% ( self.name, self.vtype, self.length )
[319]	2088	if (self.binpath != ''): s += ' binpath="%s"' % (self.binpath)
	2089	if (self.align != 0 ): s += ' align="%d"' % (self.align)
	2090	if (self.init != 0 ): s += ' init="%d"' % (self.init)
[305]	2091	s += ' />\n'
[319]	2092
[305]	2093	return s
	2094
[319]	2095	#############################################
	2096	def cbin( self, mapping, verbose, expected ): # C binary structure for Vobj
[305]	2097
[319]	2098	# check index
	2099	if (self.index != expected):
	2100	print 'error in Vobj.cbin() : vobj global index = %d / expected = %d' \
	2101	% (self.index, expected )
	2102	sys.exit(1)
	2103	elif ( verbose ):
	2104	print '*** cbin for vobj[%d] %s' % (self.index, self.name)
[305]	2105
[319]	2106	# compute numerical value for vtype
	2107	vtype_int = 0xFFFFFFFF
	2108	for x in xrange( len(VOBJTYPES) ):
	2109	if ( self.vtype == VOBJTYPES[x] ):
	2110	vtype_int = x
	2111	if ( vtype_int == 0xFFFFFFFF ):
	2112	print 'error in Vobj.cbin() : undefined vobj type %s' % self.vtype
	2113	sys.exit(1)
	2114
	2115	byte_stream = bytearray()
	2116	byte_stream += mapping.str2bytes( 32, self.name ) # vobj name
	2117	byte_stream += mapping.str2bytes( 64, self.binpath ) # pathname for .elf file
	2118	byte_stream += mapping.int2bytes( 4 , vtype_int ) # vobj type
	2119	byte_stream += mapping.int2bytes( 4 , self.length ) # vobj size
	2120	byte_stream += mapping.int2bytes( 4 , self.align ) # required alignment
	2121	byte_stream += mapping.int2bytes( 4 , 0 ) # virtual base address
	2122	byte_stream += mapping.int2bytes( 8 , 0 ) # physical base address
	2123	byte_stream += mapping.int2bytes( 4 , self.init ) # init value
	2124
	2125	if ( verbose ):
	2126	print 'binpath = %s' % self.binpath
	2127	print 'type = %s' % self.vtype
	2128	print 'length = %x' % self.length
	2129
	2130	return byte_stream
	2131
	2132	###########################################################################################
[305]	2133	class Processor ( object ):
[319]	2134	###########################################################################################
	2135	def __init__( self,
	2136	x,
	2137	y,
	2138	lpid ):
	2139
	2140	self.index = 0 # global index ( set by addProc() )
	2141	self.x = x # x cluster coordinate
	2142	self.y = y # y cluster coordinate
	2143	self.lpid = lpid # processor local index
	2144
[305]	2145	return
	2146
[319]	2147	################
	2148	def xml( self ): # xml for a processor
[305]	2149	return ' <proc index="%d" />\n' % (self.lpid)
	2150
[319]	2151	#############################################
	2152	def cbin( self, mapping, verbose, expected ): # C binary structure for Proc
	2153
	2154	if ( verbose ):
	2155	print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y)
	2156
	2157	# check index
	2158	if (self.index != expected):
	2159	print 'error in Proc.cbin() : proc global index = %d / expected = %d' \
	2160	% (self.index, expected )
	2161	sys.exit(1)
	2162
	2163	byte_stream = bytearray()
	2164	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
	2165
	2166	return byte_stream
	2167
	2168	###########################################################################################
[305]	2169	class Pseg ( object ):
[319]	2170	###########################################################################################
	2171	def __init__( self,
	2172	name,
	2173	base,
	2174	size,
	2175	x,
	2176	y,
	2177	segtype ):
	2178
	2179	assert( segtype in PSEGTYPES )
	2180
	2181	self.index = 0 # global index ( set by addPseg() )
	2182	self.name = name # pseg name (unique in cluster)
	2183	self.base = base # physical base address
	2184	self.size = size # segment size (bytes)
	2185	self.x = x # cluster x coordinate
	2186	self.y = y # cluster y coordinate
	2187	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
	2188
[305]	2189	return
	2190
[319]	2191	################
	2192	def xml( self ): # xml for a pseg
	2193
[305]	2194	return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
	2195	% (self.name, self.segtype, self.base, self.size)
	2196
[319]	2197	######################################################
	2198	def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg
	2199
	2200	if ( verbose ):
	2201	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
	2202	% (self.index, self.name, cluster.x, cluster.y)
	2203
	2204	# check index
	2205	if (self.index != expected):
	2206	print 'error in Pseg.cbin() : pseg global index = %d / expected = %d' \
	2207	% (self.index, expected )
	2208	sys.exit(1)
	2209
	2210	# compute numerical value for segtype
	2211	segtype_int = 0xFFFFFFFF
	2212	for x in xrange( len(PSEGTYPES) ):
	2213	if ( self.segtype == PSEGTYPES[x] ):
	2214	segtype_int = x
	2215	if ( segtype_int == 0xFFFFFFFF ):
	2216	print 'error in Pseg.cbin() : undefined segment type %s' % self.segtype
	2217	sys.exit(1)
	2218
	2219	byte_stream = bytearray()
	2220	byte_stream += mapping.str2bytes( 32, self.name ) # pseg name
	2221	byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address
	2222	byte_stream += mapping.int2bytes( 8 , self.size ) # segment length
	2223	byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type
	2224	byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index
	2225	byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs
	2226
	2227	if ( verbose ):
	2228	print 'pbase = %x' % self.base
	2229	print 'size = %x' % self.size
	2230	print 'type = %s' % self.segtype
	2231
	2232	return byte_stream
	2233
	2234	###########################################################################################
	2235	class Periph ( object ):
	2236	###########################################################################################
	2237	def __init__( self,
	2238	pseg, # associated pseg
	2239	ptype, # peripheral type
	2240	subtype = 'NONE', # peripheral subtype
	2241	channels = 1, # for multi-channels peripherals
	2242	arg = 0 ): # optional argument (semantic depends on ptype)
	2243
	2244	assert ptype in PERIPHTYPES
	2245
	2246	assert subtype in PERIPHSUBTYPES
	2247
	2248	self.index = 0 # global index ( set by addPeriph() )
	2249	self.channels = channels
	2250	self.ptype = ptype
	2251	self.subtype = subtype
	2252	self.arg = arg
	2253	self.pseg = pseg
	2254	self.irqs = []
[305]	2255	return
	2256
[319]	2257	################
	2258	def xml( self ): # xml for a periph
	2259
	2260	s = ' <periph type="%s"' % self.ptype
	2261	s += ' subtype="%s"' % self.subtype
	2262	s += ' psegname="%s"' % self.pseg.name
	2263	s += ' channels="%d"' % self.channels
	2264	s += ' arg="%d" >\n' % self.arg
	2265	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') or (self.ptype == 'ICU') ):
	2266	for irq in self.irqs: s += irq.xml()
[305]	2267	s += ' </periph>\n'
[319]	2268
[305]	2269	return s
	2270
[319]	2271	#############################################
	2272	def cbin( self, mapping, verbose, expected ): # C binary structure for Periph
[305]	2273
[319]	2274	if ( verbose ):
	2275	print '*** cbin for periph %s in cluster [%d,%d]' \
	2276	% (self.ptype, self.pseg.x, self.pseg.y)
[305]	2277
[319]	2278	# check index
	2279	if (self.index != expected):
	2280	print 'error in Periph.cbin() : periph global index = %d / expected = %d' \
	2281	% (self.index, expected )
	2282	sys.exit(1)
[305]	2283
[319]	2284	# compute pseg global index
	2285	pseg_id = self.pseg.index
[305]	2286
[319]	2287	# compute first irq global index
	2288	if ( len(self.irqs) > 0 ):
	2289	irq_id = self.irqs[0].index
	2290	else:
	2291	irq_id = 0
[305]	2292
[319]	2293	# compute numerical value for ptype
	2294	ptype_id = 0xFFFFFFFF
	2295	for x in xrange( len(PERIPHTYPES) ):
	2296	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
	2297	if ( ptype_id == 0xFFFFFFFF ):
	2298	print 'error in Periph.cbin() : undefined peripheral type %s' % self.ptype
	2299	sys.exit(1)
[305]	2300
[319]	2301	# compute numerical value for subtype
	2302	subtype_id = 0xFFFFFFFF
	2303	for x in xrange( len(PERIPHSUBTYPES) ):
	2304	if ( self.subtype == PERIPHSUBTYPES[x] ): subtype_id = x
[305]	2305
[319]	2306	# compute
	2307	byte_stream = bytearray()
	2308	byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type
	2309	byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype
	2310	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
	2311	byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels
	2312	byte_stream += mapping.int2bytes( 4 , self.arg ) # optionnal argument
	2313	byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs
	2314	byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index
[305]	2315
[319]	2316	if ( verbose ):
	2317	print 'ptype = %d' % ptype_id
	2318	print 'pseg_id = %d' % pseg_id
	2319	print 'nb_irqs = %d' % len( self.irqs )
	2320	print 'irq_id = %d' % irq_id
	2321	return byte_stream
[305]	2322
[319]	2323	###########################################################################################
	2324	class Irq ( object ):
	2325	###########################################################################################
	2326	def __init__( self,
	2327	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
	2328	srcid, # input IRQ index (for XCU or PIC)
	2329	isrtype, # Type of ISR to be executed
	2330	channel = 0 ): # channel index for multi-channel ISR
[305]	2331
[319]	2332	assert irqtype in IRQTYPES
	2333	assert isrtype in ISRTYPES
	2334	assert srcid < 32
[305]	2335
[319]	2336	self.index = 0 # global index ( set by addIrq() )
	2337	self.irqtype = irqtype # IRQ type
	2338	self.srcid = srcid # source IRQ index
	2339	self.isrtype = isrtype # ISR type
	2340	self.channel = channel # channel index (for multi-channels ISR)
[305]	2341	return
	2342
[319]	2343	################
	2344	def xml( self ): # xml for Irq
[305]	2345
[319]	2346	return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
	2347	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
[305]	2348
[319]	2349	#############################################
	2350	def cbin( self, mapping, verbose, expected ): # C binary structure for Irq
[305]	2351
[319]	2352	if ( verbose ):
	2353	print '*** cbin for irq[%d]' % (self.index)
[305]	2354
[319]	2355	# check index
	2356	if (self.index != expected):
	2357	print 'error in Irq.cbin() : irq global index = %d / expected = %d' \
	2358	% (self.index, expected )
	2359	sys.exit(1)
[305]	2360
[319]	2361	# compute numerical value for irqtype
	2362	irqtype_id = 0xFFFFFFFF
	2363	for x in xrange( len(IRQTYPES) ):
	2364	if ( self.irqtype == IRQTYPES[x] ):
	2365	irqtype_id = x
	2366	if ( irqtype_id == 0xFFFFFFFF ):
	2367	print 'error in Irq.cbin() : undefined irqtype %s' % self.irqtype
	2368	sys.exit(1)
[305]	2369
[319]	2370	# compute numerical value for isrtype
	2371	isrtype_id = 0xFFFFFFFF
	2372	for x in xrange( len(ISRTYPES) ):
	2373	if ( self.isrtype == ISRTYPES[x] ):
	2374	isrtype_id = x
	2375	if ( isrtype_id == 0xFFFFFFFF ):
	2376	print 'error in Irq.cbin() : undefined isrtype %s' % self.isrtype
	2377	sys.exit(1)
	2378
	2379	byte_stream = bytearray()
	2380	byte_stream += mapping.int2bytes( 4, irqtype_id )
	2381	byte_stream += mapping.int2bytes( 4, self.srcid )
	2382	byte_stream += mapping.int2bytes( 4, isrtype_id )
	2383	byte_stream += mapping.int2bytes( 4, self.channel )
	2384	byte_stream += mapping.int2bytes( 4, 0 )
	2385	byte_stream += mapping.int2bytes( 4, 0 )
	2386
	2387	if ( verbose ):
	2388	print 'irqtype = %s' % self.irqtype
	2389	print 'srcid = %d' % self.srcid
	2390	print 'isrtype = %s' % self.isrtype
	2391	print 'channel = %d' % self.channel
	2392
	2393	return byte_stream
	2394
	2395	###########################################################################################
	2396	class Coproc ( object ):
	2397	###########################################################################################
	2398	def __init__( self,
	2399	pseg ): # associated pseg
	2400
	2401	self.index = 0 # global index value set by addCoproc()
	2402	self.pseg = pseg
	2403	self.ports = []
	2404
[305]	2405	return
	2406
[319]	2407	################
	2408	def xml( self ): # xml for Coproc
[305]	2409
[319]	2410	print 'error in Coproc.xml() : not defined yet'
	2411	sys.exit(1)
	2412
	2413	return
	2414
	2415	#############################################
	2416	def cbin( self, mapping, verbose, expected ): # C binary structure for Coproc
	2417
	2418	if ( verbose ):
	2419	print '*** cbin for coproc in cluster (%d,%d)' % (self.pseg.x, self.pseg.y)
	2420
	2421	# check index
	2422	if (self.index != expected):
	2423	print 'error in Coproc.cbin() : coproc global index = %d / expected = %d' \
	2424	% (self.index, expected )
	2425	sys.exit(1)
	2426
	2427	# compute pseg global index
	2428	pseg_id = self.pseg.index
	2429
	2430	# compute first port global index
	2431	port_id = self.ports[0].index
	2432
	2433	byte_stream = bytearray()
	2434	byte_stream += mapping.str2bytes( 32, self.pseg.name ) # probablement inutile (AG)
	2435	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
	2436	byte_stream += mapping.int2bytes( 4 , len( self.ports ) ) # number of input irqs
	2437	byte_stream += mapping.int2bytes( 4 , port_id ) # first port global index
	2438
	2439	if ( verbose ):
	2440	print 'irqtype = %s' % self.irqtype
	2441	print 'pseg_id = %d' % pseg_id
	2442	print 'nb_ports = %d' % len( self.ports )
	2443	print 'port_id %d' % port_id
	2444
	2445	return byte_stream
	2446
	2447	###########################################################################################
	2448	class Cpport ( object ):
	2449	###########################################################################################
	2450	def __init__( self,
	2451	direction,
	2452	vspacename,
	2453	mwmrname ):
	2454
	2455	self.index = 0 # global index ( set by addCpport() )
	2456	self.direction = direction # TO_COPROC / FROM_COPROC
	2457	self.vspacename = vspacename # name of vspace containing mwmr channel
	2458	self.mwmrname = mwmrname # name of vobj defining mwmr channel
	2459
[305]	2460	return
	2461
[319]	2462	################
	2463	def xml( self ): # xml for Cpport
[305]	2464
[319]	2465	print 'error in Cpport.xml() : not defined yet'
	2466	sys.exit(1)
[305]	2467
[319]	2468	return
	2469
	2470	#############################################
	2471	def cbin( self, mapping, verbose, expected ): # C binary structure for Cpport
	2472
	2473	if ( verbose ):
	2474	print '*** cbin for cpport[%d]' % (self.index)
	2475
	2476	# check index
	2477	if ( self.index != expected ):
	2478	print 'error in Cpport.cbin() : port global index = %d / expected = %d' \
	2479	% ( self.index, expected )
	2480	sys.exit(1)
	2481
	2482	# compute numerical value for direction
	2483	if ( self.direction == 'TO_COPROC' ):
	2484	dir_int = 0
	2485	else:
	2486	dir_int = 1
	2487
	2488	# compute vspace global index
	2489	vspace_id = 0xFFFFFFFF
	2490	for vspace in mapping.vspaces:
	2491	if ( self.vspacename == vspace.name ):
	2492	vspace_id = vspace.index
	2493	if (vspace_id == 0xFFFFFFFF):
	2494	print 'error in Cpport.cbin() : vspace name %s not found' \
	2495	% ( self.vspacename )
	2496	sys.exit(1)
	2497
	2498	# compute mwmr global index
	2499	mwmr_id = 0xFFFFFFFF
	2500	for vseg in mapping.vspace[vspace_id].vsegs:
	2501	for vobj in vseg.vobjs:
	2502	if (self.mwmrname == vobj.name):
	2503	mwmr_id = vobj.index
	2504	if (mwmr_id == 0xFFFFFFFF):
	2505	print 'error in Cpport.cbin() : mwmr vobj name %s not found in vspace %s' \
	2506	% ( self.mwmrname, self.vspacename )
	2507	sys.exit(1)
	2508
	2509	byte_stream = bytearray()
	2510	byte_stream += mapping.int2bytes( 4 , dir_int ) # pseg global index
	2511	byte_stream += mapping.int2bytes( 4 , vspace_id ) # vspace global index
	2512	byte_stream += mapping.int2bytes( 4 , mwmr_id ) # mwmr vobj global index
	2513
	2514	if ( verbose ):
	2515	print 'direction = %s' % self.direction
	2516	print 'vspace_id = %d' % vspace_id
	2517	print 'mwmr_id = %d' % mwmr_id
	2518
	2519	return byte_stream
	2520
	2521
[305]	2522	# Local Variables:
	2523	# tab-width: 4;
	2524	# c-basic-offset: 4;
	2525	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	2526	# indent-tabs-mode: nil;
	2527	# End:
	2528	#
	2529	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	2530

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