Changeset 328 for soft/giet_vm/giet_python/mapping.py
- Timestamp:
- Jun 16, 2014, 3:15:08 PM (10 years ago)
- File:
-
- 1 edited
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soft/giet_vm/giet_python/mapping.py
r327 r328 143 143 x_io = 0, # cluster_io x coordinate 144 144 y_io = 0, # cluster_io y coordinate 145 peri_increment = 0x10000, # address increment for globals 145 146 reset_address = 0xBFC00000 ): # Processor wired boot_address 146 147 … … 158 159 self.x_io = x_io 159 160 self.y_io = y_io 161 self.peri_increment = peri_increment 160 162 self.reset_address = reset_address 161 162 self.vseg_increment = 0x10000163 163 164 164 self.total_vspaces = 0 … … 344 344 pseg, # destination pseg name 345 345 identity = False, # identity mapping required if true 346 replicated = False, # replicated in all clusters if true347 346 binpath = '' ): # pathname for binary code 348 347 349 assert (identity and replicated) == False350 351 348 assert mode in VSEGMODES 352 349 … … 357 354 assert (x < self.x_size) and (y < self.y_size) 358 355 359 if ( replicated ): # replicated 360 for x_rep in xrange( self.x_size ): 361 for y_rep in xrange( self.y_size ): 362 vbase_rep = vbase + (((x_rep << self.y_width) + y_rep) << 16) 363 name_rep = name + '_%d_%d' % ( x_rep , y_rep ) 364 365 # add one vseg [x,y] into mapping 366 vseg = Vseg( name_rep, vbase_rep, mode, x_rep, y_rep, pseg, identity ) 367 self.globs.append( vseg ) 368 self.total_globals += 1 369 vseg.index = self.total_vsegs 370 self.total_vsegs += 1 356 # add one vseg into mapping 357 vseg = Vseg( name, vbase, mode, x, y, pseg, identity ) 358 self.globs.append( vseg ) 359 self.total_globals += 1 360 vseg.index = self.total_vsegs 361 self.total_vsegs += 1 371 362 372 # add one vobj [x,y] in the mapping 373 vobj = Vobj( name_rep, size, vtype, binpath, 0, 0 ) 374 vseg.vobjs.append( vobj ) 375 vobj.index = self.total_vobjs 376 self.total_vobjs += 1 377 378 else: # single vseg 379 # add one vseg into mapping 380 vseg = Vseg( name, vbase, mode, x, y, pseg, identity ) 381 self.globs.append( vseg ) 382 self.total_globals += 1 383 vseg.index = self.total_vsegs 384 self.total_vsegs += 1 385 386 # add one vobj into mapping 387 vobj = Vobj( name, size, vtype, binpath, 0, 0 ) 388 vseg.vobjs.append( vobj ) 389 vobj.index = self.total_vobjs 390 self.total_vobjs += 1 363 # add one vobj into mapping 364 vobj = Vobj( name, size, vtype, binpath, 0, 0 ) 365 vseg.vobjs.append( vobj ) 366 vobj.index = self.total_vobjs 367 self.total_vobjs += 1 391 368 392 369 return … … 825 802 nb_fbf = 0 826 803 fbf_channels = 0 804 fbf_arg = 0 827 805 seg_fbf_base = 0xFFFFFFFF 828 806 seg_fbf_size = 0 … … 885 863 nb_xcu = 0 886 864 xcu_channels = 0 865 xcu_arg = 0 887 866 seg_xcu_base = 0xFFFFFFFF 888 867 seg_xcu_size = 0 … … 911 890 seg_fbf_size = periph.pseg.size 912 891 fbf_channels = periph.channels 892 fbf_arg = periph.arg 913 893 nb_fbf +=1 914 894 … … 986 966 seg_xcu_size = periph.pseg.size 987 967 xcu_channels = periph.channels 968 xcu_arg = periph.arg 988 969 nb_xcu +=1 989 970 … … 1048 1029 boot_stack_found = True 1049 1030 1050 # check allBOOT vsegs are found and identity mapping1031 # check that BOOT vsegs are found and identity mapping 1051 1032 if ( (boot_mapping_found == False) or (boot_mapping_ident == False) ): 1052 1033 print 'error in hard_config() : seg_boot_mapping missing or not ident' … … 1126 1107 s += '#define USE_RAMDISK %d\n' % self.use_ramdisk 1127 1108 s += '\n' 1109 s += '#define FBUF_X_SIZE %d\n' % fbf_arg 1110 s += '#define FBUF_Y_SIZE %d\n' % fbf_arg 1111 s += '\n' 1112 s += '#define XCU_NB_INPUTS %d\n' % xcu_arg 1113 s += '\n' 1128 1114 1129 1115 s += '/* physical base addresses for peripherals */\n' … … 1177 1163 s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size 1178 1164 s += '\n' 1179 s += '#define VSEG_CLUSTER_INCREMENT 0x%x\n' % self.vseg_increment1165 s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment 1180 1166 s += '\n' 1181 1167
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