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source: soft/giet_vm/giet_python/mapping.py @ 375

Last change on this file since 375 was 361, checked in by alain, 10 years ago
Remove the seg_boot_buffer from the generated hard_config.h file.
Property svn:executable set to ``*
File size: 102.3 KB

Rev	Line
[305]	1	#!/usr/bin/env python
	2
[319]	3	import sys
	4
	5	##########################################################################################
[305]	6	# file : giet_mapping.py
	7	# date : april 2014
	8	# author : Alain Greiner
[319]	9	##########################################################################################
	10	# This file contains the classes required to define a mapping for the GIET_VM.
	11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
	12	# a set of 'Vseg' (kernel virtual segments mapping)
	13	# a set of 'Vspace' (several user applications).
	14	# - A 'Cluster' contains a set of 'Pseg' (all physical segments in cluster)
	15	# a set of 'Proc' (processors in cluster)
	16	# a set of 'Periph' (peripherals in cluster)
	17	# a set of 'Coproc' (coprocessors in cluster)
	18	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments mapping)
	19	# a set of 'Task' (user tasks mapping)
	20	# - A 'Vseg' contains a set of 'Vobj'
	21	# - A 'Periph' contains a set of 'Irq' (only for XCU, ICU and PIC types )
	22	# - A 'Coproc' contains a set of 'Cpports' (one port per MWMR channel)
	23	##########################################################################################
	24	# Implementation Note
	25	# As described above, the various objects are distributed in the PYTHON structure:
	26	# For example the psegs set is split in several subsets (one subset per cluster),
	27	# or the tasks set is split in several subsets (one subset per vspace), etc...
	28	# In the C binary data structure used by the giet_vm, all objects of same type
	29	# are stored in a linear array (one single array for all psegs for example).
	30	# For all objects, we compute and store in the PYTHON object itsel a "global index"
	31	# corresponding to the index in this global array, and this index can be used as
	32	# a pseudo-pointer to identify a specific object of a given type.
	33	##########################################################################################
[305]	34
[319]	35	######################################################################################
	36	# These global lists must be consistent with enums in mapping_info.h or irq_handler.h
	37	######################################################################################
	38	PERIPHTYPES = [
	39	'CMA',
	40	'DMA',
	41	'FBF',
	42	'ICU',
	43	'IOB',
	44	'IOC',
	45	'MMC',
	46	'MWR',
	47	'NIC',
	48	'ROM',
	49	'SIM',
	50	'TIM',
	51	'TTY',
	52	'XCU',
	53	'PIC',
	54	]
	55
	56	PERIPHSUBTYPES = [
	57	'BDV',
	58	'HBA',
	59	'SPI',
	60	'NONE',
	61	]
	62
	63	IRQTYPES = [
	64	'HWI',
	65	'WTI',
	66	'PTI',
	67	]
	68
	69	ISRTYPES = [
	70	'ISR_DEFAULT',
	71	'ISR_TICK',
	72	'ISR_TTY_RX',
	73	'ISR_TTY_TX',
	74	'ISR_BDV',
	75	'ISR_TIMER',
	76	'ISR_WAKUP',
	77	'ISR_NIC_RX',
	78	'ISR_NIC_TX',
	79	'ISR_CMA',
	80	'ISR_MMC',
	81	'ISR_DMA',
	82	'ISR_SPI',
	83	]
	84
	85	VOBJTYPES = [
	86	'ELF',
	87	'BLOB',
	88	'PTAB',
	89	'PERI',
	90	'MWMR',
	91	'LOCK',
	92	'BUFFER',
	93	'BARRIER',
	94	'CONST',
	95	'MEMSPACE',
	96	'SCHED',
	97	]
	98
	99	VSEGMODES = [
	100	'____',
	101	'___U',
	102	'__W_',
	103	'__WU',
	104	'_X__',
	105	'_X_U',
	106	'_XW_',
	107	'_XWU',
	108	'C___',
	109	'C__U',
	110	'C_W_',
	111	'C_WU',
	112	'CX__',
	113	'CX_U',
	114	'CXW_',
	115	'CXWU',
	116	]
	117
	118	PSEGTYPES = [
	119	'RAM',
	120	'ROM', # deprecated => use PERI
	121	'PERI',
	122	]
	123
	124	CP_PORT_DIRS = [
	125	'TO_COPROC',
	126	'FROM_COPROC',
	127	]
	128
	129	##########################################################################################
[305]	130	class Mapping( object ):
[319]	131	##########################################################################################
[305]	132	def __init__( self,
[319]	133	name, # mapping name
	134	x_size, # number of clusters in a row
	135	y_size, # number of clusters in a column
	136	procs_max, # max number of processors per cluster
	137	x_width = 4, # number of bits encoding x coordinate
	138	y_width = 4, # number of bits encoding y coordinate
	139	paddr_width = 40, # number of bits for physical address
	140	coherence = 1, # hardware cache coherence when non-zero
	141	irq_per_proc = 1, # number or IRQs from XCU to processor
	142	use_ramdisk = False, # use ramdisk when true
	143	x_io = 0, # cluster_io x coordinate
	144	y_io = 0, # cluster_io y coordinate
[328]	145	peri_increment = 0x10000, # address increment for globals
[356]	146	reset_address = 0xBFC00000, # Processor wired boot_address
	147	ram_base = 0, # RAM physical base address in cluster[0,0]
	148	ram_size = 0 ): # RAM size in each cluster (bytes)
[305]	149
[319]	150	self.signature = 0xDACE2014
	151	self.name = name
	152	self.paddr_width = paddr_width
	153	self.coherence = coherence
	154	self.x_size = x_size
	155	self.y_size = y_size
	156	self.x_width = x_width
	157	self.y_width = y_width
	158	self.irq_per_proc = irq_per_proc
	159	self.procs_max = procs_max
	160	self.use_ramdisk = use_ramdisk
	161	self.x_io = x_io
	162	self.y_io = y_io
[328]	163	self.peri_increment = peri_increment
[319]	164	self.reset_address = reset_address
[356]	165	self.ram_base = ram_base
	166	self.ram_size = ram_size
[305]	167
[356]	168
[319]	169	self.total_vspaces = 0
	170	self.total_globals = 0
	171	self.total_psegs = 0
	172	self.total_vsegs = 0
	173	self.total_vobjs = 0
	174	self.total_tasks = 0
	175	self.total_procs = 0
	176	self.total_irqs = 0
	177	self.total_coprocs = 0
	178	self.total_cpports = 0
	179	self.total_periphs = 0
[305]	180
[319]	181	self.clusters = []
	182	self.globs = []
	183	self.vspaces = []
[305]	184
[319]	185	for x in xrange( self.x_size ):
	186	for y in xrange( self.y_size ):
	187	cluster = Cluster( x , y )
	188	cluster.index = (x * self.y_size) + y
	189	self.clusters.append( cluster )
[305]	190
	191	return
	192
[319]	193	########################## add a ram pseg in a cluster
	194	def addRam( self,
	195	name, # pseg name
	196	base, # pseg base address
	197	size ): # pseg length (bytes)
	198
	199	# check coordinates (obtained from the base address)
[356]	200	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
	201	cluster_xy = base >> paddr_lsb_width
[305]	202	x = cluster_xy >> (self.y_width);
	203	y = cluster_xy & ((1 << self.y_width) - 1)
	204
[319]	205	assert (base & 0xFFF) == 0
	206
	207	assert (x < self.x_size) and (y < self.y_size)
	208
[356]	209	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
	210
	211	assert ( size == self.ram_size )
	212
[319]	213	cluster_id = (x * self.y_size) + y
	214
	215	# add one pseg in the mapping
	216	pseg = Pseg( name, base, size, x, y, 'RAM' )
	217	self.clusters[cluster_id].psegs.append( pseg )
	218	pseg.index = self.total_psegs
	219	self.total_psegs += 1
	220
	221	return pseg
	222
	223	############################## add a peripheral and the associated pseg in a cluster
	224	def addPeriph( self,
	225	name, # associated pseg name
	226	base, # associated pseg base address
	227	size, # associated pseg length (bytes)
	228	ptype, # peripheral type
	229	subtype = 'NONE', # peripheral subtype
	230	channels = 1, # number of channels
	231	arg = 0 ): # optional argument (semantic depends on ptype)
	232
	233	# check cluster coordinates (obtained from the base address)
	234	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
[305]	235	x = cluster_xy >> (self.y_width);
	236	y = cluster_xy & ((1 << self.y_width) - 1)
	237
[319]	238	assert (x < self.x_size) and (y < self.y_size)
	239
	240	assert (base & 0xFFF) == 0
	241
	242	assert ptype in PERIPHTYPES
	243
	244	assert subtype in PERIPHSUBTYPES
	245
	246	cluster_id = (x * self.y_size) + y
	247
	248	# add one pseg into mapping
	249	pseg = Pseg( name, base, size, x, y, 'PERI' )
	250	self.clusters[cluster_id].psegs.append( pseg )
	251	pseg.index = self.total_psegs
	252	self.total_psegs += 1
	253
	254	# add one periph into mapping
	255	periph = Periph( pseg, ptype, subtype, channels, arg )
	256	self.clusters[cluster_id].periphs.append( periph )
	257	periph.index = self.total_periphs
	258	self.total_periphs += 1
	259
	260	return periph
	261
	262	################################ add an IRQ in a peripheral
	263	def addIrq( self,
	264	periph, # peripheral containing IRQ (PIC or XCU)
	265	index, # peripheral input port index
	266	isrtype, # ISR type
	267	channel = 0 ): # channel for multi-channels ISR
	268
	269	assert isrtype in ISRTYPES
	270
	271	assert index < 32
	272
	273	# add one irq into mapping
	274	irq = Irq( 'HWI', index , isrtype, channel )
	275	periph.irqs.append( irq )
	276	irq.index = self.total_irqs
	277	self.total_irqs += 1
	278
	279	return irq
	280
	281	########################## add a processor in a cluster
	282	def addProc( self,
	283	x, # cluster x coordinate
	284	y, # cluster y coordinate
	285	p ): # processor local index
	286
	287	assert (x < self.x_size) and (y < self.y_size)
	288
	289	cluster_id = (x * self.y_size) + y
	290
	291	# add one proc into mapping
	292	proc = Processor( x, y, p )
	293	self.clusters[cluster_id].procs.append( proc )
	294	proc.index = self.total_procs
[305]	295	self.total_procs += 1
	296
[319]	297	return proc
	298
	299	############################## add a coprocessor in a cluster
	300	def addCoproc( self,
	301	name, # associated pseg name
	302	base, # associated pseg base address
	303	size ): # associated pseg length
	304
	305	# check cluster coordinates (obtained from the base address)
	306	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
	307	x = cluster_xy >> (self.y_width);
	308	y = cluster_xy & ((1 << self.y_width) - 1)
	309
	310	assert (x < self.x_size) and (y < self.y_size)
	311
	312	cluster_id = (x * self.y_size) + y
	313
	314	# add one pseg into mapping
	315	pseg = Pseg( name, base, size, x, y, 'PERI' )
	316	self.clusters[cluster_id].psegs.append( pseg )
	317	pseg.index = self.total_psegs
	318	self.total_psegs += 1
	319
	320	# add one coproc into mapping
	321	periph = Coproc( pseg )
	322	self.clusters[cluster_id].coprocs.append( coproc )
	323	periph.index = self.total_coprocs
	324	self.total_coprocs += 1
	325
	326	return coproc
	327
	328	################################## add a port in a coprocessor
	329	def addPort( self,
	330	coproc, # coprocessor containing the port
	331	direction, # direction (TO_COPROC / FROM_COPROC)
	332	vspacename, # name of vspace using the coproc
	333	mwmrname ): # name of the vobj defining the MWMR channel
	334
	335	assert direction in CP_PORT_DIRS
	336
	337	# add one cpport into mapping
	338	port = Cpport( direction, vspacename, mwmrname )
	339	coproc.ports.append( port )
	340	port.index = self.total_cpports
	341	self.total_cpports += 1
	342
	343	return port
	344
	345	############################ add one (or several) global vseg into mapping
	346	def addGlobal( self,
[348]	347	name, # vseg name
	348	vbase, # virtual base address
	349	size, # vobj length (bytes)
	350	mode, # CXWU flags
	351	vtype, # vobj type
	352	x, # destination x coordinate
	353	y, # destination y coordinate
	354	pseg, # destination pseg name
	355	identity = False, # identity mapping required if true
	356	binpath = '', # pathname for binary code
	357	local = False ): # non shared vseg when true
[319]	358
	359	assert mode in VSEGMODES
	360
	361	assert vtype in VOBJTYPES
	362
	363	assert (vbase & 0xFFF) == 0
	364
	365	assert (x < self.x_size) and (y < self.y_size)
	366
[328]	367	# add one vseg into mapping
[348]	368	vseg = Vseg( name, vbase, mode, x, y, pseg,
	369	identity = identity, local = local )
	370
[328]	371	self.globs.append( vseg )
	372	self.total_globals += 1
	373	vseg.index = self.total_vsegs
	374	self.total_vsegs += 1
[319]	375
[328]	376	# add one vobj into mapping
	377	vobj = Vobj( name, size, vtype, binpath, 0, 0 )
	378	vseg.vobjs.append( vobj )
	379	vobj.index = self.total_vobjs
	380	self.total_vobjs += 1
[319]	381
[305]	382	return
	383
[319]	384	################################ add a vspace into mapping
	385	def addVspace( self,
	386	name, # vspace name
	387	startname ): # name of vobj containing start_vector
	388
	389	# add one vspace into mapping
	390	vspace = Vspace( name, startname )
[305]	391	self.vspaces.append( vspace )
[319]	392	vspace.index = self.total_vspaces
	393	self.total_vspaces += 1
	394
	395	return vspace
[305]	396
[319]	397	################################# add a private vseg and a vobj in a vspace
	398	def addVseg( self,
	399	vspace, # vspace containing the vseg
	400	name, # vseg name
	401	vbase, # virtual base address
	402	size, # vobj length (bytes)
	403	mode, # CXWU flags
	404	vtype, # vobj type
	405	x, # destination x coordinate
	406	y, # destination y coordinate
	407	pseg, # destination pseg name
[348]	408	binpath = '', # pathname for binary code
	409	align = 0, # alignment required
	410	init = 0, # initial value
	411	local = False ): # non shared when true
[319]	412
	413	assert mode in VSEGMODES
	414
	415	assert vtype in VOBJTYPES
	416
	417	assert (x < self.x_size) and (y < self.y_size)
	418
	419	# add one vseg into mapping
[348]	420	vseg = Vseg( name, vbase, mode, x, y, pseg, local = local )
[319]	421	vspace.vsegs.append( vseg )
	422	vseg.index = self.total_vsegs
	423	self.total_vsegs += 1
	424
	425	# add one vobj into mapping
	426	vobj = Vobj( name, size, vtype, binpath, align, init )
	427	vseg.vobjs.append( vobj )
	428	vobj.index = self.total_vobjs
	429	self.total_vobjs += 1
	430
	431	return vseg
	432
	433	################################ add a vobj in a private vseg
	434	def addVobj( self,
	435	vseg, # vseg containing vobj
	436	name, # vobj name
	437	size, # vobj length (bytes)
	438	vtype, # vobj type
	439	binpath = '', # pathname to binary
	440	align = 0, # alignment constraint
	441	init = 0 ): # initial value
	442
	443	assert vtype in VOBJTYPES
	444
	445	# add one vobj into mapping
	446	vobj = Vobj( name, size, vtype, binpath, align, init )
	447	vseg.vobjs.append( vobj )
	448	vobj.index = self.total_vobjs
	449	self.total_vobjs += 1
	450
	451	return vobj
	452
	453	################################ add a task in a vspace
	454	def addTask( self,
	455	vspace, # vspace containing task
	456	name, # task name
	457	trdid, # task index in vspace
	458	x, # destination x coordinate
	459	y, # destination y coordinate
	460	lpid, # destination processor local index
	461	stackname, # name of vobj containing stack
	462	heapname, # name of vobj containing heap
	463	startid, # index in start_vector
	464	usetty = False, # request a private TTY channel
	465	usenic = False, # request a private NIC channel
	466	usecma = False, # request a private CMA channel
	467	usehba = False, # request a private HBA channel
	468	usetim = False ): # request a private TIM channel
	469
	470	assert (x < self.x_size) and (y < self.y_size)
	471
	472	assert lpid < self.procs_max
	473
	474	# add one task into mapping
	475	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid,
	476	usetty, usenic, usecma, usehba, usetim )
	477	vspace.tasks.append( task )
	478	task.index = self.total_tasks
	479	self.total_tasks += 1
	480
	481	return task
	482
	483	#################################
	484	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
	485
	486	byte_stream = bytearray()
	487	length = len( s )
	488	if length < (nbytes - 1):
	489	for b in s:
	490	byte_stream.append( b )
	491	for x in xrange(nbytes-length):
	492	byte_stream.append( '\0' )
	493	else:
[348]	494	print '[genmap error] in str2bytes() : string %s too long' % s
[319]	495	sys.exit(1)
	496
	497	return byte_stream
	498
	499	###################################
	500	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
	501
	502	byte_stream = bytearray()
	503	for n in xrange( nbytes ):
	504	byte_stream.append( (val >> (n<<3)) & 0xFF )
	505
	506	return byte_stream
	507
	508	################
	509	def xml( self ): # xml file generation for mapping
	510
[305]	511	s = '<?xml version="1.0"?>\n\n'
[319]	512	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
[305]	513	s += ' name = "%s"\n' % (self.name)
	514	s += ' x_size = "%d"\n' % (self.x_size)
	515	s += ' y_size = "%d"\n' % (self.y_size)
	516	s += ' x_width = "%d"\n' % (self.x_width)
	517	s += ' y_width = "%d"\n' % (self.y_width)
	518	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
[319]	519	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
[305]	520	s += ' x_io = "%d"\n' % (self.x_io)
	521	s += ' y_io = "%d" >\n' % (self.y_io)
[319]	522	s += '\n'
	523
[305]	524	s += ' <clusterset>\n'
	525	for x in xrange ( self.x_size ):
	526	for y in xrange ( self.y_size ):
[319]	527	cluster_id = (x * self.y_size) + y
	528	s += self.clusters[cluster_id].xml()
[305]	529	s += ' </clusterset>\n'
[319]	530	s += '\n'
	531
[305]	532	s += ' <globalset>\n'
[319]	533	for vseg in self.globs: s += vseg.xml()
[305]	534	s += ' </globalset>\n'
[319]	535	s += '\n'
	536
[305]	537	s += ' <vspaceset>\n'
[319]	538	for vspace in self.vspaces: s += vspace.xml()
[305]	539	s += ' </vspaceset>\n'
[319]	540
[305]	541	s += '</mapping_info>\n'
	542	return s
[319]	543
	544	#########################
	545	def cbin( self, verbose ): # C binary structure generation for mapping
	546
	547	byte_stream = bytearray()
	548
	549	# header
	550	byte_stream += self.int2bytes(4, self.signature)
	551	byte_stream += self.int2bytes(4, self.x_size)
	552	byte_stream += self.int2bytes(4, self.y_size)
	553	byte_stream += self.int2bytes(4, self.x_width)
	554	byte_stream += self.int2bytes(4, self.y_width)
	555	byte_stream += self.int2bytes(4, self.x_io)
	556	byte_stream += self.int2bytes(4, self.y_io)
	557	byte_stream += self.int2bytes(4, self.irq_per_proc)
	558	byte_stream += self.int2bytes(4, self.use_ramdisk)
	559	byte_stream += self.int2bytes(4, self.total_globals)
	560	byte_stream += self.int2bytes(4, self.total_vspaces)
	561	byte_stream += self.int2bytes(4, self.total_psegs)
	562	byte_stream += self.int2bytes(4, self.total_vsegs)
	563	byte_stream += self.int2bytes(4, self.total_vobjs)
	564	byte_stream += self.int2bytes(4, self.total_tasks)
	565	byte_stream += self.int2bytes(4, self.total_procs)
	566	byte_stream += self.int2bytes(4, self.total_irqs)
	567	byte_stream += self.int2bytes(4, self.total_coprocs)
	568	byte_stream += self.int2bytes(4, self.total_cpports)
	569	byte_stream += self.int2bytes(4, self.total_periphs)
	570	byte_stream += self.str2bytes(32, self.name)
	571
	572	if ( verbose ):
	573	print '\n'
	574	print 'name = %s' % self.name
	575	print 'signature = %x' % self.signature
	576	print 'x_size = %d' % self.x_size
	577	print 'y_size = %d' % self.y_size
	578	print 'x_width = %d' % self.x_width
	579	print 'y_width = %d' % self.y_width
	580	print 'x_io = %d' % self.x_io
	581	print 'y_io = %d' % self.y_io
	582	print 'irq_per_proc = %d' % self.irq_per_proc
	583	print 'use_ramdisk = %d' % self.use_ramdisk
	584	print 'total_globals = %d' % self.total_globals
	585	print 'total_psegs = %d' % self.total_psegs
	586	print 'total_vsegs = %d' % self.total_vsegs
	587	print 'total_vobjs = %d' % self.total_vobjs
	588	print 'total_tasks = %d' % self.total_tasks
	589	print 'total_procs = %d' % self.total_procs
	590	print 'total_irqs = %d' % self.total_irqs
	591	print 'total_coprocs = %d' % self.total_coprocs
	592	print 'total_cpports = %d' % self.total_cpports
	593	print 'total_periphs = %d' % self.total_periphs
	594	print '\n'
	595
	596	# clusters array
	597	index = 0
	598	for cluster in self.clusters:
	599	byte_stream += cluster.cbin( self, verbose, index )
	600	index += 1
	601
	602	if ( verbose ): print '\n'
	603
	604	# psegs array
	605	index = 0
	606	for cluster in self.clusters:
	607	for pseg in cluster.psegs:
	608	byte_stream += pseg.cbin( self, verbose, index, cluster )
	609	index += 1
	610
	611	if ( verbose ): print '\n'
	612
	613	# vspaces array
	614	index = 0
	615	for vspace in self.vspaces:
	616	byte_stream += vspace.cbin( self, verbose, index )
	617	index += 1
	618
	619	if ( verbose ): print '\n'
	620
	621	# vsegs array
	622	index = 0
	623	for vseg in self.globs:
	624	byte_stream += vseg.cbin( self, verbose, index )
	625	index += 1
	626	for vspace in self.vspaces:
	627	for vseg in vspace.vsegs:
	628	byte_stream += vseg.cbin( self, verbose, index )
	629	index += 1
	630
	631	if ( verbose ): print '\n'
	632
	633	# vobjs array
	634	index = 0
	635	for vseg in self.globs:
	636	for vobj in vseg.vobjs:
	637	byte_stream += vobj.cbin( self, verbose, index )
	638	index += 1
	639	for vspace in self.vspaces:
	640	for vseg in vspace.vsegs:
	641	for vobj in vseg.vobjs:
	642	byte_stream += vobj.cbin( self, verbose, index )
	643	index += 1
	644
	645	if ( verbose ): print '\n'
	646
	647	# tasks array
	648	index = 0
	649	for vspace in self.vspaces:
	650	for task in vspace.tasks:
	651	byte_stream += task.cbin( self, verbose, index, vspace )
	652	index += 1
	653
	654	if ( verbose ): print '\n'
	655
	656	# procs array
	657	index = 0
	658	for cluster in self.clusters:
	659	for proc in cluster.procs:
	660	byte_stream += proc.cbin( self, verbose, index )
	661	index += 1
	662
	663	if ( verbose ): print '\n'
	664
	665	# irqs array
	666	index = 0
	667	for cluster in self.clusters:
	668	for periph in cluster.periphs:
	669	for irq in periph.irqs:
	670	byte_stream += irq.cbin( self, verbose, index )
	671	index += 1
	672
	673	if ( verbose ): print '\n'
	674
	675	# coprocs array
	676	index = 0
	677	for cluster in self.clusters:
	678	for coproc in cluster.coprocs:
	679	byte_stream += coproc.cbin( self, verbose, index )
	680	index += 1
	681
	682	if ( verbose ): print '\n'
	683
	684	# cpports array
	685	index = 0
	686	for cluster in self.clusters:
	687	for coproc in cluster.coprocs:
	688	for port in coproc.ports:
	689	byte_stream += port.cbin( self, verbose, index )
	690	index += 1
	691
	692	if ( verbose ): print '\n'
	693
	694	# periphs array
	695	index = 0
	696	for cluster in self.clusters:
	697	for periph in cluster.periphs:
	698	byte_stream += periph.cbin( self, verbose, index )
	699	index += 1
	700
	701	return byte_stream
	702	# end of cbin()
	703
	704	#######################
	705	def giet_vsegs( self ): # compute string for giet_vsegs.ld file
	706	# required by giet_vm compilation
	707
	708	# search the vsegs required for the giet_vsegs.ld
	709	boot_code_found = False
	710	boot_data_found = False
	711	kernel_uncdata_found = False
	712	kernel_data_found = False
	713	kernel_code_found = False
	714	kernel_init_found = False
	715	for vseg in self.globs:
[348]	716
[319]	717	if ( vseg.name == 'seg_boot_code' ):
	718	boot_code_vbase = vseg.vbase
	719	boot_code_size = vseg.vobjs[0].length
	720	boot_code_found = True
	721
	722	if ( vseg.name == 'seg_boot_data' ):
	723	boot_data_vbase = vseg.vbase
	724	boot_data_size = vseg.vobjs[0].length
	725	boot_data_found = True
	726
	727	if ( vseg.name == 'seg_kernel_uncdata' ):
	728	kernel_uncdata_vbase = vseg.vbase
	729	kernel_uncdata_size = vseg.vobjs[0].length
	730	kernel_uncdata_found = True
	731
	732	if ( vseg.name == 'seg_kernel_data' ):
	733	kernel_data_vbase = vseg.vbase
	734	kernel_data_size = vseg.vobjs[0].length
	735	kernel_data_found = True
	736
	737	if ( vseg.name == 'seg_kernel_code' ):
	738	kernel_code_vbase = vseg.vbase
	739	kernel_code_size = vseg.vobjs[0].length
	740	kernel_code_found = True
	741
	742	if ( vseg.name == 'seg_kernel_init' ):
	743	kernel_init_vbase = vseg.vbase
	744	kernel_init_size = vseg.vobjs[0].length
	745	kernel_init_found = True
	746
	747	# check if all required vsegs have been found
	748	if ( boot_code_found == False ):
[348]	749	print '[genmap error] in giet_vsegs() : seg_boot_code vseg missing'
[319]	750	sys.exit()
	751
	752	if ( boot_data_found == False ):
[348]	753	print '[genmap error] in giet_vsegs() : seg_boot_data vseg missing'
[319]	754	sys.exit()
	755
	756	if ( kernel_data_found == False ):
[348]	757	print '[genmap error] in giet_vsegs() : seg_kernel_data vseg missing'
[319]	758	sys.exit()
	759
	760	if ( kernel_uncdata_found == False ):
[348]	761	print '[genmap error] in giet_vsegs() : seg_kernel_uncdata vseg missing'
[319]	762	sys.exit()
	763
	764	if ( kernel_code_found == False ):
[348]	765	print '[genmap error] in giet_vsegs() : seg_kernel_code vseg missing'
[319]	766	sys.exit()
	767
	768	if ( kernel_init_found == False ):
[348]	769	print '[genmap error] in giet_vsegs() : seg_kernel_init vseg missing'
[319]	770	sys.exit()
	771
	772	# build string
[327]	773	s = '/* Generated by genmap for %s */\n' % self.name
[319]	774	s += '\n'
	775
	776	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
	777	s += 'boot_code_size = 0x%x;\n' % boot_code_size
	778	s += '\n'
	779	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
	780	s += 'boot_data_size = 0x%x;\n' % boot_data_size
	781	s += '\n'
	782	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
	783	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
	784	s += '\n'
	785	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
	786	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
	787	s += '\n'
	788	s += 'kernel_uncdata_vbase = 0x%x;\n' % kernel_uncdata_vbase
	789	s += 'kernel_uncdata_size = 0x%x;\n' % kernel_uncdata_size
	790	s += '\n'
	791	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
	792	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
	793	s += '\n'
	794
	795	return s
	796
	797	########################
	798	def hard_config( self ): # compute string for hard_config.h file required by
	799	# - top.cpp compilation
	800	# - giet_vm compilation
	801	# - tsar_preloader compilation
	802
	803	nb_total_procs = 0
	804
	805	# for each peripheral type, define default values
	806	# for pbase address, size, number of components, and channels
	807	nb_cma = 0
	808	cma_channels = 0
	809	seg_cma_base = 0xFFFFFFFF
	810	seg_cma_size = 0
	811
	812	nb_dma = 0
	813	dma_channels = 0
	814	seg_dma_base = 0xFFFFFFFF
	815	seg_dma_size = 0
	816
	817	nb_fbf = 0
	818	fbf_channels = 0
[328]	819	fbf_arg = 0
[319]	820	seg_fbf_base = 0xFFFFFFFF
	821	seg_fbf_size = 0
	822
	823	nb_icu = 0
	824	icu_channels = 0
	825	seg_icu_base = 0xFFFFFFFF
	826	seg_icu_size = 0
	827
	828	nb_iob = 0
	829	iob_channels = 0
	830	seg_iob_base = 0xFFFFFFFF
	831	seg_iob_size = 0
	832
	833	nb_ioc = 0
	834	ioc_channels = 0
	835	seg_ioc_base = 0xFFFFFFFF
	836	seg_ioc_size = 0
	837
	838	nb_mmc = 0
	839	mmc_channels = 0
	840	seg_mmc_base = 0xFFFFFFFF
	841	seg_mmc_size = 0
	842
	843	nb_mwr = 0
	844	mwr_channels = 0
	845	seg_mwr_base = 0xFFFFFFFF
	846	seg_mwr_size = 0
	847
	848	nb_nic = 0
	849	nic_channels = 0
	850	seg_nic_base = 0xFFFFFFFF
	851	seg_nic_size = 0
	852
	853	nb_pic = 0
	854	pic_channels = 0
	855	seg_pic_base = 0xFFFFFFFF
	856	seg_pic_size = 0
	857
	858	nb_rom = 0
	859	rom_channels = 0
	860	seg_rom_base = 0xFFFFFFFF
	861	seg_rom_size = 0
	862
	863	nb_sim = 0
	864	sim_channels = 0
	865	seg_sim_base = 0xFFFFFFFF
	866	seg_sim_size = 0
	867
	868	nb_tim = 0
	869	tim_channels = 0
	870	seg_tim_base = 0xFFFFFFFF
	871	seg_tim_size = 0
	872
	873	nb_tty = 0
	874	tty_channels = 0
	875	seg_tty_base = 0xFFFFFFFF
	876	seg_tty_size = 0
	877
	878	nb_xcu = 0
	879	xcu_channels = 0
[328]	880	xcu_arg = 0
[319]	881	seg_xcu_base = 0xFFFFFFFF
	882	seg_xcu_size = 0
	883
	884	use_bdv = False
	885	use_spi = False
	886	use_hba = False
	887
	888	# get peripherals attributes
	889	for cluster in self.clusters:
	890	for periph in cluster.periphs:
	891	if ( periph.ptype == 'CMA' ):
	892	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
	893	seg_cma_size = periph.pseg.size
	894	cma_channels = periph.channels
	895	nb_cma +=1
	896
	897	elif ( periph.ptype == 'DMA' ):
	898	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
	899	seg_dma_size = periph.pseg.size
	900	dma_channels = periph.channels
	901	nb_dma +=1
	902
	903	elif ( periph.ptype == 'FBF' ):
	904	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
	905	seg_fbf_size = periph.pseg.size
	906	fbf_channels = periph.channels
[328]	907	fbf_arg = periph.arg
[319]	908	nb_fbf +=1
	909
	910	elif ( periph.ptype == 'ICU' ):
	911	seg_icu_base = periph.pseg.base & 0xFFFFFFFF
	912	seg_icu_size = periph.pseg.size
	913	icu_channels = periph.channels
	914	nb_icu +=1
	915
	916	elif ( periph.ptype == 'IOB' ):
	917	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
	918	seg_iob_size = periph.pseg.size
	919	iob_channels = periph.channels
	920	nb_iob +=1
	921
	922	elif ( periph.ptype == 'IOC' ):
	923	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
	924	seg_ioc_size = periph.pseg.size
	925	ioc_channels = periph.channels
	926	nb_ioc += 1
	927	if ( periph.subtype == 'BDV' ): use_bdv = True
	928	elif ( periph.subtype == 'HBA' ): use_hba = True
	929	elif ( periph.subtype == 'SPI' ): use_spi = True
	930
	931	elif ( periph.ptype == 'MMC' ):
	932	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
	933	seg_mmc_size = periph.pseg.size
	934	mmc_channels = periph.channels
	935	nb_mmc +=1
	936
	937	elif ( periph.ptype == 'MWR' ):
	938	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
	939	seg_wmr_size = periph.pseg.size
	940	mwr_channels = periph.channels
	941	nb_mwr +=1
	942
	943	elif ( periph.ptype == 'ROM' ):
	944	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
	945	seg_rom_size = periph.pseg.size
	946	rom_channels = periph.channels
	947	nb_rom +=1
	948
	949	elif ( periph.ptype == 'SIM' ):
	950	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
	951	seg_sim_size = periph.pseg.size
	952	sim_channels = periph.channels
	953	nb_sim +=1
	954
	955	elif ( periph.ptype == 'NIC' ):
	956	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
	957	seg_nic_size = periph.pseg.size
	958	nic_channels = periph.channels
	959	nb_nic +=1
	960
	961	elif ( periph.ptype == 'PIC' ):
	962	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
	963	seg_pic_size = periph.pseg.size
	964	pic_channels = periph.channels
	965	nb_pic +=1
	966
	967	elif ( periph.ptype == 'TIM' ):
	968	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
	969	seg_tim_size = periph.pseg.size
	970	tim_channels = periph.channels
	971	nb_tim +=1
	972
	973	elif ( periph.ptype == 'TTY' ):
	974	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
	975	seg_tty_size = periph.pseg.size
	976	tty_channels = periph.channels
	977	nb_tty +=1
	978
	979	elif ( periph.ptype == 'XCU' ):
	980	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
	981	seg_xcu_size = periph.pseg.size
	982	xcu_channels = periph.channels
[328]	983	xcu_arg = periph.arg
[319]	984	nb_xcu +=1
	985
	986	# don't mix ICU and XCU
	987	assert ( nb_icu*nb_xcu == 0 )
	988
	989	# no more than two access to external peripherals
	990	assert ( nb_fbf <= 2 )
	991	assert ( nb_cma <= 2 )
	992	assert ( nb_ioc <= 2 )
	993	assert ( nb_nic <= 2 )
	994	assert ( nb_tim <= 2 )
	995	assert ( nb_tty <= 2 )
	996	assert ( nb_pic <= 2 )
	997
	998	# one and only one type of IOC controller
	999	assert ( use_hba or use_bdv or use_spi )
	1000	assert ( (use_hba and use_bdv) == False )
	1001	assert ( (use_hba and use_spi) == False )
	1002	assert ( (use_bdv and use_spi) == False )
	1003
	1004	# Compute total number of processors
	1005	for cluster in self.clusters:
	1006	nb_total_procs += len( cluster.procs )
	1007
	1008	# Compute physical addresses for BOOT vsegs
	1009	boot_mapping_found = False
	1010	boot_code_found = False
	1011	boot_data_found = False
	1012	boot_stack_found = False
	1013
	1014	for vseg in self.globs:
	1015	if ( vseg.name == 'seg_boot_mapping' ):
	1016	boot_mapping_base = vseg.vbase
	1017	boot_mapping_size = vseg.vobjs[0].length
[348]	1018	boot_mapping_identity = vseg.identity
[319]	1019	boot_mapping_found = True
	1020
	1021	if ( vseg.name == 'seg_boot_code' ):
	1022	boot_code_base = vseg.vbase
	1023	boot_code_size = vseg.vobjs[0].length
[348]	1024	boot_code_identity = vseg.identity
[319]	1025	boot_code_found = True
	1026
	1027	if ( vseg.name == 'seg_boot_data' ):
	1028	boot_data_base = vseg.vbase
	1029	boot_data_size = vseg.vobjs[0].length
[348]	1030	boot_data_identity = vseg.identity
[319]	1031	boot_data_found = True
	1032
	1033	if ( vseg.name == 'seg_boot_stack' ):
	1034	boot_stack_base = vseg.vbase
	1035	boot_stack_size = vseg.vobjs[0].length
[348]	1036	boot_stack_identity = vseg.identity
[319]	1037	boot_stack_found = True
	1038
[328]	1039	# check that BOOT vsegs are found and identity mapping
[348]	1040	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
	1041	print '[genmap error] in hard_config() : seg_boot_mapping missing or not ident'
[319]	1042	sys.exit()
	1043
[348]	1044	if ( (boot_code_found == False) or (boot_code_identity == False) ):
	1045	print '[genmap error] in hard_config() : seg_boot_code missing or not ident'
[319]	1046	sys.exit()
	1047
[348]	1048	if ( (boot_data_found == False) or (boot_data_identity == False) ):
	1049	print '[genmap error] in hard_config() : seg_boot_data missing or not ident'
[319]	1050	sys.exit()
	1051
[348]	1052	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
	1053	print '[genmap error] in giet_vsegs() : seg_boot_stack missing or not ident'
[319]	1054	sys.exit()
	1055
	1056	# Search RAMDISK global vseg if required
	1057	seg_rdk_base = 0xFFFFFFFF
	1058	seg_rdk_size = 0
	1059	seg_rdk_found = False
	1060
	1061	if self.use_ramdisk:
	1062	for vseg in self.globs:
	1063	if ( vseg.name == 'seg_ramdisk' ):
	1064	seg_rdk_base = vseg.vbase
	1065	seg_rdk_size = vseg.vobjs[0].length
	1066	seg_rdk_found = True
	1067
	1068	if ( seg_rdk_found == False ):
	1069	print 'Error in hard_config() "seg_ramdisk" not found'
	1070	sys.exit(1)
	1071
	1072	# build string
[327]	1073	s = '/* Generated by genmap for %s */\n' % self.name
[319]	1074	s += '\n'
	1075	s += '#ifndef HARD_CONFIG_H\n'
	1076	s += '#define HARD_CONFIG_H\n'
	1077	s += '\n'
	1078
	1079	s += '/* General platform parameters */\n'
	1080	s += '\n'
	1081	s += '#define X_SIZE %d\n' % self.x_size
	1082	s += '#define Y_SIZE %d\n' % self.y_size
	1083	s += '#define X_WIDTH %d\n' % self.x_width
	1084	s += '#define Y_WIDTH %d\n' % self.y_width
	1085	s += '#define X_IO %d\n' % self.x_io
	1086	s += '#define Y_IO %d\n' % self.y_io
	1087	s += '#define NB_PROCS_MAX %d\n' % self.procs_max
	1088	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
	1089	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
	1090	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
	1091	s += '\n'
	1092
	1093	s += '/* Peripherals */\n'
	1094	s += '\n'
	1095	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
	1096	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
	1097	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
	1098	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
	1099	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
	1100	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
	1101	s += '\n'
	1102	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
	1103	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
	1104	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
	1105	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
	1106	s += '\n'
	1107	s += '#define USE_IOC_BDV %d\n' % use_bdv
	1108	s += '#define USE_IOC_SPI %d\n' % use_spi
	1109	s += '#define USE_IOC_HBA %d\n' % use_hba
	1110	s += '\n'
	1111	s += '#define USE_RAMDISK %d\n' % self.use_ramdisk
	1112	s += '\n'
[328]	1113	s += '#define FBUF_X_SIZE %d\n' % fbf_arg
	1114	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg
	1115	s += '\n'
	1116	s += '#define XCU_NB_INPUTS %d\n' % xcu_arg
	1117	s += '\n'
[319]	1118
[356]	1119	s += '/* base addresses and sizes for physical segments */\n'
[319]	1120	s += '\n'
[356]	1121	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
	1122	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
	1123	s += '\n'
[319]	1124	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
	1125	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
	1126	s += '\n'
	1127	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
[341]	1128	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
[319]	1129	s += '\n'
	1130	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
[341]	1131	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
[319]	1132	s += '\n'
	1133	s += '#define SEG_ICU_BASE 0x%x\n' % seg_icu_base
[341]	1134	s += '#define SEG_ICU_SIZE 0x%x\n' % seg_icu_size
[319]	1135	s += '\n'
	1136	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
[341]	1137	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
[319]	1138	s += '\n'
	1139	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
	1140	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
	1141	s += '\n'
	1142	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
	1143	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
	1144	s += '\n'
	1145	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
	1146	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
	1147	s += '\n'
	1148	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
	1149	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
	1150	s += '\n'
	1151	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
	1152	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
	1153	s += '\n'
	1154	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
	1155	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
	1156	s += '\n'
	1157	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
	1158	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
	1159	s += '\n'
	1160	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
	1161	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
	1162	s += '\n'
	1163	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
	1164	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
	1165	s += '\n'
	1166	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
	1167	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
	1168	s += '\n'
	1169	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
	1170	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
	1171	s += '\n'
[328]	1172	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
[319]	1173	s += '\n'
	1174
[326]	1175	s += '/* physical base addresses for identity mapped vsegs */\n'
	1176	s += '/* used by the GietVM OS */\n'
[319]	1177	s += '\n'
	1178	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
	1179	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
	1180	s += '\n'
	1181	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
	1182	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
	1183	s += '\n'
	1184	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
	1185	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
	1186	s += '\n'
	1187	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
	1188	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
	1189	s += '#endif\n'
	1190
	1191	return s
	1192
	1193	# end of hard_config()
	1194
	1195	#######################
	1196	def netbsd_dts( self ): # compute string for netbsd.dts file generation,
	1197	# used for netbsd configuration
	1198	# header
	1199	s = '/dts-v1/;\n'
	1200	s += '\n'
	1201	s += '/{\n'
	1202	s += ' #address-cells = <2>;\n'
	1203	s += ' #size-cells = <1>;\n'
	1204
	1205	# cpus (for each cluster)
	1206	s += ' cpus {\n'
	1207	s += ' #address-cells = <1>;\n'
	1208	s += ' #size-cells = <0>;\n'
	1209
	1210	for cluster in self.clusters:
	1211	for proc in cluster.procs:
	1212	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + proc.lpid
	1213
	1214	s += ' Mips,32@0x%x {\n' % proc_id
	1215	s += ' device_type = "cpu";\n'
	1216	s += ' icudev_type = "cpu:mips";\n'
	1217	s += ' name = "Mips,32";\n'
	1218	s += ' reg = <0x%x>;\n' % proc_id
	1219	s += ' };\n'
	1220	s += '\n'
	1221
	1222	s += ' };\n'
	1223
	1224	# rams (for each cluster)
	1225	for cluster in self.clusters:
	1226	for pseg in cluster.psegs:
	1227
	1228	if ( pseg.segtype == 'RAM' ):
	1229	msb = pseg.base >> 32
	1230	lsb = pseg.base & 0xFFFFFFFF
	1231	size = pseg.size
	1232
	1233	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
	1234	s += ' cached = <1>;\n'
	1235	s += ' device_type = "memory";\n'
	1236	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1237	s += ' };\n'
	1238
	1239	# peripherals (for each cluster)
	1240	for cluster in self.clusters:
	1241
	1242	# research XCU component
	1243	found_xcu = False
	1244	for periph in cluster.periphs:
	1245	if ( (periph.ptype == 'XCU') ):
	1246	found_xcu = True
	1247	xcu = periph
	1248	msb = periph.pseg.base >> 32
	1249	lsb = periph.pseg.base & 0xFFFFFFFF
	1250	size = periph.pseg.size
	1251
	1252	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1253	s += ' device_type = "soclib:xicu:root";\n'
	1254	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1255	s += ' input_lines = <%d>;\n' % periph.arg1
	1256	s += ' ipis = <%d>;\n' % periph.arg2
	1257	s += ' timers = <%d>;\n' % periph.arg3
	1258
	1259	output_id = 0 # output index from XCU
	1260	for lpid in xrange ( len(cluster.procs) ): # destination processor index
	1261	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
	1262	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + lpid
	1263	s += ' out@%d {\n' % output_id
	1264	s += ' device_type = "soclib:xicu:filter";\n'
	1265	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
	1266	s += ' output_line = <%d>;\n' % output_id
	1267	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1268	s += ' };\n'
	1269
	1270	output_id += 1
	1271
	1272	s += ' };\n'
	1273
	1274	# research PIC component
	1275	found_pic = False
	1276	for periph in cluster.periphs:
	1277	if ( periph.ptype == 'PIC' ):
	1278	found_pic = True
	1279	pic = periph
	1280	msb = periph.pseg.base >> 32
	1281	lsb = periph.pseg.base & 0xFFFFFFFF
	1282	size = periph.pseg.size
	1283
	1284	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1285	s += ' device_type = "soclib:pic:root";\n'
	1286	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1287	s += ' input_lines = <%d>;\n' % periph.channels
	1288	s += ' };\n'
	1289
	1290	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
[348]	1291	print '[genmap error] in netbsd_dts() : No XCU/PIC in cluster(%d,%d)' % (cluster.x, cluster.y)
[319]	1292	sys.exit(1)
	1293
	1294	if ( found_pic == True ): irq_tgt = pic
	1295	else: irq_tgt = xcu
	1296
	1297	# get all others peripherals in cluster
	1298	for periph in cluster.periphs:
	1299	msb = periph.pseg.base >> 32
	1300	lsb = periph.pseg.base & 0xFFFFFFFF
	1301	size = periph.pseg.size
	1302
	1303	# research DMA component
	1304	if ( periph.ptype == 'DMA' ):
	1305
	1306	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1307	s += ' device_type = "soclib:dma";\n'
	1308	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1309	s += ' channel_count = <%d>;\n' % periph.channels
	1310
	1311	# multi-channels : get HWI index (to XCU) for each channel
	1312	for channel in xrange( periph.channels ):
	1313	hwi_id = 0xFFFFFFFF
	1314	for irq in xcu.irqs:
	1315	if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ):
	1316	hwi_id = irq.srcid
	1317	if ( hwi_id == 0xFFFFFFFF ):
[348]	1318	print '[genmap error] in netbsd.dts() ISR_DMA channel %d not found' % channel
[319]	1319	sys.exit(1)
	1320
	1321	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
	1322	s += ' irq@%d{\n' % channel
	1323	s += ' device_type = "soclib:periph:irq";\n'
	1324	s += ' output_line = <%d>;\n' % channel
	1325	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1326	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1327	s += ' };\n'
	1328
	1329	s += ' };\n'
	1330
	1331	# research MMC component
	1332	elif ( periph.ptype == 'MMC' ):
	1333
	1334	# get irq line index associated to MMC in XCU
	1335	irq_in = 0xFFFFFFFF
	1336	for irq in xcu.irqs:
	1337	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
	1338	if ( irq_in == 0xFFFFFFFF ):
[348]	1339	print '[genmap error] in netbsd.dts() ISR_MMC not found'
[319]	1340	sys.exit(1)
	1341
	1342	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1343	s += ' device_type = "soclib:mmc";\n'
	1344	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1345	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1346	s += ' };\n'
	1347
	1348	# research FBF component
	1349	elif ( periph.ptype == 'FBF' ):
	1350
	1351	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1352	s += ' device_type = "soclib:framebuffer";\n'
	1353	s += ' mode = <32>;\n' # bits par pixel
	1354	s += ' width = <%d>;\n' % periph.arg1
	1355	s += ' height = <%d>;\n' % periph.arg2
	1356	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1357	s += ' };\n'
	1358
	1359	# research IOC component
	1360	elif ( periph.ptype == 'IOC' ):
	1361
	1362	if ( periph.subtype == 'BDV' ):
	1363
	1364	# get irq line index associated to bdv
	1365	irq_in = 0xFFFFFFFF
	1366	for irq in irq_tgt.irqs:
	1367	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
	1368	if ( irq_in == 0xFFFFFFFF ):
[348]	1369	print '[genmap error] in netbsd.dts() ISR_BDV not found'
[319]	1370	sys.exit(1)
	1371
	1372	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1373	s += ' device_type = "soclib:blockdevice";\n'
	1374	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1375	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1376	s += ' };\n'
	1377
	1378	elif ( periph.subtype == 'HBA' ):
[348]	1379	print '[genmap error] in netbsd_dts() : HBA peripheral not supported by NetBSD'
[319]	1380	sys.exit(1)
	1381
	1382	elif ( periph.subtype == 'SPI' ):
	1383
	1384	# get irq line index associated to spi
	1385	irq_in = 0xFFFFFFFF
	1386	for irq in irq_tgt.irqs:
	1387	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
	1388	if ( irq_in == 0xFFFFFFFF ):
[348]	1389	print '[genmap error] in netbsd.dts() ISR_SPI not found'
[319]	1390	sys.exit(1)
	1391
	1392	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1393	s += ' device_type = "soclib:spi";\n'
	1394	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1395	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1396	s += ' };\n'
	1397
	1398	# research ROM component
	1399	elif ( periph.ptype == 'ROM' ):
	1400
	1401	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1402	s += ' device_type = "rom";\n'
	1403	s += ' cached = <1>;\n'
	1404	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1405	s += ' };\n'
	1406
	1407	# research SIM component
	1408	elif ( periph.ptype == 'SIM' ):
	1409
	1410	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1411	s += ' device_type = "soclib:simhelper";\n'
	1412	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1413	s += ' };\n'
	1414
	1415	# research TTY component
	1416	elif ( periph.ptype == 'TTY' ):
	1417
	1418	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1419	s += ' device_type = "soclib:tty";\n'
	1420	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1421	s += ' channel_count = < %d >;\n' % periph.channels
	1422
	1423	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1424	for channel in xrange( periph.channels ):
	1425	hwi_id = 0xFFFFFFFF
	1426	for irq in irq_tgt.irqs:
	1427	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
	1428	hwi_id = irq.srcid
	1429	if ( hwi_id == 0xFFFFFFFF ):
[348]	1430	print '[genmap error] in netbsd.dts() ISR_TTY_RX channel %d not found' % channel
[319]	1431	sys.exit(1)
	1432
	1433	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1434	s += ' irq@%d{\n' % channel
	1435	s += ' device_type = "soclib:periph:irq";\n'
	1436	s += ' output_line = <%d>;\n' % channel
	1437	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1438	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1439	s += ' };\n'
	1440
	1441	s += ' };\n'
	1442
	1443	# research IOB component
	1444	elif ( periph.ptype == 'IOB' ):
	1445
	1446	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1447	s += ' device_type = "soclib:iob";\n'
	1448	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1449	s += ' };\n'
	1450
	1451	# research NIC component
	1452	elif ( periph.ptype == 'NIC' ):
	1453
	1454	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1455	s += ' device_type = "soclib:nic";\n'
	1456	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1457	s += ' channel_count = < %d >;\n' % periph.channels
	1458
	1459	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
	1460	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
	1461	for channel in xrange( periph.channels ):
	1462	hwi_id = 0xFFFFFFFF
	1463	for irq in irq_tgt.irqs:
	1464	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
	1465	hwi_id = irq.srcid
	1466	if ( hwi_id == 0xFFFFFFFF ):
[348]	1467	print '[genmap error] in netbsd.dts() ISR_NIC_RX channel %d not found' % channel
[319]	1468	sys.exit(1)
	1469
	1470	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1471	s += ' irq_rx@%d{\n' % channel
	1472	s += ' device_type = "soclib:periph:irq";\n'
	1473	s += ' output_line = <%d>;\n' % (2*channel)
	1474	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1475	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1476	s += ' };\n'
	1477
	1478	hwi_id = 0xFFFFFFFF
	1479	for irq in irq_tgt.irqs:
	1480	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
	1481	hwi_id = irq.srcid
	1482	if ( hwi_id == 0xFFFFFFFF ):
[348]	1483	print '[genmap error] in netbsd.dts() ISR_NIC_TX channel %d not found' % channel
[319]	1484	sys.exit(1)
	1485
	1486	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1487	s += ' irq_tx@%d{\n' % channel
	1488	s += ' device_type = "soclib:periph:irq";\n'
	1489	s += ' output_line = <%d>;\n' % (2*channel + 1)
	1490	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1491	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1492	s += ' };\n'
	1493
	1494	s += ' };\n'
	1495
	1496	# research CMA component
	1497	elif ( periph.ptype == 'CMA' ):
	1498
	1499	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1500	s += ' device_type = "soclib:cma";\n'
	1501	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1502	s += ' channel_count = < %d >;\n' % periph.channels
	1503
	1504	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1505	for channel in xrange( periph.channels ):
	1506	hwi_id = 0xFFFFFFFF
	1507	for irq in irq_tgt.irqs:
	1508	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
	1509	hwi_id = irq.srcid
	1510	if ( hwi_id == 0xFFFFFFFF ):
[348]	1511	print '[genmap error] in netbsd.dts() ISR_CMA channel %d not found' % channel
[319]	1512	sys.exit(1)
	1513
	1514	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1515	s += ' irq@%d{\n' % channel
	1516	s += ' device_type = "soclib:periph:irq";\n'
	1517	s += ' output_line = <%d>;\n' % channel
	1518	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1519	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1520	s += ' };\n'
	1521
	1522	s += ' };\n'
	1523
	1524	# research TIM component
	1525	elif ( periph.ptype == 'TIM' ):
	1526
[348]	1527	print '[genmap error] in netbsd_dts() : TIM peripheral not supported by NetBSD'
[319]	1528	sys.exit(1)
	1529
	1530	# research MWR component
	1531	elif ( periph.ptype == 'MWR' ):
	1532
[348]	1533	print '[genmap error] in netbsd_dts() : MWR peripheral not supported by NetBSD'
[319]	1534	sys.exit(1)
	1535
	1536	# research ICU component
	1537	elif ( periph.ptype == 'ICU' ):
[348]	1538	print '[genmap error] in netbsd_dts() : ICU peripheral not supported by NetBSD'
[319]	1539	sys.exit(1)
	1540
	1541	# topology
	1542	s += '\n'
	1543	s += ' topology {\n'
	1544	s += ' #address-cells = <2>;\n'
	1545	s += ' #size-cells = <0>;\n'
	1546	for cluster in self.clusters:
	1547	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
	1548	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
	1549	s += ' devices = <\n'
	1550
	1551	offset = ((cluster.x << self.y_width) + cluster.y) * self.procs_max
	1552	for proc in cluster.procs:
	1553	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
	1554	for periph in cluster.periphs:
	1555	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
	1556
	1557	s += ' >;\n'
	1558	s += ' };\n'
	1559	s += ' };\n'
	1560	s += '};\n'
	1561
	1562	return s
	1563	# end netbsd_dts( )
	1564
	1565	###########################
	1566	def almos_archinfo( self ): # compute string for arch.info file generation,
	1567	# used for almos configuration
	1568	# header
[327]	1569	s = '# arch.info file generated by genmap for %s\n' % self.name
[319]	1570	s += '\n'
	1571	s += '[HEADER]\n'
	1572	s += ' REVISION=1\n'
	1573	s += ' ARCH=%s\n' % self.name
	1574	s += ' XMAX=%d\n' % self.x_size
	1575	s += ' YMAX=%d\n' % self.y_size
	1576	s += ' CPU_NR=%d\n' % self.procs_max
	1577	s += '\n'
	1578
	1579	# clusters
	1580	cluster_id = 0
	1581	for cluster in self.clusters:
	1582
	1583	ram = None
	1584	nb_cpus = len( cluster.procs )
	1585	nb_devs = len( cluster.periphs )
	1586	if ( len( cluster.coprocs ) != 0 ):
	1587	print 'Error in almos_archinfo() coprocessors not supported yet'
	1588	sys.exit(1)
	1589
	1590	# search a RAM
	1591	for pseg in cluster.psegs:
	1592	if ( pseg.segtype == 'RAM' ):
	1593	ram = pseg
	1594	nb_devs += 1
	1595
	1596	# search XCU to get IRQs indexes if cluster contains peripherals
	1597	if ( len( cluster.periphs ) != 0 ):
	1598	tty_irq_id = None
	1599	bdv_irq_id = None
	1600	dma_irq_id = None
	1601
	1602	for periph in cluster.periphs:
	1603	if ( periph.ptype == 'XCU' ):
	1604	# scan irqs
	1605	for irq in periph.irqs:
	1606	if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid
	1607	if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid
	1608	if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid
	1609
	1610	# Build the cluster description
	1611	s += '[CLUSTER]\n'
	1612	s += ' CID=%d\n' % cluster_id
	1613	s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y)
	1614	s += ' CPU_NR=%d\n' % nb_cpus
	1615	s += ' DEV_NR=%d\n' % nb_devs
	1616
	1617
	1618	# Handling RAM when cluster contain a RAM
	1619	if (ram != None ):
	1620	base = ram.base
	1621	size = ram.size
	1622	irqid = -1
	1623	s += ' DEVID=RAM'
	1624	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1625
	1626	# Handling peripherals
	1627	for periph in cluster.periphs:
	1628	base = periph.pseg.base
	1629	size = periph.pseg.size
	1630
	1631	if ( periph.ptype == 'XCU' ):
	1632
	1633	s += ' DEVID=XICU'
	1634	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1635
	1636	elif ( (periph.ptype == 'TTY')
	1637	and (tty_irq_id != None) ):
	1638
	1639	s += ' DEVID=TTY'
	1640	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id )
	1641
	1642	elif ( (periph.ptype == 'DMA')
	1643	and (dma_irq_id != None) ):
	1644
	1645	s += ' DEVID=DMA'
	1646	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id )
	1647
	1648	elif ( periph.ptype == 'FBF' ):
	1649
	1650	s += ' DEVID=FB'
	1651	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1652
	1653	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
	1654	and (bdv_irq_id != None) ):
	1655
	1656	s += ' DEVID=BLKDEV'
	1657	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id )
	1658
	1659	elif ( periph.ptype == 'PIC' ):
	1660
	1661	s += ' DEVID=IOPIC'
	1662	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1663
	1664	else:
	1665	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
	1666	% (cluster.x, cluster.y)
	1667	print '# peripheral type %s/%s not supported yet\n' \
	1668	% ( periph.ptype, periph.subtype )
	1669
	1670	cluster_id += 1
	1671
	1672	return s
	1673
	1674	# end of almos_archinfo()
	1675
	1676
	1677
	1678
	1679
	1680
	1681
	1682
	1683	###########################################################################################
	1684	class Cluster ( object ):
	1685	###########################################################################################
	1686	def __init__( self,
	1687	x,
	1688	y ):
	1689
	1690	self.index = 0 # global index (set by Mapping constructor)
	1691	self.x = x # x coordinate
	1692	self.y = y # y coordinate
	1693	self.psegs = [] # filled by addRam() or addPeriph()
	1694	self.procs = [] # filled by addProc()
	1695	self.coprocs = [] # filled by addCoproc()
	1696	self.periphs = [] # filled by addPeriph()
	1697
	1698	return
	1699
	1700	################
	1701	def xml( self ): # xml for a cluster
	1702
	1703	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
	1704	for pseg in self.psegs: s += pseg.xml()
	1705	for proc in self.procs: s += proc.xml()
	1706	for copr in self.coprocs: s += copr.xml()
	1707	for peri in self.periphs: s += peri.xml()
	1708	s += ' </cluster>\n'
	1709
	1710	return s
	1711
	1712	#############################################
	1713	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
	1714
	1715	if ( verbose ):
	1716	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
	1717
	1718	# check index
	1719	if (self.index != expected):
[348]	1720	print '[genmap error] in Cluster.cbin() : cluster global index = %d / expected = %d' \
[319]	1721	% (self.index, expected )
	1722	sys.exit(1)
	1723
	1724	# compute global index for first pseg
	1725	if ( len(self.psegs) > 0 ):
	1726	pseg_id = self.psegs[0].index
	1727	else:
	1728	pseg_id = 0
	1729
	1730	# compute global index for first proc
	1731	if ( len(self.procs) > 0 ):
	1732	proc_id = self.procs[0].index
	1733	else:
	1734	proc_id = 0
	1735
	1736	# compute global index for first coproc
	1737	if ( len(self.coprocs) > 0 ):
	1738	coproc_id = self.coprocs[0].index
	1739	else:
	1740	coproc_id = 0
	1741
	1742	# compute global index for first periph
	1743	if ( len(self.periphs) > 0 ):
	1744	periph_id = self.periphs[0].index
	1745	else:
	1746	periph_id = 0
	1747
	1748	byte_stream = bytearray()
	1749	byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate
	1750	byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate
	1751	byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number of psegs in cluster
	1752	byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index
	1753	byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number of procs in cluster
	1754	byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index
	1755	byte_stream += mapping.int2bytes( 4 , len( self.coprocs ) ) # number of coprocs in cluster
	1756	byte_stream += mapping.int2bytes( 4 , coproc_id ) # first coproc global index
	1757	byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number of periphs in cluster
	1758	byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index
	1759
	1760	if ( verbose ):
	1761	print 'nb_psegs = %d' % len( self.psegs )
	1762	print 'pseg_id = %d' % pseg_id
	1763	print 'nb_procs = %d' % len( self.procs )
	1764	print 'proc_id = %d' % proc_id
	1765	print 'nb_coprocs = %d' % len( self.coprocs )
	1766	print 'coproc_id = %d' % coproc_id
	1767	print 'nb_periphs = %d' % len( self.periphs )
	1768	print 'periph_id = %d' % periph_id
	1769
	1770	return byte_stream
	1771
	1772	###########################################################################################
[305]	1773	class Vspace( object ):
[319]	1774	###########################################################################################
	1775	def __init__( self,
	1776	name,
	1777	startname ):
	1778
	1779	self.index = 0 # global index ( set by addVspace() )
	1780	self.name = name # vspace name
[305]	1781	self.startname = startname # name of vobj containing the start_vector
[319]	1782	self.vsegs = []
[305]	1783	self.tasks = []
	1784
	1785	return
	1786
[319]	1787	################
	1788	def xml( self ): # xml for one vspace
	1789
[305]	1790	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
[319]	1791	for vseg in self.vsegs: s += vseg.xml()
	1792	for task in self.tasks: s += task.xml()
[305]	1793	s += ' </vspace>\n'
[319]	1794
[305]	1795	return s
	1796
[319]	1797	#############################################
	1798	def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace
	1799
	1800	if ( verbose ):
	1801	print '*** cbin for vspace %s' % (self.name)
	1802
	1803	# check index
	1804	if (self.index != expected):
[348]	1805	print '[genmap error] in Vspace.cbin() : vspace global index = %d / expected = %d' \
[319]	1806	% (self.index, expected )
	1807	sys.exit(1)
	1808
	1809	# compute global index for vobj containing start_vector
	1810	vobj_start_id = 0xFFFFFFFF
	1811	for vseg in self.vsegs:
	1812	if ( vseg.vobjs[0].name == self.startname ):
	1813	vobj_start_id = vseg.vobjs[0].index
	1814	if ( vobj_start_id == 0xFFFFFFFF ):
[348]	1815	print '[genmap error] in Vspace.cbin() : startname %s not found for vspace %s' \
[319]	1816	% ( self.startname, self.name )
	1817	sys.exit(1)
	1818
	1819	# compute first vseg, vobj, task global index
	1820	first_vseg_id = self.vsegs[0].index
	1821	first_vobj_id = self.vsegs[0].vobjs[0].index
	1822	first_task_id = self.tasks[0].index
	1823
	1824	# compute number of vobjs, tasks, vsegs
	1825	nb_vsegs = len( self.vsegs )
	1826	nb_tasks = len( self.tasks )
	1827	nb_vobjs = 0
	1828	for vseg in self.vsegs:
	1829	nb_vobjs += len( vseg.vobjs )
	1830
	1831	byte_stream = bytearray()
	1832	byte_stream += mapping.str2bytes( 32, self.name ) # vspace name
	1833	byte_stream += mapping.int2bytes( 4, vobj_start_id ) # vobj start_vector
	1834	byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs
	1835	byte_stream += mapping.int2bytes( 4, nb_vobjs ) # number of vobjs
	1836	byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks
	1837	byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index
	1838	byte_stream += mapping.int2bytes( 4, first_vobj_id ) # first vobj global index
	1839	byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index
	1840
	1841	if ( verbose ):
	1842	print 'start_id = %d' % vobj_start_id
	1843	print 'nb_vsegs = %d' % nb_vsegs
	1844	print 'nb_vobjs = %d' % nb_vobjs
	1845	print 'nb_tasks = %d' % nb_tasks
	1846	print 'vseg_id = %d' % first_vseg_id
	1847	print 'vobj_id = %d' % first_vobj_id
	1848	print 'task_id = %d' % first_task_id
	1849
	1850	return byte_stream
	1851
	1852	###########################################################################################
[305]	1853	class Task( object ):
[319]	1854	###########################################################################################
	1855	def __init__( self,
	1856	name,
	1857	trdid,
	1858	x,
	1859	y,
	1860	p,
	1861	stackname,
	1862	heapname,
	1863	startid,
	1864	usetty = False,
	1865	usenic = False,
	1866	usecma = False,
	1867	usehba = False,
	1868	usetim = False ):
	1869
	1870	self.index = 0 # global index value set by addTask()
	1871	self.name = name # tsk name
	1872	self.trdid = trdid # task index (unique in vspace)
	1873	self.x = x # cluster x coordinate
	1874	self.y = y # cluster y coordinate
	1875	self.p = p # processor local index
	1876	self.stackname = stackname # name of vobj containing the stack
	1877	self.heapname = heapname # name of vobj containing the heap
	1878	self.startid = startid # index in start_vector
	1879	self.usetty = usetty # request a private TTY channel
	1880	self.usenic = usenic # request a private NIC channel
	1881	self.usecma = usecma # request a private CMA channel
	1882	self.usehba = usehba # request a private HBA channel
	1883	self.usetim = usetim # request a private TIM channel
[305]	1884	return
	1885
[319]	1886	################
	1887	def xml( self ): # xml for one task
	1888
	1889	s = ' <task name="%s"' % self.name
	1890	s += ' trdid="%d"' % self.trdid
	1891	s += ' x="%d"' % self.x
	1892	s += ' y="%d"' % self.y
	1893	s += ' p="%d"' % self.p
	1894	s += ' stackname="%s"' % self.stackname
	1895	s += ' heapname="%s"' % self.heapname
	1896	s += ' startid="%d"' % self.startid
	1897	if self.usetty != 0: s += ' usetty="1"'
	1898	if self.usenic != 0: s += ' usenic="1"'
	1899	if self.usecma != 0: s += ' usehba="1"'
	1900	if self.usehba != 0: s += ' usehba="1"'
	1901	if self.usetim != 0: s += ' usehba="1"'
[305]	1902	s += ' />\n'
[319]	1903
[305]	1904	return s
	1905
[319]	1906	#####################################################
	1907	def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task
	1908
	1909	if ( verbose ):
	1910	print '*** cbin for task %s in vspace %s' % (self.name, vspace.name)
	1911
	1912	# check index
	1913	if (self.index != expected):
[348]	1914	print '[genmap error] in Task.cbin() : task global index = %d / expected = %d' \
[319]	1915	% (self.index, expected )
	1916	sys.exit(1)
	1917
	1918	# compute cluster global index
	1919	cluster_id = (self.x * mapping.y_size) + self.y
	1920
	1921	# compute vobj local index for stack
	1922	vobj_stack_id = 0xFFFFFFFF
	1923	for vseg in vspace.vsegs:
	1924	if ( vseg.vobjs[0].name == self.stackname ):
	1925	vobj_stack_id = vseg.vobjs[0].index
	1926	if ( vobj_stack_id == 0xFFFFFFFF ):
[348]	1927	print '[genmap error] in Task.cbin() : stackname %s not found for task %s in vspace %s' \
[319]	1928	% ( self.stackname, self.name, vspace.name )
	1929	sys.exit(1)
	1930
	1931	# compute vobj local index for heap
	1932	vobj_heap_id = 0xFFFFFFFF
	1933	for vseg in vspace.vsegs:
	1934	if ( vseg.vobjs[0].name == self.heapname ):
	1935	vobj_heap_id = vseg.vobjs[0].index
	1936	if ( vobj_heap_id == 0xFFFFFFFF ):
[348]	1937	print '[genmap error] in Task.cbin() : heapname %s not found for task %s in vspace %s' \
[319]	1938	% ( self.heapname, self.name, vspace.name )
	1939	sys.exit(1)
	1940
	1941	byte_stream = bytearray()
	1942	byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace
	1943	byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index
	1944	byte_stream += mapping.int2bytes( 4, self.p ) # processor local index in cluster
	1945	byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace
	1946	byte_stream += mapping.int2bytes( 4, vobj_stack_id ) # stack vobj local index
	1947	byte_stream += mapping.int2bytes( 4, vobj_heap_id ) # heap vobj local index
	1948	byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector
	1949	byte_stream += mapping.int2bytes( 4, self.usetty ) # TTY channel required
	1950	byte_stream += mapping.int2bytes( 4, self.usenic ) # NIC channel required
	1951	byte_stream += mapping.int2bytes( 4, self.usecma ) # CMA channel required
	1952	byte_stream += mapping.int2bytes( 4, self.usehba ) # IOC channel required
	1953	byte_stream += mapping.int2bytes( 4, self.usetim ) # TIM channel required
	1954
	1955	if ( verbose ):
	1956	print 'clusterid = %d' % cluster_id
	1957	print 'lpid = %d' % self.p
	1958	print 'trdid = %d' % self.trdid
	1959	print 'stackid = %d' % vobj_stack_id
	1960	print 'heapid = %d' % vobj_heap_id
	1961	print 'startid = %d' % self.startid
	1962
	1963	return byte_stream
	1964
	1965	###########################################################################################
[305]	1966	class Vseg( object ):
[319]	1967	###########################################################################################
	1968	def __init__( self,
	1969	name,
	1970	vbase,
	1971	mode,
	1972	x,
	1973	y,
	1974	psegname,
[348]	1975	identity = False,
	1976	local = False ):
[305]	1977
[319]	1978	assert mode in VSEGMODES
	1979
[348]	1980	self.index = 0 # global index ( set by addVseg() )
	1981	self.name = name # vseg name
	1982	self.vbase = vbase & 0xFFFFFFFF # virtual base address in vspace
	1983	self.mode = mode # CXWU access rights
	1984	self.x = x # x coordinate of destination cluster
	1985	self.y = y # y coordinate of destination cluster
	1986	self.psegname = psegname # name of pseg in destination cluster
	1987	self.identity = identity # identity mapping required
	1988	self.local = local # one copy per cluster
	1989	self.vobjs = []
[305]	1990	return
	1991
[319]	1992	################
	1993	def xml( self ): # xml for one vseg
	1994
	1995	s = ' <vseg name="%s" vbase="0x%x" mode="%s" x="%d" y="%d" psegname="%s"' \
	1996	% ( self.name, self.vbase, self.mode, self.x, self.y, self.psegname )
[348]	1997	if ( self.identity ): s += ' ident="1"'
	1998	if ( self.local ): s += ' local="1"'
	1999	s += ' >\n'
	2000	for vobj in self.vobjs: s += vobj.xml()
[319]	2001	s += ' </vseg>\n'
	2002
[305]	2003	return s
	2004
[319]	2005	#############################################
	2006	def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg
	2007
	2008	if ( verbose ):
	2009	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
	2010
	2011	# check index
	2012	if (self.index != expected):
[348]	2013	print '[genmap error] in Vseg.cbin() : vseg global index = %d / expected = %d' \
[319]	2014	% (self.index, expected )
	2015	sys.exit(1)
	2016
	2017	# compute pseg_id
	2018	pseg_id = 0xFFFFFFFF
	2019	cluster_id = (self.x * mapping.y_size) + self.y
	2020	cluster = mapping.clusters[cluster_id]
	2021	for pseg in cluster.psegs:
	2022	if (self.psegname == pseg.name):
	2023	pseg_id = pseg.index
	2024	if (pseg_id == 0xFFFFFFFF):
[348]	2025	print '[genmap error] in Vseg.cbin() : psegname %s not found for vseg %s in cluster %d' \
[319]	2026	% ( self.psegname, self.name, cluster_id )
	2027	sys.exit(1)
	2028
	2029	# compute numerical value for mode
	2030	mode_id = 0xFFFFFFFF
	2031	for x in xrange( len(VSEGMODES) ):
	2032	if ( self.mode == VSEGMODES[x] ):
	2033	mode_id = x
	2034	if ( mode_id == 0xFFFFFFFF ):
[348]	2035	print '[genmap error] in Vseg.cbin() : undefined vseg mode %s' % self.mode
[319]	2036	sys.exit(1)
	2037
	2038	# compute vobj_id
	2039	vobj_id = self.vobjs[0].index
	2040
	2041	byte_stream = bytearray()
	2042	byte_stream += mapping.str2bytes( 32, self.name ) # vseg name
	2043	byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address
	2044	byte_stream += mapping.int2bytes( 8, 0 ) # physical base address
	2045	byte_stream += mapping.int2bytes( 4, 0 ) # vseg size (bytes)
	2046	byte_stream += mapping.int2bytes( 4, pseg_id ) # physical segment global index
	2047	byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags
	2048	byte_stream += mapping.int2bytes( 4, len(self.vobjs) ) # number of vobjs in vseg
	2049	byte_stream += mapping.int2bytes( 4, vobj_id ) # first vobj global index
	2050	byte_stream += mapping.int2bytes( 4, 0 ) # linked list of vsegs on same pseg
	2051	byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero
[348]	2052	byte_stream += mapping.int2bytes( 1, self.identity ) # identity mapping when non zero
	2053	byte_stream += mapping.int2bytes( 1, self.local ) # non shared if non zero
	2054	byte_stream += mapping.int2bytes( 1, 0 ) # reserved (padding)
[319]	2055
	2056	if ( verbose ):
	2057	print 'vbase = %x' % self.vbase
	2058	print 'pseg_id = %d' % pseg_id
	2059	print 'mode = %s' % self.mode
	2060	print 'nb_vobjs = %d' % len(self.vobjs)
	2061	print 'vobj_id = %d' % vobj_id
	2062
	2063	return byte_stream
	2064
	2065	###########################################################################################
[305]	2066	class Vobj( object ):
[319]	2067	###########################################################################################
	2068	def __init__( self,
	2069	name,
	2070	length,
	2071	vtype,
	2072	binpath = '',
	2073	align = 0,
	2074	init = 0 ):
	2075
[305]	2076	assert vtype in ['ELF','BLOB','PTAB','PERI','MWMR','LOCK', \
	2077	'BUFFER','BARRIER','CONST','MEMSPACE','SCHED']
[319]	2078
	2079	assert (vtype != 'ELF') or (binpath != '')
	2080
	2081	self.index = 0 # global index ( set by addVobj() )
	2082	self.name = name # vobj name (unique in vspace)
	2083	self.vtype = vtype # vobj type (defined in mapping_info.h)
	2084	self.length = length # vobj size (bytes)
	2085	self.binpath = binpath # pathname for (ELF type)
	2086	self.align = align # required alignment (logarithm of 2)
	2087	self.init = init # initialisation value (for BARRIER or MWMR types)
	2088
[305]	2089	return
	2090
[319]	2091	################
	2092	def xml( self ): # xml for a vobj
	2093
[305]	2094	s = ' <vobj name="%s" type="%s" length="0x%x"' \
	2095	% ( self.name, self.vtype, self.length )
[319]	2096	if (self.binpath != ''): s += ' binpath="%s"' % (self.binpath)
	2097	if (self.align != 0 ): s += ' align="%d"' % (self.align)
	2098	if (self.init != 0 ): s += ' init="%d"' % (self.init)
[305]	2099	s += ' />\n'
[319]	2100
[305]	2101	return s
	2102
[319]	2103	#############################################
	2104	def cbin( self, mapping, verbose, expected ): # C binary structure for Vobj
[305]	2105
[319]	2106	# check index
	2107	if (self.index != expected):
[348]	2108	print '[genmap error] in Vobj.cbin() : vobj global index = %d / expected = %d' \
[319]	2109	% (self.index, expected )
	2110	sys.exit(1)
	2111	elif ( verbose ):
	2112	print '*** cbin for vobj[%d] %s' % (self.index, self.name)
[305]	2113
[319]	2114	# compute numerical value for vtype
	2115	vtype_int = 0xFFFFFFFF
	2116	for x in xrange( len(VOBJTYPES) ):
	2117	if ( self.vtype == VOBJTYPES[x] ):
	2118	vtype_int = x
	2119	if ( vtype_int == 0xFFFFFFFF ):
[348]	2120	print '[genmap error] in Vobj.cbin() : undefined vobj type %s' % self.vtype
[319]	2121	sys.exit(1)
	2122
	2123	byte_stream = bytearray()
	2124	byte_stream += mapping.str2bytes( 32, self.name ) # vobj name
	2125	byte_stream += mapping.str2bytes( 64, self.binpath ) # pathname for .elf file
	2126	byte_stream += mapping.int2bytes( 4 , vtype_int ) # vobj type
	2127	byte_stream += mapping.int2bytes( 4 , self.length ) # vobj size
	2128	byte_stream += mapping.int2bytes( 4 , self.align ) # required alignment
	2129	byte_stream += mapping.int2bytes( 4 , 0 ) # virtual base address
	2130	byte_stream += mapping.int2bytes( 8 , 0 ) # physical base address
	2131	byte_stream += mapping.int2bytes( 4 , self.init ) # init value
	2132
	2133	if ( verbose ):
	2134	print 'binpath = %s' % self.binpath
	2135	print 'type = %s' % self.vtype
	2136	print 'length = %x' % self.length
	2137
	2138	return byte_stream
	2139
	2140	###########################################################################################
[305]	2141	class Processor ( object ):
[319]	2142	###########################################################################################
	2143	def __init__( self,
	2144	x,
	2145	y,
	2146	lpid ):
	2147
	2148	self.index = 0 # global index ( set by addProc() )
	2149	self.x = x # x cluster coordinate
	2150	self.y = y # y cluster coordinate
	2151	self.lpid = lpid # processor local index
	2152
[305]	2153	return
	2154
[319]	2155	################
	2156	def xml( self ): # xml for a processor
[305]	2157	return ' <proc index="%d" />\n' % (self.lpid)
	2158
[319]	2159	#############################################
	2160	def cbin( self, mapping, verbose, expected ): # C binary structure for Proc
	2161
	2162	if ( verbose ):
	2163	print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y)
	2164
	2165	# check index
	2166	if (self.index != expected):
[348]	2167	print '[genmap error] in Proc.cbin() : proc global index = %d / expected = %d' \
[319]	2168	% (self.index, expected )
	2169	sys.exit(1)
	2170
	2171	byte_stream = bytearray()
	2172	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
	2173
	2174	return byte_stream
	2175
	2176	###########################################################################################
[305]	2177	class Pseg ( object ):
[319]	2178	###########################################################################################
	2179	def __init__( self,
	2180	name,
	2181	base,
	2182	size,
	2183	x,
	2184	y,
	2185	segtype ):
	2186
	2187	assert( segtype in PSEGTYPES )
	2188
	2189	self.index = 0 # global index ( set by addPseg() )
	2190	self.name = name # pseg name (unique in cluster)
	2191	self.base = base # physical base address
	2192	self.size = size # segment size (bytes)
	2193	self.x = x # cluster x coordinate
	2194	self.y = y # cluster y coordinate
	2195	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
	2196
[305]	2197	return
	2198
[319]	2199	################
	2200	def xml( self ): # xml for a pseg
	2201
[305]	2202	return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
	2203	% (self.name, self.segtype, self.base, self.size)
	2204
[319]	2205	######################################################
	2206	def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg
	2207
	2208	if ( verbose ):
	2209	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
	2210	% (self.index, self.name, cluster.x, cluster.y)
	2211
	2212	# check index
	2213	if (self.index != expected):
[348]	2214	print '[genmap error] in Pseg.cbin() : pseg global index = %d / expected = %d' \
[319]	2215	% (self.index, expected )
	2216	sys.exit(1)
	2217
	2218	# compute numerical value for segtype
	2219	segtype_int = 0xFFFFFFFF
	2220	for x in xrange( len(PSEGTYPES) ):
	2221	if ( self.segtype == PSEGTYPES[x] ):
	2222	segtype_int = x
	2223	if ( segtype_int == 0xFFFFFFFF ):
[348]	2224	print '[genmap error] in Pseg.cbin() : undefined segment type %s' % self.segtype
[319]	2225	sys.exit(1)
	2226
	2227	byte_stream = bytearray()
	2228	byte_stream += mapping.str2bytes( 32, self.name ) # pseg name
	2229	byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address
	2230	byte_stream += mapping.int2bytes( 8 , self.size ) # segment length
	2231	byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type
	2232	byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index
	2233	byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs
	2234
	2235	if ( verbose ):
	2236	print 'pbase = %x' % self.base
	2237	print 'size = %x' % self.size
	2238	print 'type = %s' % self.segtype
	2239
	2240	return byte_stream
	2241
	2242	###########################################################################################
	2243	class Periph ( object ):
	2244	###########################################################################################
	2245	def __init__( self,
	2246	pseg, # associated pseg
	2247	ptype, # peripheral type
	2248	subtype = 'NONE', # peripheral subtype
	2249	channels = 1, # for multi-channels peripherals
	2250	arg = 0 ): # optional argument (semantic depends on ptype)
	2251
	2252	assert ptype in PERIPHTYPES
	2253
	2254	assert subtype in PERIPHSUBTYPES
	2255
	2256	self.index = 0 # global index ( set by addPeriph() )
	2257	self.channels = channels
	2258	self.ptype = ptype
	2259	self.subtype = subtype
	2260	self.arg = arg
	2261	self.pseg = pseg
	2262	self.irqs = []
[305]	2263	return
	2264
[319]	2265	################
	2266	def xml( self ): # xml for a periph
	2267
	2268	s = ' <periph type="%s"' % self.ptype
	2269	s += ' subtype="%s"' % self.subtype
	2270	s += ' psegname="%s"' % self.pseg.name
	2271	s += ' channels="%d"' % self.channels
	2272	s += ' arg="%d" >\n' % self.arg
	2273	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') or (self.ptype == 'ICU') ):
	2274	for irq in self.irqs: s += irq.xml()
[305]	2275	s += ' </periph>\n'
[319]	2276
[305]	2277	return s
	2278
[319]	2279	#############################################
	2280	def cbin( self, mapping, verbose, expected ): # C binary structure for Periph
[305]	2281
[319]	2282	if ( verbose ):
	2283	print '*** cbin for periph %s in cluster [%d,%d]' \
	2284	% (self.ptype, self.pseg.x, self.pseg.y)
[305]	2285
[319]	2286	# check index
	2287	if (self.index != expected):
[348]	2288	print '[genmap error] in Periph.cbin() : periph global index = %d / expected = %d' \
[319]	2289	% (self.index, expected )
	2290	sys.exit(1)
[305]	2291
[319]	2292	# compute pseg global index
	2293	pseg_id = self.pseg.index
[305]	2294
[319]	2295	# compute first irq global index
	2296	if ( len(self.irqs) > 0 ):
	2297	irq_id = self.irqs[0].index
	2298	else:
	2299	irq_id = 0
[305]	2300
[319]	2301	# compute numerical value for ptype
	2302	ptype_id = 0xFFFFFFFF
	2303	for x in xrange( len(PERIPHTYPES) ):
	2304	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
	2305	if ( ptype_id == 0xFFFFFFFF ):
[348]	2306	print '[genmap error] in Periph.cbin() : undefined peripheral type %s' % self.ptype
[319]	2307	sys.exit(1)
[305]	2308
[319]	2309	# compute numerical value for subtype
	2310	subtype_id = 0xFFFFFFFF
	2311	for x in xrange( len(PERIPHSUBTYPES) ):
	2312	if ( self.subtype == PERIPHSUBTYPES[x] ): subtype_id = x
[305]	2313
[319]	2314	# compute
	2315	byte_stream = bytearray()
	2316	byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type
	2317	byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype
	2318	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
	2319	byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels
	2320	byte_stream += mapping.int2bytes( 4 , self.arg ) # optionnal argument
	2321	byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs
	2322	byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index
[305]	2323
[319]	2324	if ( verbose ):
	2325	print 'ptype = %d' % ptype_id
	2326	print 'pseg_id = %d' % pseg_id
	2327	print 'nb_irqs = %d' % len( self.irqs )
	2328	print 'irq_id = %d' % irq_id
	2329	return byte_stream
[305]	2330
[319]	2331	###########################################################################################
	2332	class Irq ( object ):
	2333	###########################################################################################
	2334	def __init__( self,
	2335	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
	2336	srcid, # input IRQ index (for XCU or PIC)
	2337	isrtype, # Type of ISR to be executed
	2338	channel = 0 ): # channel index for multi-channel ISR
[305]	2339
[319]	2340	assert irqtype in IRQTYPES
	2341	assert isrtype in ISRTYPES
	2342	assert srcid < 32
[305]	2343
[319]	2344	self.index = 0 # global index ( set by addIrq() )
	2345	self.irqtype = irqtype # IRQ type
	2346	self.srcid = srcid # source IRQ index
	2347	self.isrtype = isrtype # ISR type
	2348	self.channel = channel # channel index (for multi-channels ISR)
[305]	2349	return
	2350
[319]	2351	################
	2352	def xml( self ): # xml for Irq
[305]	2353
[319]	2354	return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
	2355	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
[305]	2356
[319]	2357	#############################################
	2358	def cbin( self, mapping, verbose, expected ): # C binary structure for Irq
[305]	2359
[319]	2360	if ( verbose ):
	2361	print '*** cbin for irq[%d]' % (self.index)
[305]	2362
[319]	2363	# check index
	2364	if (self.index != expected):
[348]	2365	print '[genmap error] in Irq.cbin() : irq global index = %d / expected = %d' \
[319]	2366	% (self.index, expected )
	2367	sys.exit(1)
[305]	2368
[319]	2369	# compute numerical value for irqtype
	2370	irqtype_id = 0xFFFFFFFF
	2371	for x in xrange( len(IRQTYPES) ):
	2372	if ( self.irqtype == IRQTYPES[x] ):
	2373	irqtype_id = x
	2374	if ( irqtype_id == 0xFFFFFFFF ):
[348]	2375	print '[genmap error] in Irq.cbin() : undefined irqtype %s' % self.irqtype
[319]	2376	sys.exit(1)
[305]	2377
[319]	2378	# compute numerical value for isrtype
	2379	isrtype_id = 0xFFFFFFFF
	2380	for x in xrange( len(ISRTYPES) ):
	2381	if ( self.isrtype == ISRTYPES[x] ):
	2382	isrtype_id = x
	2383	if ( isrtype_id == 0xFFFFFFFF ):
[348]	2384	print '[genmap error] in Irq.cbin() : undefined isrtype %s' % self.isrtype
[319]	2385	sys.exit(1)
	2386
	2387	byte_stream = bytearray()
	2388	byte_stream += mapping.int2bytes( 4, irqtype_id )
	2389	byte_stream += mapping.int2bytes( 4, self.srcid )
	2390	byte_stream += mapping.int2bytes( 4, isrtype_id )
	2391	byte_stream += mapping.int2bytes( 4, self.channel )
	2392	byte_stream += mapping.int2bytes( 4, 0 )
	2393	byte_stream += mapping.int2bytes( 4, 0 )
	2394
	2395	if ( verbose ):
	2396	print 'irqtype = %s' % self.irqtype
	2397	print 'srcid = %d' % self.srcid
	2398	print 'isrtype = %s' % self.isrtype
	2399	print 'channel = %d' % self.channel
	2400
	2401	return byte_stream
	2402
	2403	###########################################################################################
	2404	class Coproc ( object ):
	2405	###########################################################################################
	2406	def __init__( self,
	2407	pseg ): # associated pseg
	2408
	2409	self.index = 0 # global index value set by addCoproc()
	2410	self.pseg = pseg
	2411	self.ports = []
	2412
[305]	2413	return
	2414
[319]	2415	################
	2416	def xml( self ): # xml for Coproc
[305]	2417
[348]	2418	print '[genmap error] in Coproc.xml() : not defined yet'
[319]	2419	sys.exit(1)
	2420
	2421	return
	2422
	2423	#############################################
	2424	def cbin( self, mapping, verbose, expected ): # C binary structure for Coproc
	2425
	2426	if ( verbose ):
	2427	print '*** cbin for coproc in cluster (%d,%d)' % (self.pseg.x, self.pseg.y)
	2428
	2429	# check index
	2430	if (self.index != expected):
[348]	2431	print '[genmap error] in Coproc.cbin() : coproc global index = %d / expected = %d' \
[319]	2432	% (self.index, expected )
	2433	sys.exit(1)
	2434
	2435	# compute pseg global index
	2436	pseg_id = self.pseg.index
	2437
	2438	# compute first port global index
	2439	port_id = self.ports[0].index
	2440
	2441	byte_stream = bytearray()
	2442	byte_stream += mapping.str2bytes( 32, self.pseg.name ) # probablement inutile (AG)
	2443	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
	2444	byte_stream += mapping.int2bytes( 4 , len( self.ports ) ) # number of input irqs
	2445	byte_stream += mapping.int2bytes( 4 , port_id ) # first port global index
	2446
	2447	if ( verbose ):
	2448	print 'irqtype = %s' % self.irqtype
	2449	print 'pseg_id = %d' % pseg_id
	2450	print 'nb_ports = %d' % len( self.ports )
	2451	print 'port_id %d' % port_id
	2452
	2453	return byte_stream
	2454
	2455	###########################################################################################
	2456	class Cpport ( object ):
	2457	###########################################################################################
	2458	def __init__( self,
	2459	direction,
	2460	vspacename,
	2461	mwmrname ):
	2462
	2463	self.index = 0 # global index ( set by addCpport() )
	2464	self.direction = direction # TO_COPROC / FROM_COPROC
	2465	self.vspacename = vspacename # name of vspace containing mwmr channel
	2466	self.mwmrname = mwmrname # name of vobj defining mwmr channel
	2467
[305]	2468	return
	2469
[319]	2470	################
	2471	def xml( self ): # xml for Cpport
[305]	2472
[348]	2473	print '[genmap error] in Cpport.xml() : not defined yet'
[319]	2474	sys.exit(1)
[305]	2475
[319]	2476	return
	2477
	2478	#############################################
	2479	def cbin( self, mapping, verbose, expected ): # C binary structure for Cpport
	2480
	2481	if ( verbose ):
	2482	print '*** cbin for cpport[%d]' % (self.index)
	2483
	2484	# check index
	2485	if ( self.index != expected ):
[348]	2486	print '[genmap error] in Cpport.cbin() : port global index = %d / expected = %d' \
[319]	2487	% ( self.index, expected )
	2488	sys.exit(1)
	2489
	2490	# compute numerical value for direction
	2491	if ( self.direction == 'TO_COPROC' ):
	2492	dir_int = 0
	2493	else:
	2494	dir_int = 1
	2495
	2496	# compute vspace global index
	2497	vspace_id = 0xFFFFFFFF
	2498	for vspace in mapping.vspaces:
	2499	if ( self.vspacename == vspace.name ):
	2500	vspace_id = vspace.index
	2501	if (vspace_id == 0xFFFFFFFF):
[348]	2502	print '[genmap error] in Cpport.cbin() : vspace name %s not found' \
[319]	2503	% ( self.vspacename )
	2504	sys.exit(1)
	2505
	2506	# compute mwmr global index
	2507	mwmr_id = 0xFFFFFFFF
	2508	for vseg in mapping.vspace[vspace_id].vsegs:
	2509	for vobj in vseg.vobjs:
	2510	if (self.mwmrname == vobj.name):
	2511	mwmr_id = vobj.index
	2512	if (mwmr_id == 0xFFFFFFFF):
[348]	2513	print '[genmap error] in Cpport.cbin() : mwmr vobj name %s not found in vspace %s' \
[319]	2514	% ( self.mwmrname, self.vspacename )
	2515	sys.exit(1)
	2516
	2517	byte_stream = bytearray()
	2518	byte_stream += mapping.int2bytes( 4 , dir_int ) # pseg global index
	2519	byte_stream += mapping.int2bytes( 4 , vspace_id ) # vspace global index
	2520	byte_stream += mapping.int2bytes( 4 , mwmr_id ) # mwmr vobj global index
	2521
	2522	if ( verbose ):
	2523	print 'direction = %s' % self.direction
	2524	print 'vspace_id = %d' % vspace_id
	2525	print 'mwmr_id = %d' % mwmr_id
	2526
	2527	return byte_stream
	2528
	2529
[305]	2530	# Local Variables:
	2531	# tab-width: 4;
	2532	# c-basic-offset: 4;
	2533	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	2534	# indent-tabs-mode: nil;
	2535	# End:
	2536	#
	2537	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	2538

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