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source: soft/giet_vm/giet_python/mapping.py @ 529

Last change on this file since 529 was 526, checked in by cfuguet, 10 years ago
update linux_dts() function to comply with new device tree specs
Property svn:executable set to ``*
File size: 99.9 KB

Rev	Line
[425]	1	#!/usr/bin/env python
[305]	2
[319]	3	import sys
	4
[512]	5	########################################################################################
[305]	6	# file : giet_mapping.py
	7	# date : april 2014
	8	# author : Alain Greiner
[512]	9	########################################################################################
[319]	10	# This file contains the classes required to define a mapping for the GIET_VM.
	11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
[520]	12	# a set of 'Vseg' (kernel glogals virtual segments)
	13	# a set of 'Vspace' (one or several user applications)
[512]	14	# - A 'Cluster' contains a set of 'Pseg' (physical segments in cluster)
[319]	15	# a set of 'Proc' (processors in cluster)
	16	# a set of 'Periph' (peripherals in cluster)
[512]	17	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments)
	18	# a set of 'Task' (user parallel tasks)
[441]	19	# - A 'Periph' contains a set of 'Irq' (only for XCU and PIC types )
[512]	20	########################################################################################
[319]	21	# Implementation Note
[512]	22	# The objects used to describe a mapping are distributed in the PYTHON structure:
[319]	23	# For example the psegs set is split in several subsets (one subset per cluster),
	24	# or the tasks set is split in several subsets (one subset per vspace), etc...
	25	# In the C binary data structure used by the giet_vm, all objects of same type
[406]	26	# are stored in a linear array (one single array for all psegs for example).
[512]	27	# For all objects, we compute and store in the PYTHON object itself a "global index"
[406]	28	# corresponding to the index in this global array, and this index can be used as
[319]	29	# a pseudo-pointer to identify a specific object of a given type.
[512]	30	########################################################################################
[305]	31
[512]	32	########################################################################################
[411]	33	# Various constants
[512]	34	########################################################################################
[411]	35
	36	PADDR_WIDTH = 40 # number of bits for physical address
	37	X_WIDTH = 4 # number of bits encoding x coordinate
	38	Y_WIDTH = 4 # number of bits encoding y coordinate
	39	P_WIDTH = 4 # number of bits encoding local proc_id
	40	VPN_ANTI_MASK = 0x00000FFF # mask virtual address to get offset in a small page
	41	BPN_MASK = 0xFFE00000 # mask virtual address to get the BPN (big page)
[520]	42	PERI_INCREMENT = 0x10000 # virtual address increment for replicated l vsegs
[411]	43	RESET_ADDRESS = 0xBFC00000 # Processor wired boot_address
	44	MAPPING_SIGNATURE = 0xDACE2014 # Magic number indicating a valid C binary struture
	45
[512]	46	########################################################################################
[520]	47	# These lists must be consistent with values defined in
	48	# mapping_info.h / xml_driver.c /xml_parser.c
[512]	49	########################################################################################
[319]	50	PERIPHTYPES = [
	51	'CMA',
	52	'DMA',
	53	'FBF',
	54	'IOB',
	55	'IOC',
	56	'MMC',
	57	'MWR',
	58	'NIC',
	59	'ROM',
	60	'SIM',
	61	'TIM',
	62	'TTY',
	63	'XCU',
	64	'PIC',
[491]	65	'DROM',
[319]	66	]
	67
[520]	68	IOCSUBTYPES = [
[319]	69	'BDV',
	70	'HBA',
	71	'SPI',
	72	'NONE',
	73	]
	74
[520]	75	MWRSUBTYPES = [
	76	'GCD',
	77	'DCT',
	78	]
	79
	80	######################################################################################
	81	# These lists must be consistent with values defined in
	82	# irq_handler.c / irq_handler.h / xml_driver.c / xml_parser.c
	83	######################################################################################
[319]	84	IRQTYPES = [
	85	'HWI',
	86	'WTI',
	87	'PTI',
	88	]
	89
	90	ISRTYPES = [
	91	'ISR_DEFAULT',
	92	'ISR_TICK',
	93	'ISR_TTY_RX',
	94	'ISR_TTY_TX',
	95	'ISR_BDV',
	96	'ISR_TIMER',
	97	'ISR_WAKUP',
	98	'ISR_NIC_RX',
	99	'ISR_NIC_TX',
	100	'ISR_CMA',
	101	'ISR_MMC',
	102	'ISR_DMA',
	103	'ISR_SPI',
[520]	104	'ISR_MWR'
[319]	105	]
	106
[512]	107	VSEGTYPES = [
[319]	108	'ELF',
	109	'BLOB',
	110	'PTAB',
	111	'PERI',
[512]	112	'MWMR', # deprecated
	113	'LOCK', # deprecated
[319]	114	'BUFFER',
[512]	115	'BARRIER', # deprecated
	116	'CONST', # deprecated
	117	'MEMSPACE', # deprecated
	118	'SCHED',
[471]	119	'HEAP',
[319]	120	]
	121
	122	VSEGMODES = [
	123	'____',
	124	'___U',
	125	'__W_',
	126	'__WU',
	127	'_X__',
	128	'_X_U',
	129	'_XW_',
	130	'_XWU',
	131	'C___',
	132	'C__U',
	133	'C_W_',
	134	'C_WU',
	135	'CX__',
	136	'CX_U',
	137	'CXW_',
	138	'CXWU',
	139	]
	140
	141	PSEGTYPES = [
	142	'RAM',
	143	'PERI',
	144	]
	145
[512]	146	#######################################################################################
[305]	147	class Mapping( object ):
[512]	148	#######################################################################################
[305]	149	def __init__( self,
[411]	150	name, # mapping name
	151	x_size, # number of clusters in a row
	152	y_size, # number of clusters in a column
[421]	153	nprocs, # max number of processors per cluster
[411]	154	x_width = X_WIDTH, # number of bits encoding x coordinate
	155	y_width = Y_WIDTH, # number of bits encoding y coordinate
[512]	156	p_width = P_WIDTH, # number of bits encoding lpid
[411]	157	paddr_width = PADDR_WIDTH, # number of bits for physical address
[512]	158	coherence = 1, # hardware cache coherence if non-zero
[411]	159	irq_per_proc = 1, # number or IRQs from XCU to processor
	160	use_ramdisk = False, # use ramdisk when true
	161	x_io = 0, # cluster_io x coordinate
	162	y_io = 0, # cluster_io y coordinate
	163	peri_increment = PERI_INCREMENT, # address increment for globals
	164	reset_address = RESET_ADDRESS, # Processor wired boot_address
	165	ram_base = 0, # RAM physical base in cluster[0,0]
	166	ram_size = 0 ): # RAM size in each cluster (bytes)
[305]	167
[411]	168	assert ( x_size <= (1<<X_WIDTH) )
	169	assert ( y_size <= (1<<Y_WIDTH) )
	170	assert ( nprocs <= (1<<P_WIDTH) )
[406]	171
[411]	172	self.signature = MAPPING_SIGNATURE
[319]	173	self.name = name
[497]	174	self.name = name
[406]	175	self.paddr_width = paddr_width
[319]	176	self.coherence = coherence
	177	self.x_size = x_size
	178	self.y_size = y_size
[441]	179	self.nprocs = nprocs
[319]	180	self.x_width = x_width
	181	self.y_width = y_width
[406]	182	self.p_width = p_width
[319]	183	self.irq_per_proc = irq_per_proc
	184	self.use_ramdisk = use_ramdisk
	185	self.x_io = x_io
	186	self.y_io = y_io
[328]	187	self.peri_increment = peri_increment
[319]	188	self.reset_address = reset_address
[356]	189	self.ram_base = ram_base
	190	self.ram_size = ram_size
[305]	191
[319]	192	self.total_vspaces = 0
	193	self.total_globals = 0
	194	self.total_psegs = 0
	195	self.total_vsegs = 0
	196	self.total_tasks = 0
	197	self.total_procs = 0
	198	self.total_irqs = 0
	199	self.total_periphs = 0
[305]	200
[319]	201	self.clusters = []
	202	self.globs = []
	203	self.vspaces = []
[305]	204
[319]	205	for x in xrange( self.x_size ):
	206	for y in xrange( self.y_size ):
	207	cluster = Cluster( x , y )
[406]	208	cluster.index = (x * self.y_size) + y
[319]	209	self.clusters.append( cluster )
[305]	210
	211	return
	212
[319]	213	########################## add a ram pseg in a cluster
[406]	214	def addRam( self,
[319]	215	name, # pseg name
	216	base, # pseg base address
	217	size ): # pseg length (bytes)
[406]	218
[497]	219	# computes cluster index and coordinates from the base address
[356]	220	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
	221	cluster_xy = base >> paddr_lsb_width
[497]	222	x = cluster_xy >> (self.y_width);
	223	y = cluster_xy & ((1 << self.y_width) - 1)
	224	cluster_id = (x * self.y_size) + y
[305]	225
[411]	226	assert (base & VPN_ANTI_MASK) == 0
[319]	227
	228	assert (x < self.x_size) and (y < self.y_size)
[406]	229
[356]	230	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
	231
	232	assert ( size == self.ram_size )
	233
[319]	234	# add one pseg in the mapping
	235	pseg = Pseg( name, base, size, x, y, 'RAM' )
	236	self.clusters[cluster_id].psegs.append( pseg )
	237	pseg.index = self.total_psegs
	238	self.total_psegs += 1
	239
	240	return pseg
	241
[512]	242	########################## add a peripheral and the associated pseg in a cluster
[406]	243	def addPeriph( self,
[319]	244	name, # associated pseg name
	245	base, # associated pseg base address
	246	size, # associated pseg length (bytes)
[406]	247	ptype, # peripheral type
[319]	248	subtype = 'NONE', # peripheral subtype
	249	channels = 1, # number of channels
[520]	250	arg0 = 0, # optional argument (semantic depends on ptype)
	251	arg1 = 0, # optional argument (semantic depends on ptype)
	252	arg2 = 0, # optional argument (semantic depends on ptype)
	253	arg3 = 0 ): # optional argument (semantic depends on ptype)
[319]	254
[497]	255	# computes cluster index and coordinates from the base address
[319]	256	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
[497]	257	x = cluster_xy >> (self.y_width);
	258	y = cluster_xy & ((1 << self.y_width) - 1)
	259	cluster_id = (x * self.y_size) + y
[305]	260
[319]	261	assert (x < self.x_size) and (y < self.y_size)
	262
[411]	263	assert (base & VPN_ANTI_MASK) == 0
[319]	264
	265	assert ptype in PERIPHTYPES
	266
[520]	267	if (ptype == 'IOC'): assert subtype in IOCSUBTYPES
	268	if (ptype == 'MWR'): assert subtype in MWRSUBTYPES
[319]	269
	270	# add one pseg into mapping
	271	pseg = Pseg( name, base, size, x, y, 'PERI' )
	272	self.clusters[cluster_id].psegs.append( pseg )
	273	pseg.index = self.total_psegs
	274	self.total_psegs += 1
	275
	276	# add one periph into mapping
[520]	277	periph = Periph( pseg, ptype, subtype, channels, arg0, arg1, arg2, arg3 )
[319]	278	self.clusters[cluster_id].periphs.append( periph )
	279	periph.index = self.total_periphs
	280	self.total_periphs += 1
	281
	282	return periph
	283
	284	################################ add an IRQ in a peripheral
	285	def addIrq( self,
	286	periph, # peripheral containing IRQ (PIC or XCU)
	287	index, # peripheral input port index
	288	isrtype, # ISR type
	289	channel = 0 ): # channel for multi-channels ISR
	290
	291	assert isrtype in ISRTYPES
	292
	293	assert index < 32
	294
[406]	295	# add one irq into mapping
[319]	296	irq = Irq( 'HWI', index , isrtype, channel )
	297	periph.irqs.append( irq )
	298	irq.index = self.total_irqs
	299	self.total_irqs += 1
	300
	301	return irq
	302
	303	########################## add a processor in a cluster
[406]	304	def addProc( self,
[319]	305	x, # cluster x coordinate
	306	y, # cluster y coordinate
[520]	307	lpid ): # processor local index
[319]	308
	309	assert (x < self.x_size) and (y < self.y_size)
	310
	311	cluster_id = (x * self.y_size) + y
	312
[406]	313	# add one proc into mapping
[520]	314	proc = Processor( x, y, lpid )
[319]	315	self.clusters[cluster_id].procs.append( proc )
	316	proc.index = self.total_procs
[305]	317	self.total_procs += 1
	318
[319]	319	return proc
	320
[411]	321	############################ add one global vseg into mapping
	322	def addGlobal( self,
	323	name, # vseg name
	324	vbase, # virtual base address
[512]	325	length, # vseg length (bytes)
[411]	326	mode, # CXWU flags
[512]	327	vtype, # vseg type
[411]	328	x, # destination x coordinate
	329	y, # destination y coordinate
	330	pseg, # destination pseg name
	331	identity = False, # identity mapping required if true
	332	local = False, # only mapped in local PTAB if true
[512]	333	big = False, # to be mapped in a big physical page
	334	binpath = '' ): # pathname for binary code if required
[319]	335
[411]	336	# two global vsegs must not overlap if they have different names
	337	for prev in self.globs:
[512]	338	if ( ((prev.vbase + prev.length) > vbase ) and
	339	((vbase + length) > prev.vbase) and
[411]	340	(prev.name != name) ):
[512]	341	print '[genmap error] in addGlobal()'
	342	print ' global vseg %s overlap %s' % (name, prev.name)
	343	print ' %s : base = %x / size = %x' %( name, vbase, size )
	344	print ' %s : base = %x / size = %x' %( prev.name, prev.vbase, prev.size )
[411]	345	sys.exit(1)
	346
[328]	347	# add one vseg into mapping
[512]	348	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
	349	identity = identity, local = local, big = big, binpath = binpath )
[348]	350
[328]	351	self.globs.append( vseg )
	352	self.total_globals += 1
[406]	353	vseg.index = self.total_vsegs
[328]	354	self.total_vsegs += 1
[406]	355
[305]	356	return
	357
[319]	358	################################ add a vspace into mapping
[406]	359	def addVspace( self,
[319]	360	name, # vspace name
[512]	361	startname ): # name of vseg containing start_vector
[319]	362
	363	# add one vspace into mapping
	364	vspace = Vspace( name, startname )
[305]	365	self.vspaces.append( vspace )
[319]	366	vspace.index = self.total_vspaces
	367	self.total_vspaces += 1
	368
	369	return vspace
[406]	370
[512]	371	################################# add a private vseg in a vspace
[319]	372	def addVseg( self,
[406]	373	vspace, # vspace containing the vseg
[319]	374	name, # vseg name
	375	vbase, # virtual base address
[512]	376	length, # vseg length (bytes)
[319]	377	mode, # CXWU flags
[512]	378	vtype, # vseg type
[319]	379	x, # destination x coordinate
	380	y, # destination y coordinate
	381	pseg, # destination pseg name
[411]	382	local = False, # only mapped in local PTAB if true
[512]	383	big = False, # to be mapped in a big physical page
	384	binpath = '' ): # pathname for binary code
[319]	385
	386	assert mode in VSEGMODES
	387
[512]	388	assert vtype in VSEGTYPES
[319]	389
	390	assert (x < self.x_size) and (y < self.y_size)
	391
	392	# add one vseg into mapping
[512]	393	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
	394	identity = False, local = local, big = big, binpath = binpath )
[319]	395	vspace.vsegs.append( vseg )
	396	vseg.index = self.total_vsegs
	397	self.total_vsegs += 1
	398
	399	return vseg
	400
[406]	401	################################ add a task in a vspace
	402	def addTask( self,
[319]	403	vspace, # vspace containing task
	404	name, # task name
	405	trdid, # task index in vspace
	406	x, # destination x coordinate
	407	y, # destination y coordinate
	408	lpid, # destination processor local index
[512]	409	stackname, # name of vseg containing stack
	410	heapname, # name of vseg containing heap
[441]	411	startid ): # index in start_vector
[406]	412
[319]	413	assert (x < self.x_size) and (y < self.y_size)
[411]	414	assert lpid < self.nprocs
[319]	415
[406]	416	# add one task into mapping
[441]	417	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid )
[319]	418	vspace.tasks.append( task )
	419	task.index = self.total_tasks
	420	self.total_tasks += 1
	421
	422	return task
	423
	424	#################################
	425	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
	426
	427	byte_stream = bytearray()
	428	length = len( s )
	429	if length < (nbytes - 1):
	430	for b in s:
	431	byte_stream.append( b )
	432	for x in xrange(nbytes-length):
	433	byte_stream.append( '\0' )
	434	else:
[512]	435	print '[genmap error] in str2bytes()'
	436	print ' string %s too long' % s
[319]	437	sys.exit(1)
	438
	439	return byte_stream
	440
	441	###################################
[406]	442	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
[319]	443
	444	byte_stream = bytearray()
	445	for n in xrange( nbytes ):
	446	byte_stream.append( (val >> (n<<3)) & 0xFF )
	447
	448	return byte_stream
	449
[512]	450	################
[411]	451	def xml( self ): # compute string for map.xml file generation
[319]	452
[305]	453	s = '<?xml version="1.0"?>\n\n'
[319]	454	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
[305]	455	s += ' name = "%s"\n' % (self.name)
	456	s += ' x_size = "%d"\n' % (self.x_size)
	457	s += ' y_size = "%d"\n' % (self.y_size)
	458	s += ' x_width = "%d"\n' % (self.x_width)
	459	s += ' y_width = "%d"\n' % (self.y_width)
	460	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
[319]	461	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
[305]	462	s += ' x_io = "%d"\n' % (self.x_io)
	463	s += ' y_io = "%d" >\n' % (self.y_io)
[319]	464	s += '\n'
	465
[305]	466	s += ' <clusterset>\n'
	467	for x in xrange ( self.x_size ):
	468	for y in xrange ( self.y_size ):
[406]	469	cluster_id = (x * self.y_size) + y
[319]	470	s += self.clusters[cluster_id].xml()
[305]	471	s += ' </clusterset>\n'
[319]	472	s += '\n'
	473
[305]	474	s += ' <globalset>\n'
[319]	475	for vseg in self.globs: s += vseg.xml()
[305]	476	s += ' </globalset>\n'
[319]	477	s += '\n'
	478
[305]	479	s += ' <vspaceset>\n'
[319]	480	for vspace in self.vspaces: s += vspace.xml()
[305]	481	s += ' </vspaceset>\n'
[319]	482
[305]	483	s += '</mapping_info>\n'
	484	return s
[319]	485
[512]	486	##########################
[411]	487	def cbin( self, verbose ): # C binary structure for map.bin file generation
[319]	488
	489	byte_stream = bytearray()
	490
	491	# header
	492	byte_stream += self.int2bytes(4, self.signature)
[406]	493	byte_stream += self.int2bytes(4, self.x_size)
	494	byte_stream += self.int2bytes(4, self.y_size)
	495	byte_stream += self.int2bytes(4, self.x_width)
	496	byte_stream += self.int2bytes(4, self.y_width)
	497	byte_stream += self.int2bytes(4, self.x_io)
	498	byte_stream += self.int2bytes(4, self.y_io)
	499	byte_stream += self.int2bytes(4, self.irq_per_proc)
	500	byte_stream += self.int2bytes(4, self.use_ramdisk)
	501	byte_stream += self.int2bytes(4, self.total_globals)
	502	byte_stream += self.int2bytes(4, self.total_vspaces)
	503	byte_stream += self.int2bytes(4, self.total_psegs)
	504	byte_stream += self.int2bytes(4, self.total_vsegs)
	505	byte_stream += self.int2bytes(4, self.total_tasks)
	506	byte_stream += self.int2bytes(4, self.total_procs)
	507	byte_stream += self.int2bytes(4, self.total_irqs)
	508	byte_stream += self.int2bytes(4, self.total_periphs)
[319]	509	byte_stream += self.str2bytes(32, self.name)
	510
	511	if ( verbose ):
[406]	512	print '\n'
[319]	513	print 'name = %s' % self.name
	514	print 'signature = %x' % self.signature
	515	print 'x_size = %d' % self.x_size
	516	print 'y_size = %d' % self.y_size
	517	print 'x_width = %d' % self.x_width
	518	print 'y_width = %d' % self.y_width
[406]	519	print 'x_io = %d' % self.x_io
	520	print 'y_io = %d' % self.y_io
[319]	521	print 'irq_per_proc = %d' % self.irq_per_proc
	522	print 'use_ramdisk = %d' % self.use_ramdisk
	523	print 'total_globals = %d' % self.total_globals
[406]	524	print 'total_psegs = %d' % self.total_psegs
	525	print 'total_vsegs = %d' % self.total_vsegs
	526	print 'total_tasks = %d' % self.total_tasks
	527	print 'total_procs = %d' % self.total_procs
	528	print 'total_irqs = %d' % self.total_irqs
[319]	529	print 'total_periphs = %d' % self.total_periphs
[406]	530	print '\n'
[319]	531
	532	# clusters array
	533	index = 0
	534	for cluster in self.clusters:
	535	byte_stream += cluster.cbin( self, verbose, index )
	536	index += 1
	537
	538	if ( verbose ): print '\n'
	539
	540	# psegs array
	541	index = 0
	542	for cluster in self.clusters:
[406]	543	for pseg in cluster.psegs:
[319]	544	byte_stream += pseg.cbin( self, verbose, index, cluster )
	545	index += 1
	546
	547	if ( verbose ): print '\n'
	548
	549	# vspaces array
	550	index = 0
[406]	551	for vspace in self.vspaces:
	552	byte_stream += vspace.cbin( self, verbose, index )
[319]	553	index += 1
	554
	555	if ( verbose ): print '\n'
	556
	557	# vsegs array
	558	index = 0
	559	for vseg in self.globs:
	560	byte_stream += vseg.cbin( self, verbose, index )
	561	index += 1
	562	for vspace in self.vspaces:
[406]	563	for vseg in vspace.vsegs:
[319]	564	byte_stream += vseg.cbin( self, verbose, index )
	565	index += 1
	566
	567	if ( verbose ): print '\n'
	568
	569	# tasks array
	570	index = 0
	571	for vspace in self.vspaces:
[406]	572	for task in vspace.tasks:
[319]	573	byte_stream += task.cbin( self, verbose, index, vspace )
	574	index += 1
	575
	576	if ( verbose ): print '\n'
	577
	578	# procs array
	579	index = 0
	580	for cluster in self.clusters:
[406]	581	for proc in cluster.procs:
[319]	582	byte_stream += proc.cbin( self, verbose, index )
	583	index += 1
[406]	584
[319]	585	if ( verbose ): print '\n'
	586
	587	# irqs array
[406]	588	index = 0
[319]	589	for cluster in self.clusters:
	590	for periph in cluster.periphs:
	591	for irq in periph.irqs:
	592	byte_stream += irq.cbin( self, verbose, index )
	593	index += 1
	594
	595	if ( verbose ): print '\n'
	596
	597	# periphs array
	598	index = 0
	599	for cluster in self.clusters:
[406]	600	for periph in cluster.periphs:
[319]	601	byte_stream += periph.cbin( self, verbose, index )
	602	index += 1
	603
	604	return byte_stream
	605	# end of cbin()
[406]	606
[411]	607	##################################################################################
	608	def giet_vsegs( self ): # compute string for giet_vsegs.ld file generation
[319]	609	# required by giet_vm compilation
	610
[406]	611	# search the vsegs required for the giet_vsegs.ld
[319]	612	boot_code_found = False
	613	boot_data_found = False
	614	kernel_uncdata_found = False
	615	kernel_data_found = False
	616	kernel_code_found = False
	617	kernel_init_found = False
	618	for vseg in self.globs:
[348]	619
[319]	620	if ( vseg.name == 'seg_boot_code' ):
[406]	621	boot_code_vbase = vseg.vbase
[512]	622	boot_code_size = vseg.length
[319]	623	boot_code_found = True
	624
[406]	625	if ( vseg.name == 'seg_boot_data' ):
	626	boot_data_vbase = vseg.vbase
[512]	627	boot_data_size = vseg.length
[319]	628	boot_data_found = True
	629
	630	if ( vseg.name == 'seg_kernel_data' ):
[406]	631	kernel_data_vbase = vseg.vbase
[512]	632	kernel_data_size = vseg.length
[319]	633	kernel_data_found = True
	634
	635	if ( vseg.name == 'seg_kernel_code' ):
[406]	636	kernel_code_vbase = vseg.vbase
[512]	637	kernel_code_size = vseg.length
[319]	638	kernel_code_found = True
	639
	640	if ( vseg.name == 'seg_kernel_init' ):
[406]	641	kernel_init_vbase = vseg.vbase
[512]	642	kernel_init_size = vseg.length
[319]	643	kernel_init_found = True
	644
	645	# check if all required vsegs have been found
[406]	646	if ( boot_code_found == False ):
[512]	647	print '[genmap error] in giet_vsegs()'
	648	print ' seg_boot_code vseg missing'
[319]	649	sys.exit()
	650
[406]	651	if ( boot_data_found == False ):
[512]	652	print '[genmap error] in giet_vsegs()'
	653	print ' seg_boot_data vseg missing'
[319]	654	sys.exit()
	655
[406]	656	if ( kernel_data_found == False ):
[512]	657	print '[genmap error] in giet_vsegs()'
	658	print ' seg_kernel_data vseg missing'
[319]	659	sys.exit()
	660
	661	if ( kernel_code_found == False ):
[512]	662	print '[genmap error] in giet_vsegs()'
	663	print ' seg_kernel_code vseg missing'
[319]	664	sys.exit()
	665
	666	if ( kernel_init_found == False ):
[512]	667	print '[genmap error] in giet_vsegs()'
	668	print ' seg_kernel_init vseg missing'
[319]	669	sys.exit()
	670
	671	# build string
[406]	672	s = '/* Generated by genmap for %s */\n' % self.name
[319]	673	s += '\n'
	674
[406]	675	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
	676	s += 'boot_code_size = 0x%x;\n' % boot_code_size
[319]	677	s += '\n'
[406]	678	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
	679	s += 'boot_data_size = 0x%x;\n' % boot_data_size
[319]	680	s += '\n'
[406]	681	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
	682	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
[319]	683	s += '\n'
[406]	684	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
	685	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
[319]	686	s += '\n'
[406]	687	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
	688	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
[319]	689	s += '\n'
	690
	691	return s
[406]	692
[411]	693	###################################################################################
	694	def hard_config( self ): # compute string for hard_config.h file generation,
	695	# required by
[319]	696	# - top.cpp compilation
	697	# - giet_vm compilation
	698	# - tsar_preloader compilation
	699
	700	nb_total_procs = 0
	701
	702	# for each peripheral type, define default values
[406]	703	# for pbase address, size, number of components, and channels
[319]	704	nb_cma = 0
	705	cma_channels = 0
	706	seg_cma_base = 0xFFFFFFFF
	707	seg_cma_size = 0
	708
	709	nb_dma = 0
	710	dma_channels = 0
	711	seg_dma_base = 0xFFFFFFFF
	712	seg_dma_size = 0
	713
	714	nb_fbf = 0
	715	fbf_channels = 0
	716	seg_fbf_base = 0xFFFFFFFF
	717	seg_fbf_size = 0
[520]	718	fbf_arg0 = 0
	719	fbf_arg1 = 0
[319]	720
	721	nb_iob = 0
	722	iob_channels = 0
	723	seg_iob_base = 0xFFFFFFFF
	724	seg_iob_size = 0
	725
	726	nb_ioc = 0
	727	ioc_channels = 0
	728	seg_ioc_base = 0xFFFFFFFF
	729	seg_ioc_size = 0
	730
	731	nb_mmc = 0
	732	mmc_channels = 0
	733	seg_mmc_base = 0xFFFFFFFF
	734	seg_mmc_size = 0
	735
	736	nb_mwr = 0
	737	mwr_channels = 0
	738	seg_mwr_base = 0xFFFFFFFF
	739	seg_mwr_size = 0
[520]	740	mwr_arg0 = 0
	741	mwr_arg1 = 0
	742	mwr_arg2 = 0
	743	mwr_arg3 = 0
[319]	744
	745	nb_nic = 0
	746	nic_channels = 0
	747	seg_nic_base = 0xFFFFFFFF
	748	seg_nic_size = 0
	749
	750	nb_pic = 0
	751	pic_channels = 0
	752	seg_pic_base = 0xFFFFFFFF
	753	seg_pic_size = 0
	754
	755	nb_rom = 0
	756	rom_channels = 0
	757	seg_rom_base = 0xFFFFFFFF
	758	seg_rom_size = 0
	759
	760	nb_sim = 0
	761	sim_channels = 0
	762	seg_sim_base = 0xFFFFFFFF
	763	seg_sim_size = 0
	764
	765	nb_tim = 0
	766	tim_channels = 0
	767	seg_tim_base = 0xFFFFFFFF
	768	seg_tim_size = 0
	769
	770	nb_tty = 0
	771	tty_channels = 0
	772	seg_tty_base = 0xFFFFFFFF
	773	seg_tty_size = 0
	774
	775	nb_xcu = 0
	776	xcu_channels = 0
	777	seg_xcu_base = 0xFFFFFFFF
	778	seg_xcu_size = 0
[520]	779	xcu_arg0 = 0
[319]	780
[491]	781	nb_drom = 0
	782	drom_channels = 0
	783	seg_drom_base = 0xFFFFFFFF
	784	seg_drom_size = 0
	785
[319]	786	use_bdv = False
	787	use_spi = False
	788	use_hba = False
	789
	790	# get peripherals attributes
	791	for cluster in self.clusters:
	792	for periph in cluster.periphs:
[406]	793	if ( periph.ptype == 'CMA' ):
[319]	794	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
	795	seg_cma_size = periph.pseg.size
	796	cma_channels = periph.channels
	797	nb_cma +=1
	798
[406]	799	elif ( periph.ptype == 'DMA' ):
	800	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
[319]	801	seg_dma_size = periph.pseg.size
	802	dma_channels = periph.channels
	803	nb_dma +=1
	804
[406]	805	elif ( periph.ptype == 'FBF' ):
[319]	806	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
	807	seg_fbf_size = periph.pseg.size
	808	fbf_channels = periph.channels
[520]	809	fbf_arg0 = periph.arg0
	810	fbf_arg1 = periph.arg1
[319]	811	nb_fbf +=1
	812
	813	elif ( periph.ptype == 'IOB' ):
	814	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
	815	seg_iob_size = periph.pseg.size
	816	iob_channels = periph.channels
	817	nb_iob +=1
	818
[406]	819	elif ( periph.ptype == 'IOC' ):
[319]	820	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
	821	seg_ioc_size = periph.pseg.size
	822	ioc_channels = periph.channels
	823	nb_ioc += 1
[404]	824
	825	if self.use_ramdisk: continue
	826
[319]	827	if ( periph.subtype == 'BDV' ): use_bdv = True
	828	elif ( periph.subtype == 'HBA' ): use_hba = True
	829	elif ( periph.subtype == 'SPI' ): use_spi = True
	830
	831	elif ( periph.ptype == 'MMC' ):
	832	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
	833	seg_mmc_size = periph.pseg.size
	834	mmc_channels = periph.channels
	835	nb_mmc +=1
	836
	837	elif ( periph.ptype == 'MWR' ):
	838	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
[520]	839	seg_mwr_size = periph.pseg.size
[319]	840	mwr_channels = periph.channels
[520]	841	mwr_arg0 = periph.arg0
	842	mwr_arg1 = periph.arg1
	843	mwr_arg2 = periph.arg2
	844	mwr_arg3 = periph.arg3
[319]	845	nb_mwr +=1
	846
	847	elif ( periph.ptype == 'ROM' ):
	848	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
	849	seg_rom_size = periph.pseg.size
	850	rom_channels = periph.channels
	851	nb_rom +=1
	852
[491]	853	elif ( periph.ptype == 'DROM' ):
	854	seg_drom_base = periph.pseg.base & 0xFFFFFFFF
	855	seg_drom_size = periph.pseg.size
	856	drom_channels = periph.channels
	857	nb_drom +=1
	858
[319]	859	elif ( periph.ptype == 'SIM' ):
	860	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
	861	seg_sim_size = periph.pseg.size
	862	sim_channels = periph.channels
	863	nb_sim +=1
	864
[406]	865	elif ( periph.ptype == 'NIC' ):
[319]	866	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
	867	seg_nic_size = periph.pseg.size
	868	nic_channels = periph.channels
	869	nb_nic +=1
	870
[406]	871	elif ( periph.ptype == 'PIC' ):
[319]	872	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
	873	seg_pic_size = periph.pseg.size
	874	pic_channels = periph.channels
	875	nb_pic +=1
[406]	876
	877	elif ( periph.ptype == 'TIM' ):
[319]	878	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
	879	seg_tim_size = periph.pseg.size
	880	tim_channels = periph.channels
	881	nb_tim +=1
[406]	882
[319]	883	elif ( periph.ptype == 'TTY' ):
	884	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
	885	seg_tty_size = periph.pseg.size
	886	tty_channels = periph.channels
	887	nb_tty +=1
[406]	888
	889	elif ( periph.ptype == 'XCU' ):
[319]	890	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
	891	seg_xcu_size = periph.pseg.size
	892	xcu_channels = periph.channels
[520]	893	xcu_arg0 = periph.arg0
[319]	894	nb_xcu +=1
[406]	895
[319]	896	# no more than two access to external peripherals
[406]	897	assert ( nb_fbf <= 2 )
	898	assert ( nb_cma <= 2 )
	899	assert ( nb_ioc <= 2 )
	900	assert ( nb_nic <= 2 )
	901	assert ( nb_tim <= 2 )
	902	assert ( nb_tty <= 2 )
[319]	903	assert ( nb_pic <= 2 )
	904
	905	# one and only one type of IOC controller
[403]	906	nb_iocs = 0
	907	if use_hba : nb_iocs += 1
	908	if use_bdv : nb_iocs += 1
	909	if use_spi : nb_iocs += 1
	910	if self.use_ramdisk: nb_iocs += 1
	911	assert ( nb_iocs == 1 )
[404]	912
[319]	913	# Compute total number of processors
	914	for cluster in self.clusters:
	915	nb_total_procs += len( cluster.procs )
	916
	917	# Compute physical addresses for BOOT vsegs
	918	boot_mapping_found = False
	919	boot_code_found = False
	920	boot_data_found = False
	921	boot_stack_found = False
	922
	923	for vseg in self.globs:
	924	if ( vseg.name == 'seg_boot_mapping' ):
[406]	925	boot_mapping_base = vseg.vbase
[512]	926	boot_mapping_size = vseg.length
[348]	927	boot_mapping_identity = vseg.identity
[319]	928	boot_mapping_found = True
	929
	930	if ( vseg.name == 'seg_boot_code' ):
[406]	931	boot_code_base = vseg.vbase
[512]	932	boot_code_size = vseg.length
[348]	933	boot_code_identity = vseg.identity
[319]	934	boot_code_found = True
	935
[406]	936	if ( vseg.name == 'seg_boot_data' ):
	937	boot_data_base = vseg.vbase
[512]	938	boot_data_size = vseg.length
[348]	939	boot_data_identity = vseg.identity
[319]	940	boot_data_found = True
	941
	942	if ( vseg.name == 'seg_boot_stack' ):
[406]	943	boot_stack_base = vseg.vbase
[512]	944	boot_stack_size = vseg.length
[348]	945	boot_stack_identity = vseg.identity
[319]	946	boot_stack_found = True
	947
[328]	948	# check that BOOT vsegs are found and identity mapping
[348]	949	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
[512]	950	print '[genmap error] in hard_config()'
	951	print ' seg_boot_mapping missing or not identity mapping'
[319]	952	sys.exit()
	953
[406]	954	if ( (boot_code_found == False) or (boot_code_identity == False) ):
[512]	955	print '[genmap error] in hard_config()'
	956	print ' seg_boot_code missing or not identity mapping'
[319]	957	sys.exit()
	958
[406]	959	if ( (boot_data_found == False) or (boot_data_identity == False) ):
[512]	960	print '[genmap error] in hard_config()'
	961	print ' seg_boot_data missing or not identity mapping'
[319]	962	sys.exit()
	963
[348]	964	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
[512]	965	print '[genmap error] in giet_vsegs()'
	966	print ' seg_boot_stask missing or not identity mapping'
[319]	967	sys.exit()
	968
	969	# Search RAMDISK global vseg if required
	970	seg_rdk_base = 0xFFFFFFFF
	971	seg_rdk_size = 0
	972	seg_rdk_found = False
	973
	974	if self.use_ramdisk:
	975	for vseg in self.globs:
[497]	976	if ( vseg.name == 'seg_ramdisk' ):
[319]	977	seg_rdk_base = vseg.vbase
[512]	978	seg_rdk_size = vseg.length
[319]	979	seg_rdk_found = True
	980
	981	if ( seg_rdk_found == False ):
	982	print 'Error in hard_config() "seg_ramdisk" not found'
	983	sys.exit(1)
	984
	985	# build string
[406]	986	s = '/* Generated by genmap for %s */\n' % self.name
[319]	987	s += '\n'
	988	s += '#ifndef HARD_CONFIG_H\n'
	989	s += '#define HARD_CONFIG_H\n'
	990	s += '\n'
	991
[406]	992	s += '/* General platform parameters */\n'
[319]	993	s += '\n'
	994	s += '#define X_SIZE %d\n' % self.x_size
	995	s += '#define Y_SIZE %d\n' % self.y_size
	996	s += '#define X_WIDTH %d\n' % self.x_width
	997	s += '#define Y_WIDTH %d\n' % self.y_width
[406]	998	s += '#define P_WIDTH %d\n' % self.p_width
[319]	999	s += '#define X_IO %d\n' % self.x_io
[406]	1000	s += '#define Y_IO %d\n' % self.y_io
[411]	1001	s += '#define NB_PROCS_MAX %d\n' % self.nprocs
[319]	1002	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
	1003	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
	1004	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
	1005	s += '\n'
	1006
[406]	1007	s += '/* Peripherals */\n'
[319]	1008	s += '\n'
	1009	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
	1010	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
	1011	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
	1012	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
	1013	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
	1014	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
	1015	s += '\n'
	1016	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
	1017	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
	1018	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
	1019	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
	1020	s += '\n'
	1021	s += '#define USE_IOC_BDV %d\n' % use_bdv
	1022	s += '#define USE_IOC_SPI %d\n' % use_spi
	1023	s += '#define USE_IOC_HBA %d\n' % use_hba
[403]	1024	s += '#define USE_IOC_RDK %d\n' % self.use_ramdisk
[319]	1025	s += '\n'
[520]	1026	s += '#define FBUF_X_SIZE %d\n' % fbf_arg0
	1027	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg1
[328]	1028	s += '\n'
[520]	1029	s += '#define XCU_NB_INPUTS %d\n' % xcu_arg0
[328]	1030	s += '\n'
[520]	1031	s += '#define MWR_TO_COPROC %d\n' % mwr_arg0
	1032	s += '#define MWR_FROM_COPROC %d\n' % mwr_arg1
	1033	s += '#define MWR_CONFIG %d\n' % mwr_arg2
	1034	s += '#define MWR_STATUS %d\n' % mwr_arg3
	1035	s += '\n'
[319]	1036
[356]	1037	s += '/* base addresses and sizes for physical segments */\n'
[319]	1038	s += '\n'
[406]	1039	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
	1040	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
[356]	1041	s += '\n'
[406]	1042	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
	1043	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
[319]	1044	s += '\n'
[406]	1045	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
	1046	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
[319]	1047	s += '\n'
[406]	1048	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
	1049	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
[319]	1050	s += '\n'
[406]	1051	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
	1052	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
[319]	1053	s += '\n'
[406]	1054	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
	1055	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
[319]	1056	s += '\n'
[406]	1057	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
	1058	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
[319]	1059	s += '\n'
[406]	1060	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
	1061	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
[319]	1062	s += '\n'
[406]	1063	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
	1064	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
[319]	1065	s += '\n'
[406]	1066	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
	1067	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
[319]	1068	s += '\n'
[406]	1069	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
	1070	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
[319]	1071	s += '\n'
[406]	1072	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
	1073	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
[319]	1074	s += '\n'
[406]	1075	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
	1076	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
[319]	1077	s += '\n'
[406]	1078	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
	1079	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
[319]	1080	s += '\n'
[406]	1081	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
	1082	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
[319]	1083	s += '\n'
	1084	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
	1085	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
	1086	s += '\n'
[491]	1087	s += '#define SEG_DROM_BASE 0x%x\n' % seg_drom_base
	1088	s += '#define SEG_DROM_SIZE 0x%x\n' % seg_drom_size
	1089	s += '\n'
[328]	1090	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
[319]	1091	s += '\n'
	1092
[326]	1093	s += '/* physical base addresses for identity mapped vsegs */\n'
	1094	s += '/* used by the GietVM OS */\n'
[319]	1095	s += '\n'
	1096	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
	1097	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
	1098	s += '\n'
	1099	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
	1100	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
	1101	s += '\n'
	1102	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
	1103	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
	1104	s += '\n'
	1105	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
	1106	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
	1107	s += '#endif\n'
[406]	1108
[319]	1109	return s
	1110
	1111	# end of hard_config()
	1112
[411]	1113	################################################################################
	1114	def linux_dts( self ): # compute string for linux.dts file generation
[424]	1115	# used for linux configuration
[411]	1116	# header
	1117	s = '/dts-v1/;\n'
	1118	s += '\n'
	1119	s += '/{\n'
[421]	1120	s += ' compatible = "tsar,%s";\n' % self.name
[411]	1121	s += ' #address-cells = <2>;\n' # physical address on 64 bits
	1122	s += ' #size-cells = <1>;\n' # segment size on 32 bits
	1123	s += ' model = "%s";\n' % self.name
	1124	s += '\n'
	1125
	1126	# linux globals arguments
	1127	s += ' chosen {\n'
	1128	s += ' linux,stdout-path = &tty;\n'
	1129	s += ' bootargs = "console=tty0 console=ttyVTTY0 earlyprintk";\n'
[424]	1130	s += ' };\n\n'
[411]	1131
	1132	# cpus (for each cluster)
	1133	s += ' cpus {\n'
	1134	s += ' #address-cells = <1>;\n'
	1135	s += ' #size-cells = <0>;\n'
	1136
	1137	for cluster in self.clusters:
	1138	for proc in cluster.procs:
	1139	x = cluster.x
	1140	y = cluster.y
	1141	l = proc.lpid
[421]	1142	proc_id = (((x << self.y_width) + y) << self.p_width) + l
[411]	1143	s += ' cpu@%d_%d_%d {\n' %(x,y,l)
	1144	s += ' device_type = "cpu";\n'
	1145	s += ' compatible = "soclib,mips32el";\n'
	1146	s += ' reg = <0x%x>;\n' % proc_id
	1147	s += ' };\n'
	1148	s += '\n'
	1149
	1150	s += ' };\n\n'
	1151
	1152	# devices (ram or peripheral) are grouped per cluster
[424]	1153	# the "compatible" attribute links a peripheral device
[411]	1154	# to one or several drivers identified by ("major","minor")
	1155
	1156	for cluster in self.clusters:
	1157	x = cluster.x
	1158	y = cluster.y
	1159	found_xcu = False
	1160	found_pic = False
	1161
	1162	s += ' /* cluster[%d,%d] */\n\n' % (x,y)
	1163
	1164	# scan all psegs to find RAM in current cluster
	1165	for pseg in cluster.psegs:
	1166	if ( pseg.segtype == 'RAM' ):
	1167	msb = pseg.base >> 32
	1168	lsb = pseg.base & 0xFFFFFFFF
	1169	size = pseg.size
	1170
[424]	1171	s += ' ram_%d_%d: ram@0x%x {\n' % (x, y, pseg.base)
[411]	1172	s += ' device_type = "memory";\n'
	1173	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1174	s += ' };\n\n'
	1175
	1176	# scan all periphs to find XCU or PIC in current cluster
	1177	for periph in cluster.periphs:
	1178	msb = periph.pseg.base >> 32
	1179	lsb = periph.pseg.base & 0xFFFFFFFF
	1180	size = periph.pseg.size
	1181
	1182	# search XCU (can be replicated)
[424]	1183	if ( (periph.ptype == 'XCU') ):
[411]	1184	found_xcu = True
	1185	xcu = periph
[424]	1186	irq_ctrl_name = 'xcu_%d_%d' % (x, y)
[411]	1187
[424]	1188	s += ' %s: xcu@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
[421]	1189	s += ' compatible = "soclib,vci_xicu","soclib,vci_xicu_timer";\n'
[411]	1190	s += ' interrupt-controller;\n'
	1191	s += ' #interrupt-cells = <1>;\n'
[512]	1192	s += ' clocks = <&freq>;\n' # XCU contains a timer
[424]	1193	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[411]	1194	s += ' };\n\n'
	1195
	1196	# search PIC (non replicated)
[424]	1197	if ( periph.ptype == 'PIC' ):
[411]	1198	found_pic = True
	1199	pic = periph
	1200	irq_ctrl_name = 'pic'
	1201
[424]	1202	s += ' %s: pic@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
[421]	1203	s += ' compatible = "soclib,vci_iopic";\n'
[411]	1204	s += ' interrupt-controller;\n'
	1205	s += ' #interrupt-cells = <1>;\n'
	1206	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1207	s += ' };\n\n'
	1208
	1209	# we need one interrupt controler in any cluster containing peripherals
[512]	1210	if ( (found_xcu == False) and
	1211	(found_pic == False) and
	1212	(len(cluster.periphs) > 0) ):
	1213	print '[genmap error] in linux_dts()'
	1214	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
[424]	1215	sys.exit(1)
[411]	1216
	1217	if ( found_pic == True ): irq_ctrl = pic
	1218	else: irq_ctrl = xcu
[424]	1219
[411]	1220	# scan all periphs to find TTY and IOC in current cluster
	1221	for periph in cluster.periphs:
	1222	msb = periph.pseg.base >> 32
	1223	lsb = periph.pseg.base & 0xFFFFFFFF
	1224	size = periph.pseg.size
	1225
	1226	# search TTY (non replicated)
[424]	1227	if ( periph.ptype == 'TTY' ):
[411]	1228
	1229	# get HWI index to XCU or PIC (only TTY channel 0 is used by Linux)
	1230	hwi_id = 0xFFFFFFFF
	1231	for irq in irq_ctrl.irqs:
[512]	1232	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == 0) ):
	1233	hwi_id = irq.srcid
	1234
[411]	1235	if ( hwi_id == 0xFFFFFFFF ):
[512]	1236	print '[genmap error] in linux.dts()'
	1237	print ' IRQ_TTY_RX not found'
[411]	1238	sys.exit(1)
	1239
[526]	1240	s += ' tty: tty@0x%x {\n' % (periph.pseg.base)
[421]	1241	s += ' compatible = "soclib,vci_multi_tty";\n'
[411]	1242	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
[424]	1243	s += ' interrupts = <%d>;\n' % hwi_id
[411]	1244	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1245	s += ' };\n\n'
	1246
	1247	# search IOC (non replicated)
[424]	1248	elif ( periph.ptype == 'IOC' ):
[411]	1249
	1250	if ( periph.subtype == 'BDV' ):
	1251
	1252	# get irq line index associated to bdv
	1253	hwi_id = 0xFFFFFFFF
	1254	for irq in irq_ctrl.irqs:
	1255	if ( irq.isrtype == 'ISR_BDV' ): hwi_id = irq.srcid
[512]	1256
[411]	1257	if ( hwi_id == 0xFFFFFFFF ):
[512]	1258	print '[genmap error] in linux.dts()'
	1259	print ' ISR_BDV not found'
[411]	1260	sys.exit(1)
	1261
[526]	1262	s += ' bdv: bdv@0x%x {\n' % (periph.pseg.base)
[517]	1263	s += ' compatible = "tsar,vci_block_device";\n'
[411]	1264	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
[424]	1265	s += ' interrupts = <%d>;\n' % hwi_id
[411]	1266	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1267	s += ' };\n\n'
	1268
[526]	1269	else:
	1270	print '[genmap warning] in linux_dts() : %s' % (periph.subtype),
	1271	print 'peripheral not supported by LINUX'
[411]	1272
[465]	1273	# XCU or PIC have been already parsed
	1274	elif ( periph.ptype == 'XCU' ) or ( periph.ptype == 'PIC' ):
	1275	pass
	1276
[411]	1277	# other peripherals
[424]	1278	else:
[512]	1279	print '[genmap warning] in linux_dts()'
	1280	print ' %s peripheral not supported by LINUX' % (periph.ptype)
[424]	1281
	1282	# clocks
[411]	1283	s += ' /* clocks */\n\n'
	1284	s += ' clocks {\n'
[424]	1285	s += ' freq: freq@50MHZ {\n'
[411]	1286	s += ' #clock-cells = <0>;\n'
	1287	s += ' compatible = "fixed-clock";\n'
	1288	s += ' clock-frequency = <50000000>;\n'
	1289	s += ' };\n'
	1290	s += ' };\n\n'
	1291	s += ' cpuclk {\n'
[421]	1292	s += ' compatible = "soclib,mips32_clksrc";\n'
[424]	1293	s += ' clocks = <&freq>;\n'
[411]	1294	s += ' };\n'
	1295	s += '};\n'
	1296
	1297	return s
	1298	# end linux_dts()
	1299
	1300
	1301	#############################################################################
[319]	1302	def netbsd_dts( self ): # compute string for netbsd.dts file generation,
[406]	1303	# used for netbsd configuration
[319]	1304	# header
	1305	s = '/dts-v1/;\n'
	1306	s += '\n'
	1307	s += '/{\n'
[406]	1308	s += ' #address-cells = <2>;\n'
	1309	s += ' #size-cells = <1>;\n'
[319]	1310
	1311	# cpus (for each cluster)
	1312	s += ' cpus {\n'
	1313	s += ' #address-cells = <1>;\n'
	1314	s += ' #size-cells = <0>;\n'
	1315
	1316	for cluster in self.clusters:
	1317	for proc in cluster.procs:
[406]	1318	proc_id = (((cluster.x << self.y_width) + cluster.y) << self.p_width) + proc.lpid
[319]	1319
	1320	s += ' Mips,32@0x%x {\n' % proc_id
	1321	s += ' device_type = "cpu";\n'
	1322	s += ' icudev_type = "cpu:mips";\n'
	1323	s += ' name = "Mips,32";\n'
	1324	s += ' reg = <0x%x>;\n' % proc_id
	1325	s += ' };\n'
	1326	s += '\n'
	1327
	1328	s += ' };\n'
	1329
[411]	1330	# physical memory banks (for each cluster)
[319]	1331	for cluster in self.clusters:
	1332	for pseg in cluster.psegs:
	1333
	1334	if ( pseg.segtype == 'RAM' ):
	1335	msb = pseg.base >> 32
	1336	lsb = pseg.base & 0xFFFFFFFF
	1337	size = pseg.size
	1338
	1339	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
	1340	s += ' cached = <1>;\n'
	1341	s += ' device_type = "memory";\n'
	1342	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1343	s += ' };\n'
	1344
	1345	# peripherals (for each cluster)
	1346	for cluster in self.clusters:
[411]	1347	x = cluster.x
	1348	y = cluster.y
[319]	1349
[406]	1350	# research XCU component
[319]	1351	found_xcu = False
	1352	for periph in cluster.periphs:
[406]	1353	if ( (periph.ptype == 'XCU') ):
[319]	1354	found_xcu = True
	1355	xcu = periph
	1356	msb = periph.pseg.base >> 32
	1357	lsb = periph.pseg.base & 0xFFFFFFFF
	1358	size = periph.pseg.size
	1359
	1360	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1361	s += ' device_type = "soclib:xicu:root";\n'
	1362	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[400]	1363	s += ' input_lines = <%d>;\n' % periph.arg
	1364	s += ' ipis = <%d>;\n' % periph.arg
	1365	s += ' timers = <%d>;\n' % periph.arg
[319]	1366
	1367	output_id = 0 # output index from XCU
	1368	for lpid in xrange ( len(cluster.procs) ): # destination processor index
	1369	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
[406]	1370	cluster_xy = (cluster.x << self.y_width) + cluster.y
	1371	proc_id = (cluster_xy << self.p_width) + lpid
[319]	1372	s += ' out@%d {\n' % output_id
	1373	s += ' device_type = "soclib:xicu:filter";\n'
[411]	1374	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
[406]	1375	s += ' output_line = <%d>;\n' % output_id
[411]	1376	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
[319]	1377	s += ' };\n'
	1378
	1379	output_id += 1
	1380
	1381	s += ' };\n'
	1382
	1383	# research PIC component
	1384	found_pic = False
	1385	for periph in cluster.periphs:
[406]	1386	if ( periph.ptype == 'PIC' ):
[319]	1387	found_pic = True
	1388	pic = periph
	1389	msb = periph.pseg.base >> 32
	1390	lsb = periph.pseg.base & 0xFFFFFFFF
	1391	size = periph.pseg.size
	1392
	1393	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1394	s += ' device_type = "soclib:pic:root";\n'
	1395	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[406]	1396	s += ' input_lines = <%d>;\n' % periph.channels
[319]	1397	s += ' };\n'
	1398
[411]	1399	# at least one interrupt controller
[319]	1400	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
[512]	1401	print '[genmap error] in netbsd_dts()'
	1402	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
[406]	1403	sys.exit(1)
	1404
[319]	1405	if ( found_pic == True ): irq_tgt = pic
	1406	else: irq_tgt = xcu
[406]	1407
[319]	1408	# get all others peripherals in cluster
	1409	for periph in cluster.periphs:
	1410	msb = periph.pseg.base >> 32
	1411	lsb = periph.pseg.base & 0xFFFFFFFF
	1412	size = periph.pseg.size
	1413
	1414	# research DMA component
	1415	if ( periph.ptype == 'DMA' ):
	1416
	1417	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
[411]	1418	s += ' device_type = "soclib:dma";\n'
	1419	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1420	s += ' channel_count = <%d>;\n' % periph.channels
	1421
	1422	# multi-channels : get HWI index (to XCU) for each channel
	1423	for channel in xrange( periph.channels ):
	1424	hwi_id = 0xFFFFFFFF
	1425	for irq in xcu.irqs:
[406]	1426	if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ):
[319]	1427	hwi_id = irq.srcid
[512]	1428
[319]	1429	if ( hwi_id == 0xFFFFFFFF ):
[512]	1430	print '[genmap error] in netbsd.dts()'
	1431	print ' ISR_DMA channel %d not found' % channel
[319]	1432	sys.exit(1)
	1433
	1434	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
	1435	s += ' irq@%d{\n' % channel
	1436	s += ' device_type = "soclib:periph:irq";\n'
	1437	s += ' output_line = <%d>;\n' % channel
[411]	1438	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1439	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
[319]	1440	s += ' };\n'
	1441
[406]	1442	s += ' };\n'
[319]	1443
	1444	# research MMC component
	1445	elif ( periph.ptype == 'MMC' ):
	1446
	1447	# get irq line index associated to MMC in XCU
	1448	irq_in = 0xFFFFFFFF
	1449	for irq in xcu.irqs:
	1450	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
[512]	1451
[319]	1452	if ( irq_in == 0xFFFFFFFF ):
[512]	1453	print '[genmap error] in netbsd.dts()'
	1454	print ' ISR_MMC not found'
[319]	1455	sys.exit(1)
	1456
	1457	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1458	s += ' device_type = "soclib:mmc";\n'
[411]	1459	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1460	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[406]	1461	s += ' };\n'
[319]	1462
	1463	# research FBF component
[406]	1464	elif ( periph.ptype == 'FBF' ):
[319]	1465
[411]	1466	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
[319]	1467	s += ' device_type = "soclib:framebuffer";\n'
	1468	s += ' mode = <32>;\n' # bits par pixel
[400]	1469	s += ' width = <%d>;\n' % periph.arg
	1470	s += ' height = <%d>;\n' % periph.arg
[319]	1471	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1472	s += ' };\n'
	1473
	1474	# research IOC component
[406]	1475	elif ( periph.ptype == 'IOC' ):
[319]	1476
	1477	if ( periph.subtype == 'BDV' ):
	1478
	1479	# get irq line index associated to bdv
	1480	irq_in = 0xFFFFFFFF
	1481	for irq in irq_tgt.irqs:
	1482	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
	1483	if ( irq_in == 0xFFFFFFFF ):
[512]	1484	print '[genmap error] in netbsd.dts()'
	1485	print ' ISR_BDV not found'
[319]	1486	sys.exit(1)
	1487
[411]	1488	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
[319]	1489	s += ' device_type = "soclib:blockdevice";\n'
[411]	1490	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
	1491	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1492	s += ' };\n'
	1493
	1494	elif ( periph.subtype == 'HBA' ):
[512]	1495	print '[genmap error] in netbsd_dts()'
	1496	print ' HBA peripheral not supported by NetBSD'
[319]	1497	sys.exit(1)
	1498
	1499	elif ( periph.subtype == 'SPI' ):
	1500
	1501	# get irq line index associated to spi
	1502	irq_in = 0xFFFFFFFF
	1503	for irq in irq_tgt.irqs:
	1504	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
	1505	if ( irq_in == 0xFFFFFFFF ):
[512]	1506	print '[genmap error] in netbsd.dts()'
	1507	print ' ISR_SPI not found'
[319]	1508	sys.exit(1)
	1509
	1510	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1511	s += ' device_type = "soclib:spi";\n'
[411]	1512	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
	1513	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1514	s += ' };\n'
	1515
	1516	# research ROM component
	1517	elif ( periph.ptype == 'ROM' ):
	1518
[411]	1519	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
[319]	1520	s += ' device_type = "rom";\n'
[411]	1521	s += ' cached = <1>;\n'
	1522	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1523	s += ' };\n'
	1524
	1525	# research SIM component
	1526	elif ( periph.ptype == 'SIM' ):
	1527
	1528	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1529	s += ' device_type = "soclib:simhelper";\n'
	1530	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1531	s += ' };\n'
	1532
	1533	# research TTY component
	1534	elif ( periph.ptype == 'TTY' ):
	1535
[411]	1536	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1537	s += ' device_type = "soclib:tty";\n'
[406]	1538	s += ' channel_count = < %d >;\n' % periph.channels
[411]	1539	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1540
	1541	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1542	for channel in xrange( periph.channels ):
	1543	hwi_id = 0xFFFFFFFF
	1544	for irq in irq_tgt.irqs:
[406]	1545	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
[319]	1546	hwi_id = irq.srcid
	1547	if ( hwi_id == 0xFFFFFFFF ):
[512]	1548	print '[genmap error] in netbsd.dts()'
	1549	print ' ISR_TTY_RX channel %d not found' % channel
[319]	1550	sys.exit(1)
	1551
	1552	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1553	s += ' irq@%d{\n' % channel
	1554	s += ' device_type = "soclib:periph:irq";\n'
	1555	s += ' output_line = <%d>;\n' % channel
[411]	1556	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1557	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
[319]	1558	s += ' };\n'
	1559
	1560	s += ' };\n'
[406]	1561
[319]	1562	# research IOB component
	1563	elif ( periph.ptype == 'IOB' ):
	1564
	1565	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1566	s += ' device_type = "soclib:iob";\n'
	1567	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1568	s += ' };\n'
	1569
	1570	# research NIC component
[406]	1571	elif ( periph.ptype == 'NIC' ):
[319]	1572
	1573	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1574	s += ' device_type = "soclib:nic";\n'
	1575	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1576	s += ' channel_count = < %d >;\n' % periph.channels
	1577
	1578	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
	1579	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
	1580	for channel in xrange( periph.channels ):
	1581	hwi_id = 0xFFFFFFFF
	1582	for irq in irq_tgt.irqs:
[406]	1583	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
[319]	1584	hwi_id = irq.srcid
	1585	if ( hwi_id == 0xFFFFFFFF ):
[512]	1586	print '[genmap error] in netbsd.dts()'
	1587	print ' ISR_NIC_RX channel %d not found' % channel
[319]	1588	sys.exit(1)
	1589
	1590	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1591	s += ' irq_rx@%d{\n' % channel
	1592	s += ' device_type = "soclib:periph:irq";\n'
	1593	s += ' output_line = <%d>;\n' % (2*channel)
	1594	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1595	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1596	s += ' };\n'
	1597
	1598	hwi_id = 0xFFFFFFFF
	1599	for irq in irq_tgt.irqs:
[406]	1600	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
[319]	1601	hwi_id = irq.srcid
	1602	if ( hwi_id == 0xFFFFFFFF ):
[512]	1603	print '[genmap error] in netbsd.dts()'
	1604	print ' ISR_NIC_TX channel %d not found' % channel
[319]	1605	sys.exit(1)
	1606
	1607	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1608	s += ' irq_tx@%d{\n' % channel
	1609	s += ' device_type = "soclib:periph:irq";\n'
	1610	s += ' output_line = <%d>;\n' % (2*channel + 1)
	1611	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1612	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1613	s += ' };\n'
[406]	1614
[319]	1615	s += ' };\n'
	1616
	1617	# research CMA component
[406]	1618	elif ( periph.ptype == 'CMA' ):
[319]	1619
	1620	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1621	s += ' device_type = "soclib:cma";\n'
	1622	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1623	s += ' channel_count = < %d >;\n' % periph.channels
	1624
	1625	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1626	for channel in xrange( periph.channels ):
	1627	hwi_id = 0xFFFFFFFF
	1628	for irq in irq_tgt.irqs:
[406]	1629	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
[319]	1630	hwi_id = irq.srcid
[512]	1631
[319]	1632	if ( hwi_id == 0xFFFFFFFF ):
[512]	1633	print '[genmap error] in netbsd.dts()'
	1634	print ' ISR_CMA channel %d not found' % channel
[319]	1635	sys.exit(1)
	1636
	1637	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1638	s += ' irq@%d{\n' % channel
	1639	s += ' device_type = "soclib:periph:irq";\n'
	1640	s += ' output_line = <%d>;\n' % channel
[411]	1641	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1642	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
[319]	1643	s += ' };\n'
	1644
	1645	s += ' };\n'
	1646
	1647	# research TIM component
[406]	1648	elif ( periph.ptype == 'TIM' ):
[319]	1649
[512]	1650	print '[genmap error] in netbsd_dts()'
	1651	print ' TIM peripheral not supported by NetBSD'
[319]	1652	sys.exit(1)
	1653
	1654	# research MWR component
	1655	elif ( periph.ptype == 'MWR' ):
	1656
[512]	1657	print '[genmap error] in netbsd_dts()'
	1658	print ' MWR peripheral not supported by NetBSD'
[319]	1659	sys.exit(1)
	1660
	1661	# topology
	1662	s += '\n'
	1663	s += ' topology {\n'
	1664	s += ' #address-cells = <2>;\n'
	1665	s += ' #size-cells = <0>;\n'
	1666	for cluster in self.clusters:
[406]	1667	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
[319]	1668	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
	1669	s += ' devices = <\n'
	1670
[406]	1671	offset = ((cluster.x << self.y_width) + cluster.y) << self.p_width
[319]	1672	for proc in cluster.procs:
	1673	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
	1674	for periph in cluster.periphs:
	1675	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
[492]	1676	for pseg in cluster.psegs:
	1677	if ( pseg.segtype == 'RAM' ):
	1678	s += ' &{/%s@0x%x}\n' % (pseg.name, pseg.base)
[319]	1679
	1680	s += ' >;\n'
	1681	s += ' };\n'
	1682	s += ' };\n'
	1683	s += '};\n'
	1684
	1685	return s
[411]	1686	# end netbsd_dts()
[319]	1687
	1688	###########################
	1689	def almos_archinfo( self ): # compute string for arch.info file generation,
[406]	1690	# used for almos configuration
[319]	1691	# header
[327]	1692	s = '# arch.info file generated by genmap for %s\n' % self.name
[319]	1693	s += '\n'
	1694	s += '[HEADER]\n'
	1695	s += ' REVISION=1\n'
	1696	s += ' ARCH=%s\n' % self.name
	1697	s += ' XMAX=%d\n' % self.x_size
	1698	s += ' YMAX=%d\n' % self.y_size
[411]	1699	s += ' CPU_NR=%d\n' % self.nprocs
[319]	1700	s += '\n'
	1701
	1702	# clusters
	1703	cluster_id = 0
	1704	for cluster in self.clusters:
	1705
	1706	ram = None
	1707	nb_cpus = len( cluster.procs )
	1708	nb_devs = len( cluster.periphs )
	1709
	1710	# search a RAM
	1711	for pseg in cluster.psegs:
[406]	1712	if ( pseg.segtype == 'RAM' ):
[319]	1713	ram = pseg
	1714	nb_devs += 1
	1715
	1716	# search XCU to get IRQs indexes if cluster contains peripherals
	1717	if ( len( cluster.periphs ) != 0 ):
	1718	tty_irq_id = None
	1719	bdv_irq_id = None
	1720	dma_irq_id = None
	1721
	1722	for periph in cluster.periphs:
[406]	1723	if ( periph.ptype == 'XCU' ):
[319]	1724	# scan irqs
	1725	for irq in periph.irqs:
	1726	if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid
	1727	if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid
	1728	if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid
	1729
	1730	# Build the cluster description
	1731	s += '[CLUSTER]\n'
[406]	1732	s += ' CID=%d\n' % cluster_id
	1733	s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y)
[319]	1734	s += ' CPU_NR=%d\n' % nb_cpus
	1735	s += ' DEV_NR=%d\n' % nb_devs
	1736
[406]	1737
[319]	1738	# Handling RAM when cluster contain a RAM
	1739	if (ram != None ):
	1740	base = ram.base
	1741	size = ram.size
	1742	irqid = -1
[406]	1743	s += ' DEVID=RAM'
[319]	1744	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1745
	1746	# Handling peripherals
	1747	for periph in cluster.periphs:
	1748	base = periph.pseg.base
	1749	size = periph.pseg.size
	1750
[406]	1751	if ( periph.ptype == 'XCU' ):
[319]	1752
[406]	1753	s += ' DEVID=XICU'
[319]	1754	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1755
[406]	1756	elif ( (periph.ptype == 'TTY')
[319]	1757	and (tty_irq_id != None) ):
	1758
[406]	1759	s += ' DEVID=TTY'
[319]	1760	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id )
	1761
[406]	1762	elif ( (periph.ptype == 'DMA')
[319]	1763	and (dma_irq_id != None) ):
	1764
	1765	s += ' DEVID=DMA'
	1766	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id )
	1767
	1768	elif ( periph.ptype == 'FBF' ):
	1769
	1770	s += ' DEVID=FB'
	1771	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1772
	1773	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
	1774	and (bdv_irq_id != None) ):
	1775
[406]	1776	s += ' DEVID=BLKDEV'
[319]	1777	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id )
	1778
	1779	elif ( periph.ptype == 'PIC' ):
	1780
[406]	1781	s += ' DEVID=IOPIC'
[319]	1782	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1783
	1784	else:
	1785	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
	1786	% (cluster.x, cluster.y)
	1787	print '# peripheral type %s/%s not supported yet\n' \
	1788	% ( periph.ptype, periph.subtype )
[406]	1789
[319]	1790	cluster_id += 1
	1791
	1792	return s
	1793
	1794	# end of almos_archinfo()
	1795
	1796
	1797
	1798
	1799
	1800
	1801
	1802
	1803	###########################################################################################
	1804	class Cluster ( object ):
	1805	###########################################################################################
	1806	def __init__( self,
[406]	1807	x,
[319]	1808	y ):
[406]	1809
[319]	1810	self.index = 0 # global index (set by Mapping constructor)
	1811	self.x = x # x coordinate
	1812	self.y = y # y coordinate
	1813	self.psegs = [] # filled by addRam() or addPeriph()
	1814	self.procs = [] # filled by addProc()
	1815	self.periphs = [] # filled by addPeriph()
	1816
	1817	return
	1818
	1819	################
	1820	def xml( self ): # xml for a cluster
	1821
	1822	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
[406]	1823	for pseg in self.psegs: s += pseg.xml()
[319]	1824	for proc in self.procs: s += proc.xml()
[406]	1825	for peri in self.periphs: s += peri.xml()
[319]	1826	s += ' </cluster>\n'
	1827
	1828	return s
	1829
	1830	#############################################
	1831	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
	1832
	1833	if ( verbose ):
	1834	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
	1835
	1836	# check index
	1837	if (self.index != expected):
[512]	1838	print '[genmap error] in Cluster.cbin()'
	1839	print ' cluster global index = %d / expected = %d' % (self.index,expected)
[319]	1840	sys.exit(1)
	1841
[406]	1842	# compute global index for first pseg
[319]	1843	if ( len(self.psegs) > 0 ):
	1844	pseg_id = self.psegs[0].index
	1845	else:
	1846	pseg_id = 0
	1847
[406]	1848	# compute global index for first proc
[319]	1849	if ( len(self.procs) > 0 ):
	1850	proc_id = self.procs[0].index
	1851	else:
	1852	proc_id = 0
	1853
[406]	1854	# compute global index for first periph
[319]	1855	if ( len(self.periphs) > 0 ):
	1856	periph_id = self.periphs[0].index
	1857	else:
	1858	periph_id = 0
	1859
	1860	byte_stream = bytearray()
[512]	1861	byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate
	1862	byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate
	1863	byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number psegs in cluster
	1864	byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index
	1865	byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number procs in cluster
	1866	byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index
	1867	byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number periphs in cluster
	1868	byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index
[406]	1869
[319]	1870	if ( verbose ):
	1871	print 'nb_psegs = %d' % len( self.psegs )
	1872	print 'pseg_id = %d' % pseg_id
	1873	print 'nb_procs = %d' % len( self.procs )
	1874	print 'proc_id = %d' % proc_id
	1875	print 'nb_periphs = %d' % len( self.periphs )
	1876	print 'periph_id = %d' % periph_id
	1877
	1878	return byte_stream
	1879
[512]	1880	########################################################################################
[305]	1881	class Vspace( object ):
[512]	1882	########################################################################################
[406]	1883	def __init__( self,
	1884	name,
[319]	1885	startname ):
	1886
	1887	self.index = 0 # global index ( set by addVspace() )
	1888	self.name = name # vspace name
[512]	1889	self.startname = startname # name of vseg containing the start_vector
[406]	1890	self.vsegs = []
[305]	1891	self.tasks = []
	1892
	1893	return
	1894
[319]	1895	################
	1896	def xml( self ): # xml for one vspace
	1897
[305]	1898	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
[319]	1899	for vseg in self.vsegs: s += vseg.xml()
[406]	1900	for task in self.tasks: s += task.xml()
[305]	1901	s += ' </vspace>\n'
[319]	1902
[305]	1903	return s
	1904
[319]	1905	#############################################
	1906	def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace
	1907
	1908	if ( verbose ):
	1909	print '*** cbin for vspace %s' % (self.name)
	1910
	1911	# check index
	1912	if (self.index != expected):
[512]	1913	print '[genmap error] in Vspace.cbin()'
	1914	print ' vspace global index = %d / expected = %d' %(self.index,expected)
[319]	1915	sys.exit(1)
	1916
[512]	1917	# compute global index for vseg containing start_vector
	1918	vseg_start_id = 0xFFFFFFFF
[319]	1919	for vseg in self.vsegs:
[512]	1920	if ( vseg.name == self.startname ): vseg_start_id = vseg.index
	1921
	1922	if ( vseg_start_id == 0xFFFFFFFF ):
	1923	print '[genmap error] in Vspace.cbin()'
	1924	print ' startname %s not found for vspace %s' %(self.startname,self.name)
[319]	1925	sys.exit(1)
[406]	1926
[512]	1927	# compute first vseg and first task global index
[319]	1928	first_vseg_id = self.vsegs[0].index
	1929	first_task_id = self.tasks[0].index
[406]	1930
[512]	1931	# compute number of tasks and number of vsegs
[319]	1932	nb_vsegs = len( self.vsegs )
	1933	nb_tasks = len( self.tasks )
	1934
	1935	byte_stream = bytearray()
	1936	byte_stream += mapping.str2bytes( 32, self.name ) # vspace name
[512]	1937	byte_stream += mapping.int2bytes( 4, vseg_start_id ) # vseg start_vector
[319]	1938	byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs
	1939	byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks
	1940	byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index
	1941	byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index
	1942
	1943	if ( verbose ):
[512]	1944	print 'start_id = %d' % vseg_start_id
[319]	1945	print 'nb_vsegs = %d' % nb_vsegs
	1946	print 'nb_tasks = %d' % nb_tasks
	1947	print 'vseg_id = %d' % first_vseg_id
	1948	print 'task_id = %d' % first_task_id
	1949
	1950	return byte_stream
	1951
[512]	1952	########################################################################################
[305]	1953	class Task( object ):
[512]	1954	########################################################################################
[406]	1955	def __init__( self,
	1956	name,
	1957	trdid,
	1958	x,
[319]	1959	y,
[406]	1960	p,
	1961	stackname,
	1962	heapname,
[441]	1963	startid ):
[319]	1964
	1965	self.index = 0 # global index value set by addTask()
	1966	self.name = name # tsk name
	1967	self.trdid = trdid # task index (unique in vspace)
[406]	1968	self.x = x # cluster x coordinate
	1969	self.y = y # cluster y coordinate
	1970	self.p = p # processor local index
[512]	1971	self.stackname = stackname # name of vseg containing the stack
	1972	self.heapname = heapname # name of vseg containing the heap
[319]	1973	self.startid = startid # index in start_vector
[305]	1974	return
	1975
[319]	1976	################
	1977	def xml( self ): # xml for one task
	1978
	1979	s = ' <task name="%s"' % self.name
	1980	s += ' trdid="%d"' % self.trdid
	1981	s += ' x="%d"' % self.x
	1982	s += ' y="%d"' % self.y
	1983	s += ' p="%d"' % self.p
[512]	1984	s += '\n '
[319]	1985	s += ' stackname="%s"' % self.stackname
	1986	s += ' heapname="%s"' % self.heapname
	1987	s += ' startid="%d"' % self.startid
[406]	1988	s += ' />\n'
[319]	1989
[305]	1990	return s
	1991
[319]	1992	#####################################################
[406]	1993	def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task
[319]	1994
	1995	if ( verbose ):
	1996	print '*** cbin for task %s in vspace %s' % (self.name, vspace.name)
	1997
	1998	# check index
	1999	if (self.index != expected):
[512]	2000	print '[genmap error] in Task.cbin()'
	2001	print ' task global index = %d / expected = %d' %(self.index,expected)
[319]	2002	sys.exit(1)
	2003
	2004	# compute cluster global index
	2005	cluster_id = (self.x * mapping.y_size) + self.y
	2006
[512]	2007	# compute vseg index for stack
	2008	vseg_stack_id = 0xFFFFFFFF
[319]	2009	for vseg in vspace.vsegs:
[512]	2010	if ( vseg.name == self.stackname ): vseg_stack_id = vseg.index
	2011
	2012	if ( vseg_stack_id == 0xFFFFFFFF ):
	2013	print '[genmap error] in Task.cbin()'
	2014	print ' stackname %s not found for task %s in vspace %s' \
[319]	2015	% ( self.stackname, self.name, vspace.name )
	2016	sys.exit(1)
	2017
[512]	2018	# compute vseg index for heap
[453]	2019	if ( self.heapname == '' ):
[512]	2020	vseg_heap_id = 0
[453]	2021	else:
[512]	2022	vseg_heap_id = 0xFFFFFFFF
[453]	2023	for vseg in vspace.vsegs:
[512]	2024	if ( vseg.name == self.heapname ): vseg_heap_id = vseg.index
	2025
	2026	if ( vseg_heap_id == 0xFFFFFFFF ):
	2027	print '[genmap error] in Task.cbin()'
	2028	print ' heapname %s not found for task %s in vspace %s' \
[453]	2029	% ( self.heapname, self.name, vspace.name )
	2030	sys.exit(1)
[319]	2031
	2032	byte_stream = bytearray()
	2033	byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace
	2034	byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index
[512]	2035	byte_stream += mapping.int2bytes( 4, self.p ) # processor local index
[319]	2036	byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace
[512]	2037	byte_stream += mapping.int2bytes( 4, vseg_stack_id ) # stack vseg local index
	2038	byte_stream += mapping.int2bytes( 4, vseg_heap_id ) # heap vseg local index
[406]	2039	byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector
[319]	2040
	2041	if ( verbose ):
	2042	print 'clusterid = %d' % cluster_id
	2043	print 'lpid = %d' % self.p
[406]	2044	print 'trdid = %d' % self.trdid
[512]	2045	print 'stackid = %d' % vseg_stack_id
	2046	print 'heapid = %d' % vseg_heap_id
[406]	2047	print 'startid = %d' % self.startid
	2048
[319]	2049	return byte_stream
	2050
[512]	2051	########################################################################################
[305]	2052	class Vseg( object ):
[512]	2053	########################################################################################
[406]	2054	def __init__( self,
	2055	name,
	2056	vbase,
[512]	2057	length,
[406]	2058	mode,
[512]	2059	vtype,
[406]	2060	x,
	2061	y,
[512]	2062	pseg,
[348]	2063	identity = False,
[411]	2064	local = False,
[512]	2065	big = False,
	2066	binpath = '' ):
[305]	2067
[512]	2068	assert (vbase & 0xFFFFFFFF) == vbase
	2069
	2070	assert (length & 0xFFFFFFFF) == length
	2071
[319]	2072	assert mode in VSEGMODES
	2073
[512]	2074	assert vtype in VSEGTYPES
	2075
	2076	assert (vtype != 'ELF') or (binpath != '')
	2077
[348]	2078	self.index = 0 # global index ( set by addVseg() )
[512]	2079	self.name = name # vseg name (unique in vspace)
	2080	self.vbase = vbase # virtual base address in vspace
	2081	self.length = length # vseg length (bytes)
	2082	self.vtype = vtype # vseg type (defined in VSEGTYPES)
[348]	2083	self.mode = mode # CXWU access rights
[406]	2084	self.x = x # x coordinate of destination cluster
[348]	2085	self.y = y # y coordinate of destination cluster
[512]	2086	self.psegname = pseg # name of pseg in destination cluster
[348]	2087	self.identity = identity # identity mapping required
[411]	2088	self.local = local # only mapped in local PTAB when true
	2089	self.big = big # to be mapped in a big physical page
[512]	2090	self.binpath = binpath # path name for binary file (ELF or BLOB)
	2091
[305]	2092	return
	2093
[319]	2094	################
[406]	2095	def xml( self ): # xml for one vseg
[319]	2096
[512]	2097	s = ' <vseg name="%s"' %(self.name)
	2098	s += ' vbase="0x%x"' %(self.vbase)
	2099	s += ' length="0x%x"' %(self.length)
	2100	s += ' type="%s"' %(self.vtype)
	2101	s += ' mode="%s"' %(self.mode)
	2102	s += '\n '
	2103	s += ' x="%d"' %(self.x)
	2104	s += ' y="%d"' %(self.y)
	2105	s += ' psegname="%s"' %(self.psegname)
	2106	if ( self.identity ): s += ' ident="1"'
	2107	if ( self.local ): s += ' local="1"'
	2108	if ( self.big ): s += ' big="1"'
	2109	if ( self.binpath != '' ): s += ' binpath="%s"' %(self.binpath)
	2110	s += ' />\n'
[319]	2111
[305]	2112	return s
	2113
[319]	2114	#############################################
	2115	def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg
	2116
	2117	if ( verbose ):
	2118	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
	2119
	2120	# check index
	2121	if (self.index != expected):
[512]	2122	print '[genmap error] in Vseg.cbin()'
	2123	print ' vseg global index = %d / expected = %d' \
[319]	2124	% (self.index, expected )
	2125	sys.exit(1)
	2126
	2127	# compute pseg_id
	2128	pseg_id = 0xFFFFFFFF
	2129	cluster_id = (self.x * mapping.y_size) + self.y
	2130	cluster = mapping.clusters[cluster_id]
	2131	for pseg in cluster.psegs:
	2132	if (self.psegname == pseg.name):
	2133	pseg_id = pseg.index
	2134	if (pseg_id == 0xFFFFFFFF):
[512]	2135	print '[genmap error] in Vseg.cbin() : '
	2136	print ' psegname %s not found for vseg %s in cluster %d' \
[319]	2137	% ( self.psegname, self.name, cluster_id )
	2138	sys.exit(1)
	2139
	2140	# compute numerical value for mode
	2141	mode_id = 0xFFFFFFFF
[406]	2142	for x in xrange( len(VSEGMODES) ):
	2143	if ( self.mode == VSEGMODES[x] ):
[319]	2144	mode_id = x
	2145	if ( mode_id == 0xFFFFFFFF ):
[512]	2146	print '[genmap error] in Vseg.cbin() : '
	2147	print ' undefined vseg mode %s' % self.mode
[319]	2148	sys.exit(1)
	2149
[512]	2150	# compute numerical value for vtype
	2151	vtype_id = 0xFFFFFFFF
	2152	for x in xrange( len(VSEGTYPES) ):
	2153	if ( self.vtype == VSEGTYPES[x] ):
	2154	vtype_id = x
	2155	if ( vtype_id == 0xFFFFFFFF ):
	2156	print '[genmap error] in Vseg.cbin()'
	2157	print ' undefined vseg type %s' % self.vtype
	2158	sys.exit(1)
[319]	2159
	2160	byte_stream = bytearray()
[406]	2161	byte_stream += mapping.str2bytes( 32, self.name ) # vseg name
[512]	2162	byte_stream += mapping.str2bytes( 64, self.binpath ) # binpath
[319]	2163	byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address
	2164	byte_stream += mapping.int2bytes( 8, 0 ) # physical base address
[512]	2165	byte_stream += mapping.int2bytes( 4, self.length ) # vseg size (bytes)
	2166	byte_stream += mapping.int2bytes( 4, pseg_id ) # pseg global index
[319]	2167	byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags
[512]	2168	byte_stream += mapping.int2bytes( 4, vtype_id ) # vseg type
[319]	2169	byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero
[512]	2170	byte_stream += mapping.int2bytes( 1, self.identity ) # identity mapping
[411]	2171	byte_stream += mapping.int2bytes( 1, self.local ) # only mapped in local PTAB
[512]	2172	byte_stream += mapping.int2bytes( 1, self.big ) # to be mapped in BPP
[319]	2173
	2174	if ( verbose ):
[512]	2175	print 'binpath = %s' % self.binpath
[319]	2176	print 'vbase = %x' % self.vbase
[512]	2177	print 'pbase = 0'
	2178	print 'length = %x' % self.length
[319]	2179	print 'pseg_id = %d' % pseg_id
[512]	2180	print 'mode = %d' % mode_id
	2181	print 'type = %d' % vtype_id
	2182	print 'mapped = 0'
	2183	print 'ident = %d' % self.identity
	2184	print 'local = %d' % self.local
	2185	print 'big = %d' % self.big
[406]	2186
[319]	2187	return byte_stream
	2188
[512]	2189	######################################################################################
[305]	2190	class Processor ( object ):
[512]	2191	######################################################################################
[319]	2192	def __init__( self,
[406]	2193	x,
	2194	y,
[319]	2195	lpid ):
	2196
	2197	self.index = 0 # global index ( set by addProc() )
	2198	self.x = x # x cluster coordinate
	2199	self.y = y # y cluster coordinate
	2200	self.lpid = lpid # processor local index
	2201
[305]	2202	return
	2203
[319]	2204	################
[406]	2205	def xml( self ): # xml for a processor
[305]	2206	return ' <proc index="%d" />\n' % (self.lpid)
	2207
[319]	2208	#############################################
	2209	def cbin( self, mapping, verbose, expected ): # C binary structure for Proc
	2210
	2211	if ( verbose ):
	2212	print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y)
	2213
	2214	# check index
	2215	if (self.index != expected):
[512]	2216	print '[genmap error] in Proc.cbin()'
	2217	print ' proc global index = %d / expected = %d' % (self.index,expected)
[319]	2218	sys.exit(1)
	2219
	2220	byte_stream = bytearray()
	2221	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
[406]	2222
[319]	2223	return byte_stream
	2224
[512]	2225	######################################################################################
[305]	2226	class Pseg ( object ):
[512]	2227	######################################################################################
[406]	2228	def __init__( self,
	2229	name,
	2230	base,
	2231	size,
[319]	2232	x,
	2233	y,
	2234	segtype ):
	2235
	2236	assert( segtype in PSEGTYPES )
	2237
	2238	self.index = 0 # global index ( set by addPseg() )
	2239	self.name = name # pseg name (unique in cluster)
	2240	self.base = base # physical base address
	2241	self.size = size # segment size (bytes)
[406]	2242	self.x = x # cluster x coordinate
	2243	self.y = y # cluster y coordinate
[319]	2244	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
	2245
[305]	2246	return
[406]	2247
[319]	2248	################
	2249	def xml( self ): # xml for a pseg
	2250
[305]	2251	return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
	2252	% (self.name, self.segtype, self.base, self.size)
	2253
[319]	2254	######################################################
	2255	def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg
	2256
	2257	if ( verbose ):
	2258	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
	2259	% (self.index, self.name, cluster.x, cluster.y)
	2260
	2261	# check index
	2262	if (self.index != expected):
[512]	2263	print '[genmap error] in Pseg.cbin()'
	2264	print ' pseg global index = %d / expected = %d' % (self.index,expected)
[319]	2265	sys.exit(1)
[406]	2266
[319]	2267	# compute numerical value for segtype
	2268	segtype_int = 0xFFFFFFFF
[406]	2269	for x in xrange( len(PSEGTYPES) ):
[512]	2270	if ( self.segtype == PSEGTYPES[x] ): segtype_int = x
	2271
[319]	2272	if ( segtype_int == 0xFFFFFFFF ):
[512]	2273	print '[genmap error] in Pseg.cbin()'
	2274	print ' undefined segment type %s' % self.segtype
[319]	2275	sys.exit(1)
	2276
	2277	byte_stream = bytearray()
[406]	2278	byte_stream += mapping.str2bytes( 32, self.name ) # pseg name
[319]	2279	byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address
	2280	byte_stream += mapping.int2bytes( 8 , self.size ) # segment length
	2281	byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type
	2282	byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index
[406]	2283	byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs
[319]	2284
	2285	if ( verbose ):
	2286	print 'pbase = %x' % self.base
	2287	print 'size = %x' % self.size
	2288	print 'type = %s' % self.segtype
[406]	2289
[319]	2290	return byte_stream
	2291
[512]	2292	######################################################################################
[319]	2293	class Periph ( object ):
[512]	2294	######################################################################################
[406]	2295	def __init__( self,
[319]	2296	pseg, # associated pseg
	2297	ptype, # peripheral type
	2298	subtype = 'NONE', # peripheral subtype
	2299	channels = 1, # for multi-channels peripherals
[520]	2300	arg0 = 0, # optional argument (semantic depends on ptype)
	2301	arg1 = 0, # optional argument (semantic depends on ptype)
	2302	arg2 = 0, # optional argument (semantic depends on ptype)
	2303	arg3 = 0 ): # optional argument (semantic depends on ptype)
[319]	2304
	2305	self.index = 0 # global index ( set by addPeriph() )
[406]	2306	self.channels = channels
	2307	self.ptype = ptype
	2308	self.subtype = subtype
[520]	2309	self.arg0 = arg0
	2310	self.arg1 = arg1
	2311	self.arg2 = arg2
	2312	self.arg3 = arg3
[319]	2313	self.pseg = pseg
	2314	self.irqs = []
[305]	2315	return
	2316
[319]	2317	################
	2318	def xml( self ): # xml for a periph
	2319
	2320	s = ' <periph type="%s"' % self.ptype
	2321	s += ' subtype="%s"' % self.subtype
	2322	s += ' psegname="%s"' % self.pseg.name
	2323	s += ' channels="%d"' % self.channels
[520]	2324	s += ' arg0="%d"' % self.arg0
	2325	s += ' arg1="%d"' % self.arg1
	2326	s += ' arg2="%d"' % self.arg2
	2327	s += ' arg3="%d"' % self.arg3
[441]	2328	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') ):
[520]	2329	s += ' >\n'
[319]	2330	for irq in self.irqs: s += irq.xml()
[520]	2331	s += ' </periph>\n'
	2332	else:
	2333	s += ' />\n'
[305]	2334	return s
	2335
[319]	2336	#############################################
	2337	def cbin( self, mapping, verbose, expected ): # C binary structure for Periph
[305]	2338
[319]	2339	if ( verbose ):
	2340	print '*** cbin for periph %s in cluster [%d,%d]' \
	2341	% (self.ptype, self.pseg.x, self.pseg.y)
[305]	2342
[319]	2343	# check index
	2344	if (self.index != expected):
[512]	2345	print '[genmap error] in Periph.cbin()'
	2346	print ' periph global index = %d / expected = %d' % (self.index,expected)
[319]	2347	sys.exit(1)
[305]	2348
[319]	2349	# compute pseg global index
	2350	pseg_id = self.pseg.index
[305]	2351
[319]	2352	# compute first irq global index
	2353	if ( len(self.irqs) > 0 ):
	2354	irq_id = self.irqs[0].index
	2355	else:
	2356	irq_id = 0
[305]	2357
[319]	2358	# compute numerical value for ptype
	2359	ptype_id = 0xFFFFFFFF
[406]	2360	for x in xrange( len(PERIPHTYPES) ):
[319]	2361	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
[512]	2362
[319]	2363	if ( ptype_id == 0xFFFFFFFF ):
[512]	2364	print '[genmap error] in Periph.cbin()'
	2365	print ' undefined peripheral type %s' % self.ptype
[319]	2366	sys.exit(1)
[305]	2367
[319]	2368	# compute numerical value for subtype
	2369	subtype_id = 0xFFFFFFFF
[520]	2370	if (self.ptype == 'IOC'):
	2371	for x in xrange( len(IOCSUBTYPES) ):
	2372	if ( self.subtype == IOCSUBTYPES[x] ): subtype_id = x
	2373	if (self.ptype == 'MWR'):
	2374	for x in xrange( len(MWRSUBTYPES) ):
	2375	if ( self.subtype == MWRSUBTYPES[x] ): subtype_id = x
	2376
[319]	2377	byte_stream = bytearray()
[406]	2378	byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type
[319]	2379	byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype
[406]	2380	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
[319]	2381	byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels
[520]	2382	byte_stream += mapping.int2bytes( 4 , self.arg0 ) # optionnal arg0
	2383	byte_stream += mapping.int2bytes( 4 , self.arg1 ) # optionnal arg1
	2384	byte_stream += mapping.int2bytes( 4 , self.arg2 ) # optionnal arg2
	2385	byte_stream += mapping.int2bytes( 4 , self.arg3 ) # optionnal arg3
[406]	2386	byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs
	2387	byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index
[305]	2388
[319]	2389	if ( verbose ):
	2390	print 'ptype = %d' % ptype_id
[520]	2391	print 'subtype = %d' % subtype_id
[319]	2392	print 'pseg_id = %d' % pseg_id
	2393	print 'nb_irqs = %d' % len( self.irqs )
[406]	2394	print 'irq_id = %d' % irq_id
[319]	2395	return byte_stream
[305]	2396
[512]	2397	######################################################################################
[319]	2398	class Irq ( object ):
[512]	2399	######################################################################################
[406]	2400	def __init__( self,
[319]	2401	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
	2402	srcid, # input IRQ index (for XCU or PIC)
	2403	isrtype, # Type of ISR to be executed
	2404	channel = 0 ): # channel index for multi-channel ISR
[305]	2405
[319]	2406	assert irqtype in IRQTYPES
	2407	assert isrtype in ISRTYPES
	2408	assert srcid < 32
[305]	2409
[319]	2410	self.index = 0 # global index ( set by addIrq() )
[406]	2411	self.irqtype = irqtype # IRQ type
[319]	2412	self.srcid = srcid # source IRQ index
[406]	2413	self.isrtype = isrtype # ISR type
[319]	2414	self.channel = channel # channel index (for multi-channels ISR)
[305]	2415	return
	2416
[319]	2417	################
	2418	def xml( self ): # xml for Irq
[305]	2419
[319]	2420	return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
	2421	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
[305]	2422
[319]	2423	#############################################
	2424	def cbin( self, mapping, verbose, expected ): # C binary structure for Irq
[305]	2425
[319]	2426	if ( verbose ):
[406]	2427	print '*** cbin for irq[%d]' % (self.index)
[305]	2428
[319]	2429	# check index
	2430	if (self.index != expected):
[512]	2431	print '[genmap error] in Irq.cbin()'
	2432	print ' irq global index = %d / expected = %d' % (self.index,expected)
[319]	2433	sys.exit(1)
[305]	2434
[319]	2435	# compute numerical value for irqtype
	2436	irqtype_id = 0xFFFFFFFF
	2437	for x in xrange( len(IRQTYPES) ):
[512]	2438	if ( self.irqtype == IRQTYPES[x] ): irqtype_id = x
	2439
[319]	2440	if ( irqtype_id == 0xFFFFFFFF ):
[512]	2441	print '[genmap error] in Irq.cbin()'
	2442	print ' undefined irqtype %s' % self.irqtype
[319]	2443	sys.exit(1)
[305]	2444
[319]	2445	# compute numerical value for isrtype
	2446	isrtype_id = 0xFFFFFFFF
[406]	2447	for x in xrange( len(ISRTYPES) ):
[512]	2448	if ( self.isrtype == ISRTYPES[x] ): isrtype_id = x
	2449
[319]	2450	if ( isrtype_id == 0xFFFFFFFF ):
[512]	2451	print '[genmap error] in Irq.cbin()'
	2452	print ' undefined isrtype %s' % self.isrtype
[319]	2453	sys.exit(1)
	2454
	2455	byte_stream = bytearray()
	2456	byte_stream += mapping.int2bytes( 4, irqtype_id )
	2457	byte_stream += mapping.int2bytes( 4, self.srcid )
	2458	byte_stream += mapping.int2bytes( 4, isrtype_id )
	2459	byte_stream += mapping.int2bytes( 4, self.channel )
	2460	byte_stream += mapping.int2bytes( 4, 0 )
	2461	byte_stream += mapping.int2bytes( 4, 0 )
	2462
	2463	if ( verbose ):
	2464	print 'irqtype = %s' % self.irqtype
	2465	print 'srcid = %d' % self.srcid
	2466	print 'isrtype = %s' % self.isrtype
	2467	print 'channel = %d' % self.channel
	2468
	2469	return byte_stream
	2470
[305]	2471	# Local Variables:
	2472	# tab-width: 4;
	2473	# c-basic-offset: 4;
	2474	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	2475	# indent-tabs-mode: nil;
	2476	# End:
	2477	#
	2478	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	2479

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