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source: soft/giet_vm/giet_python/mapping.py @ 537

Last change on this file since 537 was 537, checked in by alain, 10 years ago

Modify the hard_config.h file:

XCU_NB_INPUTS parameter removed
XCU_NB_HWI parameter introduced
XCU_NB_PTI parameter introduced
XCU_NB_WTI parameter introduced
XCU_NB_IRQ parameter introduced

Property svn:executable set to *

File size: 100.2 KB

Rev	Line
[425]	1	#!/usr/bin/env python
[305]	2
[319]	3	import sys
	4
[512]	5	########################################################################################
[305]	6	# file : giet_mapping.py
	7	# date : april 2014
	8	# author : Alain Greiner
[512]	9	########################################################################################
[319]	10	# This file contains the classes required to define a mapping for the GIET_VM.
	11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
[520]	12	# a set of 'Vseg' (kernel glogals virtual segments)
	13	# a set of 'Vspace' (one or several user applications)
[512]	14	# - A 'Cluster' contains a set of 'Pseg' (physical segments in cluster)
[319]	15	# a set of 'Proc' (processors in cluster)
	16	# a set of 'Periph' (peripherals in cluster)
[512]	17	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments)
	18	# a set of 'Task' (user parallel tasks)
[441]	19	# - A 'Periph' contains a set of 'Irq' (only for XCU and PIC types )
[512]	20	########################################################################################
[319]	21	# Implementation Note
[512]	22	# The objects used to describe a mapping are distributed in the PYTHON structure:
[319]	23	# For example the psegs set is split in several subsets (one subset per cluster),
	24	# or the tasks set is split in several subsets (one subset per vspace), etc...
	25	# In the C binary data structure used by the giet_vm, all objects of same type
[406]	26	# are stored in a linear array (one single array for all psegs for example).
[512]	27	# For all objects, we compute and store in the PYTHON object itself a "global index"
[406]	28	# corresponding to the index in this global array, and this index can be used as
[319]	29	# a pseudo-pointer to identify a specific object of a given type.
[512]	30	########################################################################################
[305]	31
[512]	32	########################################################################################
[411]	33	# Various constants
[512]	34	########################################################################################
[411]	35
	36	PADDR_WIDTH = 40 # number of bits for physical address
	37	X_WIDTH = 4 # number of bits encoding x coordinate
	38	Y_WIDTH = 4 # number of bits encoding y coordinate
	39	P_WIDTH = 4 # number of bits encoding local proc_id
	40	VPN_ANTI_MASK = 0x00000FFF # mask virtual address to get offset in a small page
	41	BPN_MASK = 0xFFE00000 # mask virtual address to get the BPN (big page)
[520]	42	PERI_INCREMENT = 0x10000 # virtual address increment for replicated l vsegs
[411]	43	RESET_ADDRESS = 0xBFC00000 # Processor wired boot_address
	44	MAPPING_SIGNATURE = 0xDACE2014 # Magic number indicating a valid C binary struture
	45
[512]	46	########################################################################################
[520]	47	# These lists must be consistent with values defined in
	48	# mapping_info.h / xml_driver.c /xml_parser.c
[512]	49	########################################################################################
[319]	50	PERIPHTYPES = [
	51	'CMA',
	52	'DMA',
	53	'FBF',
	54	'IOB',
	55	'IOC',
	56	'MMC',
	57	'MWR',
	58	'NIC',
	59	'ROM',
	60	'SIM',
	61	'TIM',
	62	'TTY',
	63	'XCU',
	64	'PIC',
[491]	65	'DROM',
[319]	66	]
	67
[520]	68	IOCSUBTYPES = [
[319]	69	'BDV',
	70	'HBA',
	71	'SPI',
	72	'NONE',
	73	]
	74
[520]	75	MWRSUBTYPES = [
	76	'GCD',
	77	'DCT',
	78	]
	79
	80	######################################################################################
	81	# These lists must be consistent with values defined in
	82	# irq_handler.c / irq_handler.h / xml_driver.c / xml_parser.c
	83	######################################################################################
[319]	84	IRQTYPES = [
	85	'HWI',
	86	'WTI',
	87	'PTI',
	88	]
	89
	90	ISRTYPES = [
	91	'ISR_DEFAULT',
	92	'ISR_TICK',
	93	'ISR_TTY_RX',
	94	'ISR_TTY_TX',
	95	'ISR_BDV',
	96	'ISR_TIMER',
	97	'ISR_WAKUP',
	98	'ISR_NIC_RX',
	99	'ISR_NIC_TX',
	100	'ISR_CMA',
	101	'ISR_MMC',
	102	'ISR_DMA',
	103	'ISR_SPI',
[532]	104	'ISR_MWR',
	105	'ISR_HBA',
[319]	106	]
	107
[512]	108	VSEGTYPES = [
[319]	109	'ELF',
	110	'BLOB',
	111	'PTAB',
	112	'PERI',
[512]	113	'MWMR', # deprecated
	114	'LOCK', # deprecated
[319]	115	'BUFFER',
[512]	116	'BARRIER', # deprecated
	117	'CONST', # deprecated
	118	'MEMSPACE', # deprecated
	119	'SCHED',
[471]	120	'HEAP',
[319]	121	]
	122
	123	VSEGMODES = [
	124	'____',
	125	'___U',
	126	'__W_',
	127	'__WU',
	128	'_X__',
	129	'_X_U',
	130	'_XW_',
	131	'_XWU',
	132	'C___',
	133	'C__U',
	134	'C_W_',
	135	'C_WU',
	136	'CX__',
	137	'CX_U',
	138	'CXW_',
	139	'CXWU',
	140	]
	141
	142	PSEGTYPES = [
	143	'RAM',
	144	'PERI',
	145	]
	146
[512]	147	#######################################################################################
[305]	148	class Mapping( object ):
[512]	149	#######################################################################################
[305]	150	def __init__( self,
[411]	151	name, # mapping name
	152	x_size, # number of clusters in a row
	153	y_size, # number of clusters in a column
[421]	154	nprocs, # max number of processors per cluster
[411]	155	x_width = X_WIDTH, # number of bits encoding x coordinate
	156	y_width = Y_WIDTH, # number of bits encoding y coordinate
[512]	157	p_width = P_WIDTH, # number of bits encoding lpid
[411]	158	paddr_width = PADDR_WIDTH, # number of bits for physical address
[512]	159	coherence = 1, # hardware cache coherence if non-zero
[411]	160	irq_per_proc = 1, # number or IRQs from XCU to processor
	161	use_ramdisk = False, # use ramdisk when true
	162	x_io = 0, # cluster_io x coordinate
	163	y_io = 0, # cluster_io y coordinate
	164	peri_increment = PERI_INCREMENT, # address increment for globals
	165	reset_address = RESET_ADDRESS, # Processor wired boot_address
	166	ram_base = 0, # RAM physical base in cluster[0,0]
	167	ram_size = 0 ): # RAM size in each cluster (bytes)
[305]	168
[411]	169	assert ( x_size <= (1<<X_WIDTH) )
	170	assert ( y_size <= (1<<Y_WIDTH) )
	171	assert ( nprocs <= (1<<P_WIDTH) )
[406]	172
[411]	173	self.signature = MAPPING_SIGNATURE
[319]	174	self.name = name
[497]	175	self.name = name
[406]	176	self.paddr_width = paddr_width
[319]	177	self.coherence = coherence
	178	self.x_size = x_size
	179	self.y_size = y_size
[441]	180	self.nprocs = nprocs
[319]	181	self.x_width = x_width
	182	self.y_width = y_width
[406]	183	self.p_width = p_width
[319]	184	self.irq_per_proc = irq_per_proc
	185	self.use_ramdisk = use_ramdisk
	186	self.x_io = x_io
	187	self.y_io = y_io
[328]	188	self.peri_increment = peri_increment
[319]	189	self.reset_address = reset_address
[356]	190	self.ram_base = ram_base
	191	self.ram_size = ram_size
[305]	192
[319]	193	self.total_vspaces = 0
	194	self.total_globals = 0
	195	self.total_psegs = 0
	196	self.total_vsegs = 0
	197	self.total_tasks = 0
	198	self.total_procs = 0
	199	self.total_irqs = 0
	200	self.total_periphs = 0
[305]	201
[319]	202	self.clusters = []
	203	self.globs = []
	204	self.vspaces = []
[305]	205
[319]	206	for x in xrange( self.x_size ):
	207	for y in xrange( self.y_size ):
	208	cluster = Cluster( x , y )
[406]	209	cluster.index = (x * self.y_size) + y
[319]	210	self.clusters.append( cluster )
[305]	211
	212	return
	213
[319]	214	########################## add a ram pseg in a cluster
[406]	215	def addRam( self,
[319]	216	name, # pseg name
	217	base, # pseg base address
	218	size ): # pseg length (bytes)
[406]	219
[497]	220	# computes cluster index and coordinates from the base address
[356]	221	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
	222	cluster_xy = base >> paddr_lsb_width
[497]	223	x = cluster_xy >> (self.y_width);
	224	y = cluster_xy & ((1 << self.y_width) - 1)
	225	cluster_id = (x * self.y_size) + y
[305]	226
[411]	227	assert (base & VPN_ANTI_MASK) == 0
[319]	228
	229	assert (x < self.x_size) and (y < self.y_size)
[406]	230
[356]	231	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
	232
	233	assert ( size == self.ram_size )
	234
[319]	235	# add one pseg in the mapping
	236	pseg = Pseg( name, base, size, x, y, 'RAM' )
	237	self.clusters[cluster_id].psegs.append( pseg )
	238	pseg.index = self.total_psegs
	239	self.total_psegs += 1
	240
	241	return pseg
	242
[512]	243	########################## add a peripheral and the associated pseg in a cluster
[406]	244	def addPeriph( self,
[319]	245	name, # associated pseg name
	246	base, # associated pseg base address
	247	size, # associated pseg length (bytes)
[406]	248	ptype, # peripheral type
[319]	249	subtype = 'NONE', # peripheral subtype
	250	channels = 1, # number of channels
[520]	251	arg0 = 0, # optional argument (semantic depends on ptype)
	252	arg1 = 0, # optional argument (semantic depends on ptype)
	253	arg2 = 0, # optional argument (semantic depends on ptype)
	254	arg3 = 0 ): # optional argument (semantic depends on ptype)
[319]	255
[497]	256	# computes cluster index and coordinates from the base address
[319]	257	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
[497]	258	x = cluster_xy >> (self.y_width);
	259	y = cluster_xy & ((1 << self.y_width) - 1)
	260	cluster_id = (x * self.y_size) + y
[305]	261
[319]	262	assert (x < self.x_size) and (y < self.y_size)
	263
[411]	264	assert (base & VPN_ANTI_MASK) == 0
[319]	265
	266	assert ptype in PERIPHTYPES
	267
[520]	268	if (ptype == 'IOC'): assert subtype in IOCSUBTYPES
	269	if (ptype == 'MWR'): assert subtype in MWRSUBTYPES
[319]	270
	271	# add one pseg into mapping
	272	pseg = Pseg( name, base, size, x, y, 'PERI' )
	273	self.clusters[cluster_id].psegs.append( pseg )
	274	pseg.index = self.total_psegs
	275	self.total_psegs += 1
	276
	277	# add one periph into mapping
[520]	278	periph = Periph( pseg, ptype, subtype, channels, arg0, arg1, arg2, arg3 )
[319]	279	self.clusters[cluster_id].periphs.append( periph )
	280	periph.index = self.total_periphs
	281	self.total_periphs += 1
	282
	283	return periph
	284
	285	################################ add an IRQ in a peripheral
	286	def addIrq( self,
	287	periph, # peripheral containing IRQ (PIC or XCU)
	288	index, # peripheral input port index
	289	isrtype, # ISR type
	290	channel = 0 ): # channel for multi-channels ISR
	291
	292	assert isrtype in ISRTYPES
	293
	294	assert index < 32
	295
[406]	296	# add one irq into mapping
[319]	297	irq = Irq( 'HWI', index , isrtype, channel )
	298	periph.irqs.append( irq )
	299	irq.index = self.total_irqs
	300	self.total_irqs += 1
	301
	302	return irq
	303
	304	########################## add a processor in a cluster
[406]	305	def addProc( self,
[319]	306	x, # cluster x coordinate
	307	y, # cluster y coordinate
[520]	308	lpid ): # processor local index
[319]	309
	310	assert (x < self.x_size) and (y < self.y_size)
	311
	312	cluster_id = (x * self.y_size) + y
	313
[406]	314	# add one proc into mapping
[520]	315	proc = Processor( x, y, lpid )
[319]	316	self.clusters[cluster_id].procs.append( proc )
	317	proc.index = self.total_procs
[305]	318	self.total_procs += 1
	319
[319]	320	return proc
	321
[411]	322	############################ add one global vseg into mapping
	323	def addGlobal( self,
	324	name, # vseg name
	325	vbase, # virtual base address
[512]	326	length, # vseg length (bytes)
[411]	327	mode, # CXWU flags
[512]	328	vtype, # vseg type
[411]	329	x, # destination x coordinate
	330	y, # destination y coordinate
	331	pseg, # destination pseg name
	332	identity = False, # identity mapping required if true
	333	local = False, # only mapped in local PTAB if true
[512]	334	big = False, # to be mapped in a big physical page
	335	binpath = '' ): # pathname for binary code if required
[319]	336
[411]	337	# two global vsegs must not overlap if they have different names
	338	for prev in self.globs:
[512]	339	if ( ((prev.vbase + prev.length) > vbase ) and
	340	((vbase + length) > prev.vbase) and
[411]	341	(prev.name != name) ):
[512]	342	print '[genmap error] in addGlobal()'
	343	print ' global vseg %s overlap %s' % (name, prev.name)
	344	print ' %s : base = %x / size = %x' %( name, vbase, size )
	345	print ' %s : base = %x / size = %x' %( prev.name, prev.vbase, prev.size )
[411]	346	sys.exit(1)
	347
[328]	348	# add one vseg into mapping
[512]	349	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
	350	identity = identity, local = local, big = big, binpath = binpath )
[348]	351
[328]	352	self.globs.append( vseg )
	353	self.total_globals += 1
[406]	354	vseg.index = self.total_vsegs
[328]	355	self.total_vsegs += 1
[406]	356
[305]	357	return
	358
[319]	359	################################ add a vspace into mapping
[406]	360	def addVspace( self,
[319]	361	name, # vspace name
[512]	362	startname ): # name of vseg containing start_vector
[319]	363
	364	# add one vspace into mapping
	365	vspace = Vspace( name, startname )
[305]	366	self.vspaces.append( vspace )
[319]	367	vspace.index = self.total_vspaces
	368	self.total_vspaces += 1
	369
	370	return vspace
[406]	371
[512]	372	################################# add a private vseg in a vspace
[319]	373	def addVseg( self,
[406]	374	vspace, # vspace containing the vseg
[319]	375	name, # vseg name
	376	vbase, # virtual base address
[512]	377	length, # vseg length (bytes)
[319]	378	mode, # CXWU flags
[512]	379	vtype, # vseg type
[319]	380	x, # destination x coordinate
	381	y, # destination y coordinate
	382	pseg, # destination pseg name
[411]	383	local = False, # only mapped in local PTAB if true
[512]	384	big = False, # to be mapped in a big physical page
	385	binpath = '' ): # pathname for binary code
[319]	386
	387	assert mode in VSEGMODES
	388
[512]	389	assert vtype in VSEGTYPES
[319]	390
	391	assert (x < self.x_size) and (y < self.y_size)
	392
	393	# add one vseg into mapping
[512]	394	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
	395	identity = False, local = local, big = big, binpath = binpath )
[319]	396	vspace.vsegs.append( vseg )
	397	vseg.index = self.total_vsegs
	398	self.total_vsegs += 1
	399
	400	return vseg
	401
[406]	402	################################ add a task in a vspace
	403	def addTask( self,
[319]	404	vspace, # vspace containing task
	405	name, # task name
	406	trdid, # task index in vspace
	407	x, # destination x coordinate
	408	y, # destination y coordinate
	409	lpid, # destination processor local index
[512]	410	stackname, # name of vseg containing stack
	411	heapname, # name of vseg containing heap
[441]	412	startid ): # index in start_vector
[406]	413
[319]	414	assert (x < self.x_size) and (y < self.y_size)
[411]	415	assert lpid < self.nprocs
[319]	416
[406]	417	# add one task into mapping
[441]	418	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid )
[319]	419	vspace.tasks.append( task )
	420	task.index = self.total_tasks
	421	self.total_tasks += 1
	422
	423	return task
	424
	425	#################################
	426	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
	427
	428	byte_stream = bytearray()
	429	length = len( s )
	430	if length < (nbytes - 1):
	431	for b in s:
	432	byte_stream.append( b )
	433	for x in xrange(nbytes-length):
	434	byte_stream.append( '\0' )
	435	else:
[512]	436	print '[genmap error] in str2bytes()'
	437	print ' string %s too long' % s
[319]	438	sys.exit(1)
	439
	440	return byte_stream
	441
	442	###################################
[406]	443	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
[319]	444
	445	byte_stream = bytearray()
	446	for n in xrange( nbytes ):
	447	byte_stream.append( (val >> (n<<3)) & 0xFF )
	448
	449	return byte_stream
	450
[512]	451	################
[411]	452	def xml( self ): # compute string for map.xml file generation
[319]	453
[305]	454	s = '<?xml version="1.0"?>\n\n'
[319]	455	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
[305]	456	s += ' name = "%s"\n' % (self.name)
	457	s += ' x_size = "%d"\n' % (self.x_size)
	458	s += ' y_size = "%d"\n' % (self.y_size)
	459	s += ' x_width = "%d"\n' % (self.x_width)
	460	s += ' y_width = "%d"\n' % (self.y_width)
	461	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
[319]	462	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
[305]	463	s += ' x_io = "%d"\n' % (self.x_io)
	464	s += ' y_io = "%d" >\n' % (self.y_io)
[319]	465	s += '\n'
	466
[305]	467	s += ' <clusterset>\n'
	468	for x in xrange ( self.x_size ):
	469	for y in xrange ( self.y_size ):
[406]	470	cluster_id = (x * self.y_size) + y
[319]	471	s += self.clusters[cluster_id].xml()
[305]	472	s += ' </clusterset>\n'
[319]	473	s += '\n'
	474
[305]	475	s += ' <globalset>\n'
[319]	476	for vseg in self.globs: s += vseg.xml()
[305]	477	s += ' </globalset>\n'
[319]	478	s += '\n'
	479
[305]	480	s += ' <vspaceset>\n'
[319]	481	for vspace in self.vspaces: s += vspace.xml()
[305]	482	s += ' </vspaceset>\n'
[319]	483
[305]	484	s += '</mapping_info>\n'
	485	return s
[319]	486
[512]	487	##########################
[411]	488	def cbin( self, verbose ): # C binary structure for map.bin file generation
[319]	489
	490	byte_stream = bytearray()
	491
	492	# header
	493	byte_stream += self.int2bytes(4, self.signature)
[406]	494	byte_stream += self.int2bytes(4, self.x_size)
	495	byte_stream += self.int2bytes(4, self.y_size)
	496	byte_stream += self.int2bytes(4, self.x_width)
	497	byte_stream += self.int2bytes(4, self.y_width)
	498	byte_stream += self.int2bytes(4, self.x_io)
	499	byte_stream += self.int2bytes(4, self.y_io)
	500	byte_stream += self.int2bytes(4, self.irq_per_proc)
	501	byte_stream += self.int2bytes(4, self.use_ramdisk)
	502	byte_stream += self.int2bytes(4, self.total_globals)
	503	byte_stream += self.int2bytes(4, self.total_vspaces)
	504	byte_stream += self.int2bytes(4, self.total_psegs)
	505	byte_stream += self.int2bytes(4, self.total_vsegs)
	506	byte_stream += self.int2bytes(4, self.total_tasks)
	507	byte_stream += self.int2bytes(4, self.total_procs)
	508	byte_stream += self.int2bytes(4, self.total_irqs)
	509	byte_stream += self.int2bytes(4, self.total_periphs)
[319]	510	byte_stream += self.str2bytes(32, self.name)
	511
	512	if ( verbose ):
[406]	513	print '\n'
[319]	514	print 'name = %s' % self.name
	515	print 'signature = %x' % self.signature
	516	print 'x_size = %d' % self.x_size
	517	print 'y_size = %d' % self.y_size
	518	print 'x_width = %d' % self.x_width
	519	print 'y_width = %d' % self.y_width
[406]	520	print 'x_io = %d' % self.x_io
	521	print 'y_io = %d' % self.y_io
[319]	522	print 'irq_per_proc = %d' % self.irq_per_proc
	523	print 'use_ramdisk = %d' % self.use_ramdisk
	524	print 'total_globals = %d' % self.total_globals
[406]	525	print 'total_psegs = %d' % self.total_psegs
	526	print 'total_vsegs = %d' % self.total_vsegs
	527	print 'total_tasks = %d' % self.total_tasks
	528	print 'total_procs = %d' % self.total_procs
	529	print 'total_irqs = %d' % self.total_irqs
[319]	530	print 'total_periphs = %d' % self.total_periphs
[406]	531	print '\n'
[319]	532
	533	# clusters array
	534	index = 0
	535	for cluster in self.clusters:
	536	byte_stream += cluster.cbin( self, verbose, index )
	537	index += 1
	538
	539	if ( verbose ): print '\n'
	540
	541	# psegs array
	542	index = 0
	543	for cluster in self.clusters:
[406]	544	for pseg in cluster.psegs:
[319]	545	byte_stream += pseg.cbin( self, verbose, index, cluster )
	546	index += 1
	547
	548	if ( verbose ): print '\n'
	549
	550	# vspaces array
	551	index = 0
[406]	552	for vspace in self.vspaces:
	553	byte_stream += vspace.cbin( self, verbose, index )
[319]	554	index += 1
	555
	556	if ( verbose ): print '\n'
	557
	558	# vsegs array
	559	index = 0
	560	for vseg in self.globs:
	561	byte_stream += vseg.cbin( self, verbose, index )
	562	index += 1
	563	for vspace in self.vspaces:
[406]	564	for vseg in vspace.vsegs:
[319]	565	byte_stream += vseg.cbin( self, verbose, index )
	566	index += 1
	567
	568	if ( verbose ): print '\n'
	569
	570	# tasks array
	571	index = 0
	572	for vspace in self.vspaces:
[406]	573	for task in vspace.tasks:
[319]	574	byte_stream += task.cbin( self, verbose, index, vspace )
	575	index += 1
	576
	577	if ( verbose ): print '\n'
	578
	579	# procs array
	580	index = 0
	581	for cluster in self.clusters:
[406]	582	for proc in cluster.procs:
[319]	583	byte_stream += proc.cbin( self, verbose, index )
	584	index += 1
[406]	585
[319]	586	if ( verbose ): print '\n'
	587
	588	# irqs array
[406]	589	index = 0
[319]	590	for cluster in self.clusters:
	591	for periph in cluster.periphs:
	592	for irq in periph.irqs:
	593	byte_stream += irq.cbin( self, verbose, index )
	594	index += 1
	595
	596	if ( verbose ): print '\n'
	597
	598	# periphs array
	599	index = 0
	600	for cluster in self.clusters:
[406]	601	for periph in cluster.periphs:
[319]	602	byte_stream += periph.cbin( self, verbose, index )
	603	index += 1
	604
	605	return byte_stream
	606	# end of cbin()
[406]	607
[411]	608	##################################################################################
	609	def giet_vsegs( self ): # compute string for giet_vsegs.ld file generation
[319]	610	# required by giet_vm compilation
	611
[406]	612	# search the vsegs required for the giet_vsegs.ld
[319]	613	boot_code_found = False
	614	boot_data_found = False
	615	kernel_uncdata_found = False
	616	kernel_data_found = False
	617	kernel_code_found = False
	618	kernel_init_found = False
	619	for vseg in self.globs:
[348]	620
[319]	621	if ( vseg.name == 'seg_boot_code' ):
[406]	622	boot_code_vbase = vseg.vbase
[512]	623	boot_code_size = vseg.length
[319]	624	boot_code_found = True
	625
[406]	626	if ( vseg.name == 'seg_boot_data' ):
	627	boot_data_vbase = vseg.vbase
[512]	628	boot_data_size = vseg.length
[319]	629	boot_data_found = True
	630
	631	if ( vseg.name == 'seg_kernel_data' ):
[406]	632	kernel_data_vbase = vseg.vbase
[512]	633	kernel_data_size = vseg.length
[319]	634	kernel_data_found = True
	635
	636	if ( vseg.name == 'seg_kernel_code' ):
[406]	637	kernel_code_vbase = vseg.vbase
[512]	638	kernel_code_size = vseg.length
[319]	639	kernel_code_found = True
	640
	641	if ( vseg.name == 'seg_kernel_init' ):
[406]	642	kernel_init_vbase = vseg.vbase
[512]	643	kernel_init_size = vseg.length
[319]	644	kernel_init_found = True
	645
	646	# check if all required vsegs have been found
[406]	647	if ( boot_code_found == False ):
[512]	648	print '[genmap error] in giet_vsegs()'
	649	print ' seg_boot_code vseg missing'
[319]	650	sys.exit()
	651
[406]	652	if ( boot_data_found == False ):
[512]	653	print '[genmap error] in giet_vsegs()'
	654	print ' seg_boot_data vseg missing'
[319]	655	sys.exit()
	656
[406]	657	if ( kernel_data_found == False ):
[512]	658	print '[genmap error] in giet_vsegs()'
	659	print ' seg_kernel_data vseg missing'
[319]	660	sys.exit()
	661
	662	if ( kernel_code_found == False ):
[512]	663	print '[genmap error] in giet_vsegs()'
	664	print ' seg_kernel_code vseg missing'
[319]	665	sys.exit()
	666
	667	if ( kernel_init_found == False ):
[512]	668	print '[genmap error] in giet_vsegs()'
	669	print ' seg_kernel_init vseg missing'
[319]	670	sys.exit()
	671
	672	# build string
[406]	673	s = '/* Generated by genmap for %s */\n' % self.name
[319]	674	s += '\n'
	675
[406]	676	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
	677	s += 'boot_code_size = 0x%x;\n' % boot_code_size
[319]	678	s += '\n'
[406]	679	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
	680	s += 'boot_data_size = 0x%x;\n' % boot_data_size
[319]	681	s += '\n'
[406]	682	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
	683	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
[319]	684	s += '\n'
[406]	685	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
	686	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
[319]	687	s += '\n'
[406]	688	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
	689	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
[319]	690	s += '\n'
	691
	692	return s
[406]	693
[411]	694	###################################################################################
	695	def hard_config( self ): # compute string for hard_config.h file generation,
	696	# required by
[319]	697	# - top.cpp compilation
	698	# - giet_vm compilation
	699	# - tsar_preloader compilation
	700
	701	nb_total_procs = 0
	702
	703	# for each peripheral type, define default values
[406]	704	# for pbase address, size, number of components, and channels
[319]	705	nb_cma = 0
	706	cma_channels = 0
	707	seg_cma_base = 0xFFFFFFFF
	708	seg_cma_size = 0
	709
	710	nb_dma = 0
	711	dma_channels = 0
	712	seg_dma_base = 0xFFFFFFFF
	713	seg_dma_size = 0
	714
	715	nb_fbf = 0
	716	fbf_channels = 0
	717	seg_fbf_base = 0xFFFFFFFF
	718	seg_fbf_size = 0
[520]	719	fbf_arg0 = 0
	720	fbf_arg1 = 0
[319]	721
	722	nb_iob = 0
	723	iob_channels = 0
	724	seg_iob_base = 0xFFFFFFFF
	725	seg_iob_size = 0
	726
	727	nb_ioc = 0
	728	ioc_channels = 0
	729	seg_ioc_base = 0xFFFFFFFF
	730	seg_ioc_size = 0
	731
	732	nb_mmc = 0
	733	mmc_channels = 0
	734	seg_mmc_base = 0xFFFFFFFF
	735	seg_mmc_size = 0
	736
	737	nb_mwr = 0
	738	mwr_channels = 0
	739	seg_mwr_base = 0xFFFFFFFF
	740	seg_mwr_size = 0
[520]	741	mwr_arg0 = 0
	742	mwr_arg1 = 0
	743	mwr_arg2 = 0
	744	mwr_arg3 = 0
[319]	745
	746	nb_nic = 0
	747	nic_channels = 0
	748	seg_nic_base = 0xFFFFFFFF
	749	seg_nic_size = 0
	750
	751	nb_pic = 0
	752	pic_channels = 0
	753	seg_pic_base = 0xFFFFFFFF
	754	seg_pic_size = 0
	755
	756	nb_rom = 0
	757	rom_channels = 0
	758	seg_rom_base = 0xFFFFFFFF
	759	seg_rom_size = 0
	760
	761	nb_sim = 0
	762	sim_channels = 0
	763	seg_sim_base = 0xFFFFFFFF
	764	seg_sim_size = 0
	765
	766	nb_tim = 0
	767	tim_channels = 0
	768	seg_tim_base = 0xFFFFFFFF
	769	seg_tim_size = 0
	770
	771	nb_tty = 0
	772	tty_channels = 0
	773	seg_tty_base = 0xFFFFFFFF
	774	seg_tty_size = 0
	775
	776	nb_xcu = 0
	777	xcu_channels = 0
	778	seg_xcu_base = 0xFFFFFFFF
	779	seg_xcu_size = 0
[520]	780	xcu_arg0 = 0
[319]	781
[491]	782	nb_drom = 0
	783	drom_channels = 0
	784	seg_drom_base = 0xFFFFFFFF
	785	seg_drom_size = 0
	786
[319]	787	use_bdv = False
	788	use_spi = False
	789	use_hba = False
	790
	791	# get peripherals attributes
	792	for cluster in self.clusters:
	793	for periph in cluster.periphs:
[406]	794	if ( periph.ptype == 'CMA' ):
[319]	795	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
	796	seg_cma_size = periph.pseg.size
	797	cma_channels = periph.channels
	798	nb_cma +=1
	799
[406]	800	elif ( periph.ptype == 'DMA' ):
	801	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
[319]	802	seg_dma_size = periph.pseg.size
	803	dma_channels = periph.channels
	804	nb_dma +=1
	805
[406]	806	elif ( periph.ptype == 'FBF' ):
[319]	807	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
	808	seg_fbf_size = periph.pseg.size
	809	fbf_channels = periph.channels
[520]	810	fbf_arg0 = periph.arg0
	811	fbf_arg1 = periph.arg1
[319]	812	nb_fbf +=1
	813
	814	elif ( periph.ptype == 'IOB' ):
	815	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
	816	seg_iob_size = periph.pseg.size
	817	iob_channels = periph.channels
	818	nb_iob +=1
	819
[406]	820	elif ( periph.ptype == 'IOC' ):
[319]	821	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
	822	seg_ioc_size = periph.pseg.size
	823	ioc_channels = periph.channels
	824	nb_ioc += 1
[404]	825
	826	if self.use_ramdisk: continue
	827
[319]	828	if ( periph.subtype == 'BDV' ): use_bdv = True
	829	elif ( periph.subtype == 'HBA' ): use_hba = True
	830	elif ( periph.subtype == 'SPI' ): use_spi = True
	831
	832	elif ( periph.ptype == 'MMC' ):
	833	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
	834	seg_mmc_size = periph.pseg.size
	835	mmc_channels = periph.channels
	836	nb_mmc +=1
	837
	838	elif ( periph.ptype == 'MWR' ):
	839	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
[520]	840	seg_mwr_size = periph.pseg.size
[319]	841	mwr_channels = periph.channels
[520]	842	mwr_arg0 = periph.arg0
	843	mwr_arg1 = periph.arg1
	844	mwr_arg2 = periph.arg2
	845	mwr_arg3 = periph.arg3
[319]	846	nb_mwr +=1
	847
	848	elif ( periph.ptype == 'ROM' ):
	849	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
	850	seg_rom_size = periph.pseg.size
	851	rom_channels = periph.channels
	852	nb_rom +=1
	853
[491]	854	elif ( periph.ptype == 'DROM' ):
	855	seg_drom_base = periph.pseg.base & 0xFFFFFFFF
	856	seg_drom_size = periph.pseg.size
	857	drom_channels = periph.channels
	858	nb_drom +=1
	859
[319]	860	elif ( periph.ptype == 'SIM' ):
	861	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
	862	seg_sim_size = periph.pseg.size
	863	sim_channels = periph.channels
	864	nb_sim +=1
	865
[406]	866	elif ( periph.ptype == 'NIC' ):
[319]	867	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
	868	seg_nic_size = periph.pseg.size
	869	nic_channels = periph.channels
	870	nb_nic +=1
	871
[406]	872	elif ( periph.ptype == 'PIC' ):
[319]	873	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
	874	seg_pic_size = periph.pseg.size
	875	pic_channels = periph.channels
	876	nb_pic +=1
[406]	877
	878	elif ( periph.ptype == 'TIM' ):
[319]	879	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
	880	seg_tim_size = periph.pseg.size
	881	tim_channels = periph.channels
	882	nb_tim +=1
[406]	883
[319]	884	elif ( periph.ptype == 'TTY' ):
	885	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
	886	seg_tty_size = periph.pseg.size
	887	tty_channels = periph.channels
	888	nb_tty +=1
[406]	889
	890	elif ( periph.ptype == 'XCU' ):
[319]	891	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
	892	seg_xcu_size = periph.pseg.size
	893	xcu_channels = periph.channels
[520]	894	xcu_arg0 = periph.arg0
[537]	895	xcu_arg1 = periph.arg1
	896	xcu_arg2 = periph.arg2
[319]	897	nb_xcu +=1
[406]	898
[319]	899	# no more than two access to external peripherals
[406]	900	assert ( nb_fbf <= 2 )
	901	assert ( nb_cma <= 2 )
	902	assert ( nb_ioc <= 2 )
	903	assert ( nb_nic <= 2 )
	904	assert ( nb_tim <= 2 )
	905	assert ( nb_tty <= 2 )
[319]	906	assert ( nb_pic <= 2 )
	907
	908	# one and only one type of IOC controller
[403]	909	nb_iocs = 0
	910	if use_hba : nb_iocs += 1
	911	if use_bdv : nb_iocs += 1
	912	if use_spi : nb_iocs += 1
	913	if self.use_ramdisk: nb_iocs += 1
	914	assert ( nb_iocs == 1 )
[404]	915
[319]	916	# Compute total number of processors
	917	for cluster in self.clusters:
	918	nb_total_procs += len( cluster.procs )
	919
	920	# Compute physical addresses for BOOT vsegs
	921	boot_mapping_found = False
	922	boot_code_found = False
	923	boot_data_found = False
	924	boot_stack_found = False
	925
	926	for vseg in self.globs:
	927	if ( vseg.name == 'seg_boot_mapping' ):
[406]	928	boot_mapping_base = vseg.vbase
[512]	929	boot_mapping_size = vseg.length
[348]	930	boot_mapping_identity = vseg.identity
[319]	931	boot_mapping_found = True
	932
	933	if ( vseg.name == 'seg_boot_code' ):
[406]	934	boot_code_base = vseg.vbase
[512]	935	boot_code_size = vseg.length
[348]	936	boot_code_identity = vseg.identity
[319]	937	boot_code_found = True
	938
[406]	939	if ( vseg.name == 'seg_boot_data' ):
	940	boot_data_base = vseg.vbase
[512]	941	boot_data_size = vseg.length
[348]	942	boot_data_identity = vseg.identity
[319]	943	boot_data_found = True
	944
	945	if ( vseg.name == 'seg_boot_stack' ):
[406]	946	boot_stack_base = vseg.vbase
[512]	947	boot_stack_size = vseg.length
[348]	948	boot_stack_identity = vseg.identity
[319]	949	boot_stack_found = True
	950
[328]	951	# check that BOOT vsegs are found and identity mapping
[348]	952	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
[512]	953	print '[genmap error] in hard_config()'
	954	print ' seg_boot_mapping missing or not identity mapping'
[319]	955	sys.exit()
	956
[406]	957	if ( (boot_code_found == False) or (boot_code_identity == False) ):
[512]	958	print '[genmap error] in hard_config()'
	959	print ' seg_boot_code missing or not identity mapping'
[319]	960	sys.exit()
	961
[406]	962	if ( (boot_data_found == False) or (boot_data_identity == False) ):
[512]	963	print '[genmap error] in hard_config()'
	964	print ' seg_boot_data missing or not identity mapping'
[319]	965	sys.exit()
	966
[348]	967	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
[512]	968	print '[genmap error] in giet_vsegs()'
	969	print ' seg_boot_stask missing or not identity mapping'
[319]	970	sys.exit()
	971
	972	# Search RAMDISK global vseg if required
	973	seg_rdk_base = 0xFFFFFFFF
	974	seg_rdk_size = 0
	975	seg_rdk_found = False
	976
	977	if self.use_ramdisk:
	978	for vseg in self.globs:
[497]	979	if ( vseg.name == 'seg_ramdisk' ):
[319]	980	seg_rdk_base = vseg.vbase
[512]	981	seg_rdk_size = vseg.length
[319]	982	seg_rdk_found = True
	983
	984	if ( seg_rdk_found == False ):
	985	print 'Error in hard_config() "seg_ramdisk" not found'
	986	sys.exit(1)
	987
	988	# build string
[406]	989	s = '/* Generated by genmap for %s */\n' % self.name
[319]	990	s += '\n'
	991	s += '#ifndef HARD_CONFIG_H\n'
	992	s += '#define HARD_CONFIG_H\n'
	993	s += '\n'
	994
[406]	995	s += '/* General platform parameters */\n'
[319]	996	s += '\n'
	997	s += '#define X_SIZE %d\n' % self.x_size
	998	s += '#define Y_SIZE %d\n' % self.y_size
	999	s += '#define X_WIDTH %d\n' % self.x_width
	1000	s += '#define Y_WIDTH %d\n' % self.y_width
[406]	1001	s += '#define P_WIDTH %d\n' % self.p_width
[319]	1002	s += '#define X_IO %d\n' % self.x_io
[406]	1003	s += '#define Y_IO %d\n' % self.y_io
[411]	1004	s += '#define NB_PROCS_MAX %d\n' % self.nprocs
[319]	1005	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
	1006	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
	1007	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
	1008	s += '\n'
	1009
[406]	1010	s += '/* Peripherals */\n'
[319]	1011	s += '\n'
	1012	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
	1013	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
	1014	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
	1015	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
	1016	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
	1017	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
	1018	s += '\n'
	1019	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
	1020	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
	1021	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
	1022	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
	1023	s += '\n'
	1024	s += '#define USE_IOC_BDV %d\n' % use_bdv
	1025	s += '#define USE_IOC_SPI %d\n' % use_spi
	1026	s += '#define USE_IOC_HBA %d\n' % use_hba
[403]	1027	s += '#define USE_IOC_RDK %d\n' % self.use_ramdisk
[319]	1028	s += '\n'
[520]	1029	s += '#define FBUF_X_SIZE %d\n' % fbf_arg0
	1030	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg1
[328]	1031	s += '\n'
[537]	1032	s += '#define XCU_NB_HWI %d\n' % xcu_arg0
	1033	s += '#define XCU_NB_PTI %d\n' % xcu_arg1
	1034	s += '#define XCU_NB_WTI %d\n' % xcu_arg2
	1035	s += '#define XCU_NB_OUT %d\n' % xcu_channels
[328]	1036	s += '\n'
[520]	1037	s += '#define MWR_TO_COPROC %d\n' % mwr_arg0
	1038	s += '#define MWR_FROM_COPROC %d\n' % mwr_arg1
	1039	s += '#define MWR_CONFIG %d\n' % mwr_arg2
	1040	s += '#define MWR_STATUS %d\n' % mwr_arg3
	1041	s += '\n'
[319]	1042
[356]	1043	s += '/* base addresses and sizes for physical segments */\n'
[319]	1044	s += '\n'
[406]	1045	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
	1046	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
[356]	1047	s += '\n'
[406]	1048	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
	1049	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
[319]	1050	s += '\n'
[406]	1051	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
	1052	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
[319]	1053	s += '\n'
[406]	1054	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
	1055	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
[319]	1056	s += '\n'
[406]	1057	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
	1058	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
[319]	1059	s += '\n'
[406]	1060	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
	1061	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
[319]	1062	s += '\n'
[406]	1063	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
	1064	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
[319]	1065	s += '\n'
[406]	1066	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
	1067	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
[319]	1068	s += '\n'
[406]	1069	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
	1070	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
[319]	1071	s += '\n'
[406]	1072	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
	1073	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
[319]	1074	s += '\n'
[406]	1075	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
	1076	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
[319]	1077	s += '\n'
[406]	1078	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
	1079	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
[319]	1080	s += '\n'
[406]	1081	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
	1082	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
[319]	1083	s += '\n'
[406]	1084	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
	1085	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
[319]	1086	s += '\n'
[406]	1087	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
	1088	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
[319]	1089	s += '\n'
	1090	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
	1091	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
	1092	s += '\n'
[491]	1093	s += '#define SEG_DROM_BASE 0x%x\n' % seg_drom_base
	1094	s += '#define SEG_DROM_SIZE 0x%x\n' % seg_drom_size
	1095	s += '\n'
[328]	1096	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
[319]	1097	s += '\n'
	1098
[326]	1099	s += '/* physical base addresses for identity mapped vsegs */\n'
	1100	s += '/* used by the GietVM OS */\n'
[319]	1101	s += '\n'
	1102	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
	1103	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
	1104	s += '\n'
	1105	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
	1106	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
	1107	s += '\n'
	1108	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
	1109	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
	1110	s += '\n'
	1111	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
	1112	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
	1113	s += '#endif\n'
[406]	1114
[319]	1115	return s
	1116
	1117	# end of hard_config()
	1118
[411]	1119	################################################################################
	1120	def linux_dts( self ): # compute string for linux.dts file generation
[424]	1121	# used for linux configuration
[411]	1122	# header
	1123	s = '/dts-v1/;\n'
	1124	s += '\n'
	1125	s += '/{\n'
[421]	1126	s += ' compatible = "tsar,%s";\n' % self.name
[411]	1127	s += ' #address-cells = <2>;\n' # physical address on 64 bits
	1128	s += ' #size-cells = <1>;\n' # segment size on 32 bits
	1129	s += ' model = "%s";\n' % self.name
	1130	s += '\n'
	1131
	1132	# linux globals arguments
	1133	s += ' chosen {\n'
	1134	s += ' linux,stdout-path = &tty;\n'
	1135	s += ' bootargs = "console=tty0 console=ttyVTTY0 earlyprintk";\n'
[424]	1136	s += ' };\n\n'
[411]	1137
	1138	# cpus (for each cluster)
	1139	s += ' cpus {\n'
	1140	s += ' #address-cells = <1>;\n'
	1141	s += ' #size-cells = <0>;\n'
	1142
	1143	for cluster in self.clusters:
	1144	for proc in cluster.procs:
	1145	x = cluster.x
	1146	y = cluster.y
	1147	l = proc.lpid
[421]	1148	proc_id = (((x << self.y_width) + y) << self.p_width) + l
[411]	1149	s += ' cpu@%d_%d_%d {\n' %(x,y,l)
	1150	s += ' device_type = "cpu";\n'
	1151	s += ' compatible = "soclib,mips32el";\n'
	1152	s += ' reg = <0x%x>;\n' % proc_id
	1153	s += ' };\n'
	1154	s += '\n'
	1155
	1156	s += ' };\n\n'
	1157
	1158	# devices (ram or peripheral) are grouped per cluster
[424]	1159	# the "compatible" attribute links a peripheral device
[411]	1160	# to one or several drivers identified by ("major","minor")
	1161
	1162	for cluster in self.clusters:
	1163	x = cluster.x
	1164	y = cluster.y
	1165	found_xcu = False
	1166	found_pic = False
	1167
	1168	s += ' /* cluster[%d,%d] */\n\n' % (x,y)
	1169
	1170	# scan all psegs to find RAM in current cluster
	1171	for pseg in cluster.psegs:
	1172	if ( pseg.segtype == 'RAM' ):
	1173	msb = pseg.base >> 32
	1174	lsb = pseg.base & 0xFFFFFFFF
	1175	size = pseg.size
	1176
[424]	1177	s += ' ram_%d_%d: ram@0x%x {\n' % (x, y, pseg.base)
[411]	1178	s += ' device_type = "memory";\n'
	1179	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1180	s += ' };\n\n'
	1181
	1182	# scan all periphs to find XCU or PIC in current cluster
	1183	for periph in cluster.periphs:
	1184	msb = periph.pseg.base >> 32
	1185	lsb = periph.pseg.base & 0xFFFFFFFF
	1186	size = periph.pseg.size
	1187
	1188	# search XCU (can be replicated)
[424]	1189	if ( (periph.ptype == 'XCU') ):
[411]	1190	found_xcu = True
	1191	xcu = periph
[424]	1192	irq_ctrl_name = 'xcu_%d_%d' % (x, y)
[411]	1193
[424]	1194	s += ' %s: xcu@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
[421]	1195	s += ' compatible = "soclib,vci_xicu","soclib,vci_xicu_timer";\n'
[411]	1196	s += ' interrupt-controller;\n'
	1197	s += ' #interrupt-cells = <1>;\n'
[512]	1198	s += ' clocks = <&freq>;\n' # XCU contains a timer
[424]	1199	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[411]	1200	s += ' };\n\n'
	1201
	1202	# search PIC (non replicated)
[424]	1203	if ( periph.ptype == 'PIC' ):
[411]	1204	found_pic = True
	1205	pic = periph
	1206	irq_ctrl_name = 'pic'
	1207
[424]	1208	s += ' %s: pic@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
[421]	1209	s += ' compatible = "soclib,vci_iopic";\n'
[411]	1210	s += ' interrupt-controller;\n'
	1211	s += ' #interrupt-cells = <1>;\n'
	1212	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1213	s += ' };\n\n'
	1214
	1215	# we need one interrupt controler in any cluster containing peripherals
[512]	1216	if ( (found_xcu == False) and
	1217	(found_pic == False) and
	1218	(len(cluster.periphs) > 0) ):
	1219	print '[genmap error] in linux_dts()'
	1220	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
[424]	1221	sys.exit(1)
[411]	1222
	1223	if ( found_pic == True ): irq_ctrl = pic
	1224	else: irq_ctrl = xcu
[424]	1225
[411]	1226	# scan all periphs to find TTY and IOC in current cluster
	1227	for periph in cluster.periphs:
	1228	msb = periph.pseg.base >> 32
	1229	lsb = periph.pseg.base & 0xFFFFFFFF
	1230	size = periph.pseg.size
	1231
	1232	# search TTY (non replicated)
[424]	1233	if ( periph.ptype == 'TTY' ):
[411]	1234
	1235	# get HWI index to XCU or PIC (only TTY channel 0 is used by Linux)
	1236	hwi_id = 0xFFFFFFFF
	1237	for irq in irq_ctrl.irqs:
[512]	1238	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == 0) ):
	1239	hwi_id = irq.srcid
	1240
[411]	1241	if ( hwi_id == 0xFFFFFFFF ):
[512]	1242	print '[genmap error] in linux.dts()'
	1243	print ' IRQ_TTY_RX not found'
[411]	1244	sys.exit(1)
	1245
[526]	1246	s += ' tty: tty@0x%x {\n' % (periph.pseg.base)
[421]	1247	s += ' compatible = "soclib,vci_multi_tty";\n'
[411]	1248	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
[424]	1249	s += ' interrupts = <%d>;\n' % hwi_id
[411]	1250	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1251	s += ' };\n\n'
	1252
	1253	# search IOC (non replicated)
[424]	1254	elif ( periph.ptype == 'IOC' ):
[411]	1255
	1256	if ( periph.subtype == 'BDV' ):
	1257
	1258	# get irq line index associated to bdv
	1259	hwi_id = 0xFFFFFFFF
	1260	for irq in irq_ctrl.irqs:
	1261	if ( irq.isrtype == 'ISR_BDV' ): hwi_id = irq.srcid
[512]	1262
[411]	1263	if ( hwi_id == 0xFFFFFFFF ):
[512]	1264	print '[genmap error] in linux.dts()'
	1265	print ' ISR_BDV not found'
[411]	1266	sys.exit(1)
	1267
[526]	1268	s += ' bdv: bdv@0x%x {\n' % (periph.pseg.base)
[517]	1269	s += ' compatible = "tsar,vci_block_device";\n'
[411]	1270	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
[424]	1271	s += ' interrupts = <%d>;\n' % hwi_id
[411]	1272	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1273	s += ' };\n\n'
	1274
[526]	1275	else:
	1276	print '[genmap warning] in linux_dts() : %s' % (periph.subtype),
	1277	print 'peripheral not supported by LINUX'
[411]	1278
[465]	1279	# XCU or PIC have been already parsed
	1280	elif ( periph.ptype == 'XCU' ) or ( periph.ptype == 'PIC' ):
	1281	pass
	1282
[411]	1283	# other peripherals
[424]	1284	else:
[512]	1285	print '[genmap warning] in linux_dts()'
	1286	print ' %s peripheral not supported by LINUX' % (periph.ptype)
[424]	1287
	1288	# clocks
[411]	1289	s += ' /* clocks */\n\n'
	1290	s += ' clocks {\n'
[424]	1291	s += ' freq: freq@50MHZ {\n'
[411]	1292	s += ' #clock-cells = <0>;\n'
	1293	s += ' compatible = "fixed-clock";\n'
	1294	s += ' clock-frequency = <50000000>;\n'
	1295	s += ' };\n'
	1296	s += ' };\n\n'
	1297	s += ' cpuclk {\n'
[421]	1298	s += ' compatible = "soclib,mips32_clksrc";\n'
[424]	1299	s += ' clocks = <&freq>;\n'
[411]	1300	s += ' };\n'
	1301	s += '};\n'
	1302
	1303	return s
	1304	# end linux_dts()
	1305
	1306
	1307	#############################################################################
[319]	1308	def netbsd_dts( self ): # compute string for netbsd.dts file generation,
[406]	1309	# used for netbsd configuration
[319]	1310	# header
	1311	s = '/dts-v1/;\n'
	1312	s += '\n'
	1313	s += '/{\n'
[406]	1314	s += ' #address-cells = <2>;\n'
	1315	s += ' #size-cells = <1>;\n'
[319]	1316
	1317	# cpus (for each cluster)
	1318	s += ' cpus {\n'
	1319	s += ' #address-cells = <1>;\n'
	1320	s += ' #size-cells = <0>;\n'
	1321
	1322	for cluster in self.clusters:
	1323	for proc in cluster.procs:
[406]	1324	proc_id = (((cluster.x << self.y_width) + cluster.y) << self.p_width) + proc.lpid
[319]	1325
	1326	s += ' Mips,32@0x%x {\n' % proc_id
	1327	s += ' device_type = "cpu";\n'
	1328	s += ' icudev_type = "cpu:mips";\n'
	1329	s += ' name = "Mips,32";\n'
	1330	s += ' reg = <0x%x>;\n' % proc_id
	1331	s += ' };\n'
	1332	s += '\n'
	1333
	1334	s += ' };\n'
	1335
[411]	1336	# physical memory banks (for each cluster)
[319]	1337	for cluster in self.clusters:
	1338	for pseg in cluster.psegs:
	1339
	1340	if ( pseg.segtype == 'RAM' ):
	1341	msb = pseg.base >> 32
	1342	lsb = pseg.base & 0xFFFFFFFF
	1343	size = pseg.size
	1344
	1345	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
	1346	s += ' cached = <1>;\n'
	1347	s += ' device_type = "memory";\n'
	1348	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1349	s += ' };\n'
	1350
	1351	# peripherals (for each cluster)
	1352	for cluster in self.clusters:
[411]	1353	x = cluster.x
	1354	y = cluster.y
[319]	1355
[406]	1356	# research XCU component
[319]	1357	found_xcu = False
	1358	for periph in cluster.periphs:
[406]	1359	if ( (periph.ptype == 'XCU') ):
[319]	1360	found_xcu = True
	1361	xcu = periph
	1362	msb = periph.pseg.base >> 32
	1363	lsb = periph.pseg.base & 0xFFFFFFFF
	1364	size = periph.pseg.size
	1365
	1366	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1367	s += ' device_type = "soclib:xicu:root";\n'
	1368	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[400]	1369	s += ' input_lines = <%d>;\n' % periph.arg
	1370	s += ' ipis = <%d>;\n' % periph.arg
	1371	s += ' timers = <%d>;\n' % periph.arg
[319]	1372
	1373	output_id = 0 # output index from XCU
	1374	for lpid in xrange ( len(cluster.procs) ): # destination processor index
	1375	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
[406]	1376	cluster_xy = (cluster.x << self.y_width) + cluster.y
	1377	proc_id = (cluster_xy << self.p_width) + lpid
[319]	1378	s += ' out@%d {\n' % output_id
	1379	s += ' device_type = "soclib:xicu:filter";\n'
[411]	1380	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
[406]	1381	s += ' output_line = <%d>;\n' % output_id
[411]	1382	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
[319]	1383	s += ' };\n'
	1384
	1385	output_id += 1
	1386
	1387	s += ' };\n'
	1388
	1389	# research PIC component
	1390	found_pic = False
	1391	for periph in cluster.periphs:
[406]	1392	if ( periph.ptype == 'PIC' ):
[319]	1393	found_pic = True
	1394	pic = periph
	1395	msb = periph.pseg.base >> 32
	1396	lsb = periph.pseg.base & 0xFFFFFFFF
	1397	size = periph.pseg.size
	1398
	1399	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1400	s += ' device_type = "soclib:pic:root";\n'
	1401	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[406]	1402	s += ' input_lines = <%d>;\n' % periph.channels
[319]	1403	s += ' };\n'
	1404
[411]	1405	# at least one interrupt controller
[319]	1406	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
[512]	1407	print '[genmap error] in netbsd_dts()'
	1408	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
[406]	1409	sys.exit(1)
	1410
[319]	1411	if ( found_pic == True ): irq_tgt = pic
	1412	else: irq_tgt = xcu
[406]	1413
[319]	1414	# get all others peripherals in cluster
	1415	for periph in cluster.periphs:
	1416	msb = periph.pseg.base >> 32
	1417	lsb = periph.pseg.base & 0xFFFFFFFF
	1418	size = periph.pseg.size
	1419
	1420	# research DMA component
	1421	if ( periph.ptype == 'DMA' ):
	1422
	1423	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
[411]	1424	s += ' device_type = "soclib:dma";\n'
	1425	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1426	s += ' channel_count = <%d>;\n' % periph.channels
	1427
	1428	# multi-channels : get HWI index (to XCU) for each channel
	1429	for channel in xrange( periph.channels ):
	1430	hwi_id = 0xFFFFFFFF
	1431	for irq in xcu.irqs:
[406]	1432	if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ):
[319]	1433	hwi_id = irq.srcid
[512]	1434
[319]	1435	if ( hwi_id == 0xFFFFFFFF ):
[512]	1436	print '[genmap error] in netbsd.dts()'
	1437	print ' ISR_DMA channel %d not found' % channel
[319]	1438	sys.exit(1)
	1439
	1440	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
	1441	s += ' irq@%d{\n' % channel
	1442	s += ' device_type = "soclib:periph:irq";\n'
	1443	s += ' output_line = <%d>;\n' % channel
[411]	1444	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1445	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
[319]	1446	s += ' };\n'
	1447
[406]	1448	s += ' };\n'
[319]	1449
	1450	# research MMC component
	1451	elif ( periph.ptype == 'MMC' ):
	1452
	1453	# get irq line index associated to MMC in XCU
	1454	irq_in = 0xFFFFFFFF
	1455	for irq in xcu.irqs:
	1456	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
[512]	1457
[319]	1458	if ( irq_in == 0xFFFFFFFF ):
[512]	1459	print '[genmap error] in netbsd.dts()'
	1460	print ' ISR_MMC not found'
[319]	1461	sys.exit(1)
	1462
	1463	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1464	s += ' device_type = "soclib:mmc";\n'
[411]	1465	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1466	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[406]	1467	s += ' };\n'
[319]	1468
	1469	# research FBF component
[406]	1470	elif ( periph.ptype == 'FBF' ):
[319]	1471
[411]	1472	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
[319]	1473	s += ' device_type = "soclib:framebuffer";\n'
	1474	s += ' mode = <32>;\n' # bits par pixel
[400]	1475	s += ' width = <%d>;\n' % periph.arg
	1476	s += ' height = <%d>;\n' % periph.arg
[319]	1477	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1478	s += ' };\n'
	1479
	1480	# research IOC component
[406]	1481	elif ( periph.ptype == 'IOC' ):
[319]	1482
	1483	if ( periph.subtype == 'BDV' ):
	1484
	1485	# get irq line index associated to bdv
	1486	irq_in = 0xFFFFFFFF
	1487	for irq in irq_tgt.irqs:
	1488	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
	1489	if ( irq_in == 0xFFFFFFFF ):
[512]	1490	print '[genmap error] in netbsd.dts()'
	1491	print ' ISR_BDV not found'
[319]	1492	sys.exit(1)
	1493
[411]	1494	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
[319]	1495	s += ' device_type = "soclib:blockdevice";\n'
[411]	1496	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
	1497	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1498	s += ' };\n'
	1499
	1500	elif ( periph.subtype == 'HBA' ):
[512]	1501	print '[genmap error] in netbsd_dts()'
	1502	print ' HBA peripheral not supported by NetBSD'
[319]	1503	sys.exit(1)
	1504
	1505	elif ( periph.subtype == 'SPI' ):
	1506
	1507	# get irq line index associated to spi
	1508	irq_in = 0xFFFFFFFF
	1509	for irq in irq_tgt.irqs:
	1510	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
	1511	if ( irq_in == 0xFFFFFFFF ):
[512]	1512	print '[genmap error] in netbsd.dts()'
	1513	print ' ISR_SPI not found'
[319]	1514	sys.exit(1)
	1515
	1516	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1517	s += ' device_type = "soclib:spi";\n'
[411]	1518	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
	1519	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1520	s += ' };\n'
	1521
	1522	# research ROM component
	1523	elif ( periph.ptype == 'ROM' ):
	1524
[411]	1525	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
[319]	1526	s += ' device_type = "rom";\n'
[411]	1527	s += ' cached = <1>;\n'
	1528	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1529	s += ' };\n'
	1530
	1531	# research SIM component
	1532	elif ( periph.ptype == 'SIM' ):
	1533
	1534	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1535	s += ' device_type = "soclib:simhelper";\n'
	1536	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1537	s += ' };\n'
	1538
	1539	# research TTY component
	1540	elif ( periph.ptype == 'TTY' ):
	1541
[411]	1542	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1543	s += ' device_type = "soclib:tty";\n'
[406]	1544	s += ' channel_count = < %d >;\n' % periph.channels
[411]	1545	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[319]	1546
	1547	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1548	for channel in xrange( periph.channels ):
	1549	hwi_id = 0xFFFFFFFF
	1550	for irq in irq_tgt.irqs:
[406]	1551	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
[319]	1552	hwi_id = irq.srcid
	1553	if ( hwi_id == 0xFFFFFFFF ):
[512]	1554	print '[genmap error] in netbsd.dts()'
	1555	print ' ISR_TTY_RX channel %d not found' % channel
[319]	1556	sys.exit(1)
	1557
	1558	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1559	s += ' irq@%d{\n' % channel
	1560	s += ' device_type = "soclib:periph:irq";\n'
	1561	s += ' output_line = <%d>;\n' % channel
[411]	1562	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1563	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
[319]	1564	s += ' };\n'
	1565
	1566	s += ' };\n'
[406]	1567
[319]	1568	# research IOB component
	1569	elif ( periph.ptype == 'IOB' ):
	1570
	1571	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1572	s += ' device_type = "soclib:iob";\n'
	1573	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1574	s += ' };\n'
	1575
	1576	# research NIC component
[406]	1577	elif ( periph.ptype == 'NIC' ):
[319]	1578
	1579	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1580	s += ' device_type = "soclib:nic";\n'
	1581	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1582	s += ' channel_count = < %d >;\n' % periph.channels
	1583
	1584	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
	1585	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
	1586	for channel in xrange( periph.channels ):
	1587	hwi_id = 0xFFFFFFFF
	1588	for irq in irq_tgt.irqs:
[406]	1589	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
[319]	1590	hwi_id = irq.srcid
	1591	if ( hwi_id == 0xFFFFFFFF ):
[512]	1592	print '[genmap error] in netbsd.dts()'
	1593	print ' ISR_NIC_RX channel %d not found' % channel
[319]	1594	sys.exit(1)
	1595
	1596	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1597	s += ' irq_rx@%d{\n' % channel
	1598	s += ' device_type = "soclib:periph:irq";\n'
	1599	s += ' output_line = <%d>;\n' % (2*channel)
	1600	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1601	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1602	s += ' };\n'
	1603
	1604	hwi_id = 0xFFFFFFFF
	1605	for irq in irq_tgt.irqs:
[406]	1606	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
[319]	1607	hwi_id = irq.srcid
	1608	if ( hwi_id == 0xFFFFFFFF ):
[512]	1609	print '[genmap error] in netbsd.dts()'
	1610	print ' ISR_NIC_TX channel %d not found' % channel
[319]	1611	sys.exit(1)
	1612
	1613	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1614	s += ' irq_tx@%d{\n' % channel
	1615	s += ' device_type = "soclib:periph:irq";\n'
	1616	s += ' output_line = <%d>;\n' % (2*channel + 1)
	1617	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1618	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1619	s += ' };\n'
[406]	1620
[319]	1621	s += ' };\n'
	1622
	1623	# research CMA component
[406]	1624	elif ( periph.ptype == 'CMA' ):
[319]	1625
	1626	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1627	s += ' device_type = "soclib:cma";\n'
	1628	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1629	s += ' channel_count = < %d >;\n' % periph.channels
	1630
	1631	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1632	for channel in xrange( periph.channels ):
	1633	hwi_id = 0xFFFFFFFF
	1634	for irq in irq_tgt.irqs:
[406]	1635	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
[319]	1636	hwi_id = irq.srcid
[512]	1637
[319]	1638	if ( hwi_id == 0xFFFFFFFF ):
[512]	1639	print '[genmap error] in netbsd.dts()'
	1640	print ' ISR_CMA channel %d not found' % channel
[319]	1641	sys.exit(1)
	1642
	1643	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1644	s += ' irq@%d{\n' % channel
	1645	s += ' device_type = "soclib:periph:irq";\n'
	1646	s += ' output_line = <%d>;\n' % channel
[411]	1647	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1648	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
[319]	1649	s += ' };\n'
	1650
	1651	s += ' };\n'
	1652
	1653	# research TIM component
[406]	1654	elif ( periph.ptype == 'TIM' ):
[319]	1655
[512]	1656	print '[genmap error] in netbsd_dts()'
	1657	print ' TIM peripheral not supported by NetBSD'
[319]	1658	sys.exit(1)
	1659
	1660	# research MWR component
	1661	elif ( periph.ptype == 'MWR' ):
	1662
[512]	1663	print '[genmap error] in netbsd_dts()'
	1664	print ' MWR peripheral not supported by NetBSD'
[319]	1665	sys.exit(1)
	1666
	1667	# topology
	1668	s += '\n'
	1669	s += ' topology {\n'
	1670	s += ' #address-cells = <2>;\n'
	1671	s += ' #size-cells = <0>;\n'
	1672	for cluster in self.clusters:
[406]	1673	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
[319]	1674	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
	1675	s += ' devices = <\n'
	1676
[406]	1677	offset = ((cluster.x << self.y_width) + cluster.y) << self.p_width
[319]	1678	for proc in cluster.procs:
	1679	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
	1680	for periph in cluster.periphs:
	1681	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
[492]	1682	for pseg in cluster.psegs:
	1683	if ( pseg.segtype == 'RAM' ):
	1684	s += ' &{/%s@0x%x}\n' % (pseg.name, pseg.base)
[319]	1685
	1686	s += ' >;\n'
	1687	s += ' };\n'
	1688	s += ' };\n'
	1689	s += '};\n'
	1690
	1691	return s
[411]	1692	# end netbsd_dts()
[319]	1693
	1694	###########################
	1695	def almos_archinfo( self ): # compute string for arch.info file generation,
[406]	1696	# used for almos configuration
[319]	1697	# header
[327]	1698	s = '# arch.info file generated by genmap for %s\n' % self.name
[319]	1699	s += '\n'
	1700	s += '[HEADER]\n'
	1701	s += ' REVISION=1\n'
	1702	s += ' ARCH=%s\n' % self.name
	1703	s += ' XMAX=%d\n' % self.x_size
	1704	s += ' YMAX=%d\n' % self.y_size
[411]	1705	s += ' CPU_NR=%d\n' % self.nprocs
[319]	1706	s += '\n'
	1707
	1708	# clusters
	1709	cluster_id = 0
	1710	for cluster in self.clusters:
	1711
	1712	ram = None
	1713	nb_cpus = len( cluster.procs )
	1714	nb_devs = len( cluster.periphs )
	1715
	1716	# search a RAM
	1717	for pseg in cluster.psegs:
[406]	1718	if ( pseg.segtype == 'RAM' ):
[319]	1719	ram = pseg
	1720	nb_devs += 1
	1721
	1722	# search XCU to get IRQs indexes if cluster contains peripherals
	1723	if ( len( cluster.periphs ) != 0 ):
	1724	tty_irq_id = None
	1725	bdv_irq_id = None
	1726	dma_irq_id = None
	1727
	1728	for periph in cluster.periphs:
[406]	1729	if ( periph.ptype == 'XCU' ):
[319]	1730	# scan irqs
	1731	for irq in periph.irqs:
	1732	if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid
	1733	if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid
	1734	if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid
	1735
	1736	# Build the cluster description
	1737	s += '[CLUSTER]\n'
[406]	1738	s += ' CID=%d\n' % cluster_id
	1739	s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y)
[319]	1740	s += ' CPU_NR=%d\n' % nb_cpus
	1741	s += ' DEV_NR=%d\n' % nb_devs
	1742
[406]	1743
[319]	1744	# Handling RAM when cluster contain a RAM
	1745	if (ram != None ):
	1746	base = ram.base
	1747	size = ram.size
	1748	irqid = -1
[406]	1749	s += ' DEVID=RAM'
[319]	1750	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1751
	1752	# Handling peripherals
	1753	for periph in cluster.periphs:
	1754	base = periph.pseg.base
	1755	size = periph.pseg.size
	1756
[406]	1757	if ( periph.ptype == 'XCU' ):
[319]	1758
[406]	1759	s += ' DEVID=XICU'
[319]	1760	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1761
[406]	1762	elif ( (periph.ptype == 'TTY')
[319]	1763	and (tty_irq_id != None) ):
	1764
[406]	1765	s += ' DEVID=TTY'
[319]	1766	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id )
	1767
[406]	1768	elif ( (periph.ptype == 'DMA')
[319]	1769	and (dma_irq_id != None) ):
	1770
	1771	s += ' DEVID=DMA'
	1772	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id )
	1773
	1774	elif ( periph.ptype == 'FBF' ):
	1775
	1776	s += ' DEVID=FB'
	1777	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1778
	1779	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
	1780	and (bdv_irq_id != None) ):
	1781
[406]	1782	s += ' DEVID=BLKDEV'
[319]	1783	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id )
	1784
	1785	elif ( periph.ptype == 'PIC' ):
	1786
[406]	1787	s += ' DEVID=IOPIC'
[319]	1788	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1789
	1790	else:
	1791	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
	1792	% (cluster.x, cluster.y)
	1793	print '# peripheral type %s/%s not supported yet\n' \
	1794	% ( periph.ptype, periph.subtype )
[406]	1795
[319]	1796	cluster_id += 1
	1797
	1798	return s
	1799
	1800	# end of almos_archinfo()
	1801
	1802
	1803
	1804
	1805
	1806
	1807
	1808
	1809	###########################################################################################
	1810	class Cluster ( object ):
	1811	###########################################################################################
	1812	def __init__( self,
[406]	1813	x,
[319]	1814	y ):
[406]	1815
[319]	1816	self.index = 0 # global index (set by Mapping constructor)
	1817	self.x = x # x coordinate
	1818	self.y = y # y coordinate
	1819	self.psegs = [] # filled by addRam() or addPeriph()
	1820	self.procs = [] # filled by addProc()
	1821	self.periphs = [] # filled by addPeriph()
	1822
	1823	return
	1824
	1825	################
	1826	def xml( self ): # xml for a cluster
	1827
	1828	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
[406]	1829	for pseg in self.psegs: s += pseg.xml()
[319]	1830	for proc in self.procs: s += proc.xml()
[406]	1831	for peri in self.periphs: s += peri.xml()
[319]	1832	s += ' </cluster>\n'
	1833
	1834	return s
	1835
	1836	#############################################
	1837	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
	1838
	1839	if ( verbose ):
	1840	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
	1841
	1842	# check index
	1843	if (self.index != expected):
[512]	1844	print '[genmap error] in Cluster.cbin()'
	1845	print ' cluster global index = %d / expected = %d' % (self.index,expected)
[319]	1846	sys.exit(1)
	1847
[406]	1848	# compute global index for first pseg
[319]	1849	if ( len(self.psegs) > 0 ):
	1850	pseg_id = self.psegs[0].index
	1851	else:
	1852	pseg_id = 0
	1853
[406]	1854	# compute global index for first proc
[319]	1855	if ( len(self.procs) > 0 ):
	1856	proc_id = self.procs[0].index
	1857	else:
	1858	proc_id = 0
	1859
[406]	1860	# compute global index for first periph
[319]	1861	if ( len(self.periphs) > 0 ):
	1862	periph_id = self.periphs[0].index
	1863	else:
	1864	periph_id = 0
	1865
	1866	byte_stream = bytearray()
[512]	1867	byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate
	1868	byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate
	1869	byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number psegs in cluster
	1870	byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index
	1871	byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number procs in cluster
	1872	byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index
	1873	byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number periphs in cluster
	1874	byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index
[406]	1875
[319]	1876	if ( verbose ):
	1877	print 'nb_psegs = %d' % len( self.psegs )
	1878	print 'pseg_id = %d' % pseg_id
	1879	print 'nb_procs = %d' % len( self.procs )
	1880	print 'proc_id = %d' % proc_id
	1881	print 'nb_periphs = %d' % len( self.periphs )
	1882	print 'periph_id = %d' % periph_id
	1883
	1884	return byte_stream
	1885
[512]	1886	########################################################################################
[305]	1887	class Vspace( object ):
[512]	1888	########################################################################################
[406]	1889	def __init__( self,
	1890	name,
[319]	1891	startname ):
	1892
	1893	self.index = 0 # global index ( set by addVspace() )
	1894	self.name = name # vspace name
[512]	1895	self.startname = startname # name of vseg containing the start_vector
[406]	1896	self.vsegs = []
[305]	1897	self.tasks = []
	1898
	1899	return
	1900
[319]	1901	################
	1902	def xml( self ): # xml for one vspace
	1903
[305]	1904	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
[319]	1905	for vseg in self.vsegs: s += vseg.xml()
[406]	1906	for task in self.tasks: s += task.xml()
[305]	1907	s += ' </vspace>\n'
[319]	1908
[305]	1909	return s
	1910
[319]	1911	#############################################
	1912	def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace
	1913
	1914	if ( verbose ):
	1915	print '*** cbin for vspace %s' % (self.name)
	1916
	1917	# check index
	1918	if (self.index != expected):
[512]	1919	print '[genmap error] in Vspace.cbin()'
	1920	print ' vspace global index = %d / expected = %d' %(self.index,expected)
[319]	1921	sys.exit(1)
	1922
[512]	1923	# compute global index for vseg containing start_vector
	1924	vseg_start_id = 0xFFFFFFFF
[319]	1925	for vseg in self.vsegs:
[512]	1926	if ( vseg.name == self.startname ): vseg_start_id = vseg.index
	1927
	1928	if ( vseg_start_id == 0xFFFFFFFF ):
	1929	print '[genmap error] in Vspace.cbin()'
	1930	print ' startname %s not found for vspace %s' %(self.startname,self.name)
[319]	1931	sys.exit(1)
[406]	1932
[512]	1933	# compute first vseg and first task global index
[319]	1934	first_vseg_id = self.vsegs[0].index
	1935	first_task_id = self.tasks[0].index
[406]	1936
[512]	1937	# compute number of tasks and number of vsegs
[319]	1938	nb_vsegs = len( self.vsegs )
	1939	nb_tasks = len( self.tasks )
	1940
	1941	byte_stream = bytearray()
	1942	byte_stream += mapping.str2bytes( 32, self.name ) # vspace name
[512]	1943	byte_stream += mapping.int2bytes( 4, vseg_start_id ) # vseg start_vector
[319]	1944	byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs
	1945	byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks
	1946	byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index
	1947	byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index
	1948
	1949	if ( verbose ):
[512]	1950	print 'start_id = %d' % vseg_start_id
[319]	1951	print 'nb_vsegs = %d' % nb_vsegs
	1952	print 'nb_tasks = %d' % nb_tasks
	1953	print 'vseg_id = %d' % first_vseg_id
	1954	print 'task_id = %d' % first_task_id
	1955
	1956	return byte_stream
	1957
[512]	1958	########################################################################################
[305]	1959	class Task( object ):
[512]	1960	########################################################################################
[406]	1961	def __init__( self,
	1962	name,
	1963	trdid,
	1964	x,
[319]	1965	y,
[406]	1966	p,
	1967	stackname,
	1968	heapname,
[441]	1969	startid ):
[319]	1970
	1971	self.index = 0 # global index value set by addTask()
	1972	self.name = name # tsk name
	1973	self.trdid = trdid # task index (unique in vspace)
[406]	1974	self.x = x # cluster x coordinate
	1975	self.y = y # cluster y coordinate
	1976	self.p = p # processor local index
[512]	1977	self.stackname = stackname # name of vseg containing the stack
	1978	self.heapname = heapname # name of vseg containing the heap
[319]	1979	self.startid = startid # index in start_vector
[305]	1980	return
	1981
[319]	1982	################
	1983	def xml( self ): # xml for one task
	1984
	1985	s = ' <task name="%s"' % self.name
	1986	s += ' trdid="%d"' % self.trdid
	1987	s += ' x="%d"' % self.x
	1988	s += ' y="%d"' % self.y
	1989	s += ' p="%d"' % self.p
[512]	1990	s += '\n '
[319]	1991	s += ' stackname="%s"' % self.stackname
	1992	s += ' heapname="%s"' % self.heapname
	1993	s += ' startid="%d"' % self.startid
[406]	1994	s += ' />\n'
[319]	1995
[305]	1996	return s
	1997
[319]	1998	#####################################################
[406]	1999	def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task
[319]	2000
	2001	if ( verbose ):
	2002	print '*** cbin for task %s in vspace %s' % (self.name, vspace.name)
	2003
	2004	# check index
	2005	if (self.index != expected):
[512]	2006	print '[genmap error] in Task.cbin()'
	2007	print ' task global index = %d / expected = %d' %(self.index,expected)
[319]	2008	sys.exit(1)
	2009
	2010	# compute cluster global index
	2011	cluster_id = (self.x * mapping.y_size) + self.y
	2012
[512]	2013	# compute vseg index for stack
	2014	vseg_stack_id = 0xFFFFFFFF
[319]	2015	for vseg in vspace.vsegs:
[512]	2016	if ( vseg.name == self.stackname ): vseg_stack_id = vseg.index
	2017
	2018	if ( vseg_stack_id == 0xFFFFFFFF ):
	2019	print '[genmap error] in Task.cbin()'
	2020	print ' stackname %s not found for task %s in vspace %s' \
[319]	2021	% ( self.stackname, self.name, vspace.name )
	2022	sys.exit(1)
	2023
[512]	2024	# compute vseg index for heap
[453]	2025	if ( self.heapname == '' ):
[512]	2026	vseg_heap_id = 0
[453]	2027	else:
[512]	2028	vseg_heap_id = 0xFFFFFFFF
[453]	2029	for vseg in vspace.vsegs:
[512]	2030	if ( vseg.name == self.heapname ): vseg_heap_id = vseg.index
	2031
	2032	if ( vseg_heap_id == 0xFFFFFFFF ):
	2033	print '[genmap error] in Task.cbin()'
	2034	print ' heapname %s not found for task %s in vspace %s' \
[453]	2035	% ( self.heapname, self.name, vspace.name )
	2036	sys.exit(1)
[319]	2037
	2038	byte_stream = bytearray()
	2039	byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace
	2040	byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index
[512]	2041	byte_stream += mapping.int2bytes( 4, self.p ) # processor local index
[319]	2042	byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace
[512]	2043	byte_stream += mapping.int2bytes( 4, vseg_stack_id ) # stack vseg local index
	2044	byte_stream += mapping.int2bytes( 4, vseg_heap_id ) # heap vseg local index
[406]	2045	byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector
[319]	2046
	2047	if ( verbose ):
	2048	print 'clusterid = %d' % cluster_id
	2049	print 'lpid = %d' % self.p
[406]	2050	print 'trdid = %d' % self.trdid
[512]	2051	print 'stackid = %d' % vseg_stack_id
	2052	print 'heapid = %d' % vseg_heap_id
[406]	2053	print 'startid = %d' % self.startid
	2054
[319]	2055	return byte_stream
	2056
[512]	2057	########################################################################################
[305]	2058	class Vseg( object ):
[512]	2059	########################################################################################
[406]	2060	def __init__( self,
	2061	name,
	2062	vbase,
[512]	2063	length,
[406]	2064	mode,
[512]	2065	vtype,
[406]	2066	x,
	2067	y,
[512]	2068	pseg,
[348]	2069	identity = False,
[411]	2070	local = False,
[512]	2071	big = False,
	2072	binpath = '' ):
[305]	2073
[512]	2074	assert (vbase & 0xFFFFFFFF) == vbase
	2075
	2076	assert (length & 0xFFFFFFFF) == length
	2077
[319]	2078	assert mode in VSEGMODES
	2079
[512]	2080	assert vtype in VSEGTYPES
	2081
	2082	assert (vtype != 'ELF') or (binpath != '')
	2083
[348]	2084	self.index = 0 # global index ( set by addVseg() )
[512]	2085	self.name = name # vseg name (unique in vspace)
	2086	self.vbase = vbase # virtual base address in vspace
	2087	self.length = length # vseg length (bytes)
	2088	self.vtype = vtype # vseg type (defined in VSEGTYPES)
[348]	2089	self.mode = mode # CXWU access rights
[406]	2090	self.x = x # x coordinate of destination cluster
[348]	2091	self.y = y # y coordinate of destination cluster
[512]	2092	self.psegname = pseg # name of pseg in destination cluster
[348]	2093	self.identity = identity # identity mapping required
[411]	2094	self.local = local # only mapped in local PTAB when true
	2095	self.big = big # to be mapped in a big physical page
[512]	2096	self.binpath = binpath # path name for binary file (ELF or BLOB)
	2097
[305]	2098	return
	2099
[319]	2100	################
[406]	2101	def xml( self ): # xml for one vseg
[319]	2102
[512]	2103	s = ' <vseg name="%s"' %(self.name)
	2104	s += ' vbase="0x%x"' %(self.vbase)
	2105	s += ' length="0x%x"' %(self.length)
	2106	s += ' type="%s"' %(self.vtype)
	2107	s += ' mode="%s"' %(self.mode)
	2108	s += '\n '
	2109	s += ' x="%d"' %(self.x)
	2110	s += ' y="%d"' %(self.y)
	2111	s += ' psegname="%s"' %(self.psegname)
	2112	if ( self.identity ): s += ' ident="1"'
	2113	if ( self.local ): s += ' local="1"'
	2114	if ( self.big ): s += ' big="1"'
	2115	if ( self.binpath != '' ): s += ' binpath="%s"' %(self.binpath)
	2116	s += ' />\n'
[319]	2117
[305]	2118	return s
	2119
[319]	2120	#############################################
	2121	def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg
	2122
	2123	if ( verbose ):
	2124	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
	2125
	2126	# check index
	2127	if (self.index != expected):
[512]	2128	print '[genmap error] in Vseg.cbin()'
	2129	print ' vseg global index = %d / expected = %d' \
[319]	2130	% (self.index, expected )
	2131	sys.exit(1)
	2132
	2133	# compute pseg_id
	2134	pseg_id = 0xFFFFFFFF
	2135	cluster_id = (self.x * mapping.y_size) + self.y
	2136	cluster = mapping.clusters[cluster_id]
	2137	for pseg in cluster.psegs:
	2138	if (self.psegname == pseg.name):
	2139	pseg_id = pseg.index
	2140	if (pseg_id == 0xFFFFFFFF):
[512]	2141	print '[genmap error] in Vseg.cbin() : '
	2142	print ' psegname %s not found for vseg %s in cluster %d' \
[319]	2143	% ( self.psegname, self.name, cluster_id )
	2144	sys.exit(1)
	2145
	2146	# compute numerical value for mode
	2147	mode_id = 0xFFFFFFFF
[406]	2148	for x in xrange( len(VSEGMODES) ):
	2149	if ( self.mode == VSEGMODES[x] ):
[319]	2150	mode_id = x
	2151	if ( mode_id == 0xFFFFFFFF ):
[512]	2152	print '[genmap error] in Vseg.cbin() : '
	2153	print ' undefined vseg mode %s' % self.mode
[319]	2154	sys.exit(1)
	2155
[512]	2156	# compute numerical value for vtype
	2157	vtype_id = 0xFFFFFFFF
	2158	for x in xrange( len(VSEGTYPES) ):
	2159	if ( self.vtype == VSEGTYPES[x] ):
	2160	vtype_id = x
	2161	if ( vtype_id == 0xFFFFFFFF ):
	2162	print '[genmap error] in Vseg.cbin()'
	2163	print ' undefined vseg type %s' % self.vtype
	2164	sys.exit(1)
[319]	2165
	2166	byte_stream = bytearray()
[406]	2167	byte_stream += mapping.str2bytes( 32, self.name ) # vseg name
[512]	2168	byte_stream += mapping.str2bytes( 64, self.binpath ) # binpath
[319]	2169	byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address
	2170	byte_stream += mapping.int2bytes( 8, 0 ) # physical base address
[512]	2171	byte_stream += mapping.int2bytes( 4, self.length ) # vseg size (bytes)
	2172	byte_stream += mapping.int2bytes( 4, pseg_id ) # pseg global index
[319]	2173	byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags
[512]	2174	byte_stream += mapping.int2bytes( 4, vtype_id ) # vseg type
[319]	2175	byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero
[512]	2176	byte_stream += mapping.int2bytes( 1, self.identity ) # identity mapping
[411]	2177	byte_stream += mapping.int2bytes( 1, self.local ) # only mapped in local PTAB
[512]	2178	byte_stream += mapping.int2bytes( 1, self.big ) # to be mapped in BPP
[319]	2179
	2180	if ( verbose ):
[512]	2181	print 'binpath = %s' % self.binpath
[319]	2182	print 'vbase = %x' % self.vbase
[512]	2183	print 'pbase = 0'
	2184	print 'length = %x' % self.length
[319]	2185	print 'pseg_id = %d' % pseg_id
[512]	2186	print 'mode = %d' % mode_id
	2187	print 'type = %d' % vtype_id
	2188	print 'mapped = 0'
	2189	print 'ident = %d' % self.identity
	2190	print 'local = %d' % self.local
	2191	print 'big = %d' % self.big
[406]	2192
[319]	2193	return byte_stream
	2194
[512]	2195	######################################################################################
[305]	2196	class Processor ( object ):
[512]	2197	######################################################################################
[319]	2198	def __init__( self,
[406]	2199	x,
	2200	y,
[319]	2201	lpid ):
	2202
	2203	self.index = 0 # global index ( set by addProc() )
	2204	self.x = x # x cluster coordinate
	2205	self.y = y # y cluster coordinate
	2206	self.lpid = lpid # processor local index
	2207
[305]	2208	return
	2209
[319]	2210	################
[406]	2211	def xml( self ): # xml for a processor
[305]	2212	return ' <proc index="%d" />\n' % (self.lpid)
	2213
[319]	2214	#############################################
	2215	def cbin( self, mapping, verbose, expected ): # C binary structure for Proc
	2216
	2217	if ( verbose ):
	2218	print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y)
	2219
	2220	# check index
	2221	if (self.index != expected):
[512]	2222	print '[genmap error] in Proc.cbin()'
	2223	print ' proc global index = %d / expected = %d' % (self.index,expected)
[319]	2224	sys.exit(1)
	2225
	2226	byte_stream = bytearray()
	2227	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
[406]	2228
[319]	2229	return byte_stream
	2230
[512]	2231	######################################################################################
[305]	2232	class Pseg ( object ):
[512]	2233	######################################################################################
[406]	2234	def __init__( self,
	2235	name,
	2236	base,
	2237	size,
[319]	2238	x,
	2239	y,
	2240	segtype ):
	2241
	2242	assert( segtype in PSEGTYPES )
	2243
	2244	self.index = 0 # global index ( set by addPseg() )
	2245	self.name = name # pseg name (unique in cluster)
	2246	self.base = base # physical base address
	2247	self.size = size # segment size (bytes)
[406]	2248	self.x = x # cluster x coordinate
	2249	self.y = y # cluster y coordinate
[319]	2250	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
	2251
[305]	2252	return
[406]	2253
[319]	2254	################
	2255	def xml( self ): # xml for a pseg
	2256
[305]	2257	return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
	2258	% (self.name, self.segtype, self.base, self.size)
	2259
[319]	2260	######################################################
	2261	def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg
	2262
	2263	if ( verbose ):
	2264	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
	2265	% (self.index, self.name, cluster.x, cluster.y)
	2266
	2267	# check index
	2268	if (self.index != expected):
[512]	2269	print '[genmap error] in Pseg.cbin()'
	2270	print ' pseg global index = %d / expected = %d' % (self.index,expected)
[319]	2271	sys.exit(1)
[406]	2272
[319]	2273	# compute numerical value for segtype
	2274	segtype_int = 0xFFFFFFFF
[406]	2275	for x in xrange( len(PSEGTYPES) ):
[512]	2276	if ( self.segtype == PSEGTYPES[x] ): segtype_int = x
	2277
[319]	2278	if ( segtype_int == 0xFFFFFFFF ):
[512]	2279	print '[genmap error] in Pseg.cbin()'
	2280	print ' undefined segment type %s' % self.segtype
[319]	2281	sys.exit(1)
	2282
	2283	byte_stream = bytearray()
[406]	2284	byte_stream += mapping.str2bytes( 32, self.name ) # pseg name
[319]	2285	byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address
	2286	byte_stream += mapping.int2bytes( 8 , self.size ) # segment length
	2287	byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type
	2288	byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index
[406]	2289	byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs
[319]	2290
	2291	if ( verbose ):
	2292	print 'pbase = %x' % self.base
	2293	print 'size = %x' % self.size
	2294	print 'type = %s' % self.segtype
[406]	2295
[319]	2296	return byte_stream
	2297
[512]	2298	######################################################################################
[319]	2299	class Periph ( object ):
[512]	2300	######################################################################################
[406]	2301	def __init__( self,
[319]	2302	pseg, # associated pseg
	2303	ptype, # peripheral type
	2304	subtype = 'NONE', # peripheral subtype
	2305	channels = 1, # for multi-channels peripherals
[520]	2306	arg0 = 0, # optional argument (semantic depends on ptype)
	2307	arg1 = 0, # optional argument (semantic depends on ptype)
	2308	arg2 = 0, # optional argument (semantic depends on ptype)
	2309	arg3 = 0 ): # optional argument (semantic depends on ptype)
[319]	2310
	2311	self.index = 0 # global index ( set by addPeriph() )
[406]	2312	self.channels = channels
	2313	self.ptype = ptype
	2314	self.subtype = subtype
[520]	2315	self.arg0 = arg0
	2316	self.arg1 = arg1
	2317	self.arg2 = arg2
	2318	self.arg3 = arg3
[319]	2319	self.pseg = pseg
	2320	self.irqs = []
[305]	2321	return
	2322
[319]	2323	################
	2324	def xml( self ): # xml for a periph
	2325
	2326	s = ' <periph type="%s"' % self.ptype
	2327	s += ' subtype="%s"' % self.subtype
	2328	s += ' psegname="%s"' % self.pseg.name
	2329	s += ' channels="%d"' % self.channels
[520]	2330	s += ' arg0="%d"' % self.arg0
	2331	s += ' arg1="%d"' % self.arg1
	2332	s += ' arg2="%d"' % self.arg2
	2333	s += ' arg3="%d"' % self.arg3
[441]	2334	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') ):
[520]	2335	s += ' >\n'
[319]	2336	for irq in self.irqs: s += irq.xml()
[520]	2337	s += ' </periph>\n'
	2338	else:
	2339	s += ' />\n'
[305]	2340	return s
	2341
[319]	2342	#############################################
	2343	def cbin( self, mapping, verbose, expected ): # C binary structure for Periph
[305]	2344
[319]	2345	if ( verbose ):
	2346	print '*** cbin for periph %s in cluster [%d,%d]' \
	2347	% (self.ptype, self.pseg.x, self.pseg.y)
[305]	2348
[319]	2349	# check index
	2350	if (self.index != expected):
[512]	2351	print '[genmap error] in Periph.cbin()'
	2352	print ' periph global index = %d / expected = %d' % (self.index,expected)
[319]	2353	sys.exit(1)
[305]	2354
[319]	2355	# compute pseg global index
	2356	pseg_id = self.pseg.index
[305]	2357
[319]	2358	# compute first irq global index
	2359	if ( len(self.irqs) > 0 ):
	2360	irq_id = self.irqs[0].index
	2361	else:
	2362	irq_id = 0
[305]	2363
[319]	2364	# compute numerical value for ptype
	2365	ptype_id = 0xFFFFFFFF
[406]	2366	for x in xrange( len(PERIPHTYPES) ):
[319]	2367	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
[512]	2368
[319]	2369	if ( ptype_id == 0xFFFFFFFF ):
[512]	2370	print '[genmap error] in Periph.cbin()'
	2371	print ' undefined peripheral type %s' % self.ptype
[319]	2372	sys.exit(1)
[305]	2373
[319]	2374	# compute numerical value for subtype
	2375	subtype_id = 0xFFFFFFFF
[520]	2376	if (self.ptype == 'IOC'):
	2377	for x in xrange( len(IOCSUBTYPES) ):
	2378	if ( self.subtype == IOCSUBTYPES[x] ): subtype_id = x
	2379	if (self.ptype == 'MWR'):
	2380	for x in xrange( len(MWRSUBTYPES) ):
	2381	if ( self.subtype == MWRSUBTYPES[x] ): subtype_id = x
	2382
[319]	2383	byte_stream = bytearray()
[406]	2384	byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type
[319]	2385	byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype
[406]	2386	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
[319]	2387	byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels
[520]	2388	byte_stream += mapping.int2bytes( 4 , self.arg0 ) # optionnal arg0
	2389	byte_stream += mapping.int2bytes( 4 , self.arg1 ) # optionnal arg1
	2390	byte_stream += mapping.int2bytes( 4 , self.arg2 ) # optionnal arg2
	2391	byte_stream += mapping.int2bytes( 4 , self.arg3 ) # optionnal arg3
[406]	2392	byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs
	2393	byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index
[305]	2394
[319]	2395	if ( verbose ):
	2396	print 'ptype = %d' % ptype_id
[520]	2397	print 'subtype = %d' % subtype_id
[319]	2398	print 'pseg_id = %d' % pseg_id
	2399	print 'nb_irqs = %d' % len( self.irqs )
[406]	2400	print 'irq_id = %d' % irq_id
[319]	2401	return byte_stream
[305]	2402
[512]	2403	######################################################################################
[319]	2404	class Irq ( object ):
[512]	2405	######################################################################################
[406]	2406	def __init__( self,
[319]	2407	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
	2408	srcid, # input IRQ index (for XCU or PIC)
	2409	isrtype, # Type of ISR to be executed
	2410	channel = 0 ): # channel index for multi-channel ISR
[305]	2411
[319]	2412	assert irqtype in IRQTYPES
	2413	assert isrtype in ISRTYPES
	2414	assert srcid < 32
[305]	2415
[319]	2416	self.index = 0 # global index ( set by addIrq() )
[406]	2417	self.irqtype = irqtype # IRQ type
[319]	2418	self.srcid = srcid # source IRQ index
[406]	2419	self.isrtype = isrtype # ISR type
[319]	2420	self.channel = channel # channel index (for multi-channels ISR)
[305]	2421	return
	2422
[319]	2423	################
	2424	def xml( self ): # xml for Irq
[305]	2425
[319]	2426	return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
	2427	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
[305]	2428
[319]	2429	#############################################
	2430	def cbin( self, mapping, verbose, expected ): # C binary structure for Irq
[305]	2431
[319]	2432	if ( verbose ):
[406]	2433	print '*** cbin for irq[%d]' % (self.index)
[305]	2434
[319]	2435	# check index
	2436	if (self.index != expected):
[512]	2437	print '[genmap error] in Irq.cbin()'
	2438	print ' irq global index = %d / expected = %d' % (self.index,expected)
[319]	2439	sys.exit(1)
[305]	2440
[319]	2441	# compute numerical value for irqtype
	2442	irqtype_id = 0xFFFFFFFF
	2443	for x in xrange( len(IRQTYPES) ):
[512]	2444	if ( self.irqtype == IRQTYPES[x] ): irqtype_id = x
	2445
[319]	2446	if ( irqtype_id == 0xFFFFFFFF ):
[512]	2447	print '[genmap error] in Irq.cbin()'
	2448	print ' undefined irqtype %s' % self.irqtype
[319]	2449	sys.exit(1)
[305]	2450
[319]	2451	# compute numerical value for isrtype
	2452	isrtype_id = 0xFFFFFFFF
[406]	2453	for x in xrange( len(ISRTYPES) ):
[512]	2454	if ( self.isrtype == ISRTYPES[x] ): isrtype_id = x
	2455
[319]	2456	if ( isrtype_id == 0xFFFFFFFF ):
[512]	2457	print '[genmap error] in Irq.cbin()'
	2458	print ' undefined isrtype %s' % self.isrtype
[319]	2459	sys.exit(1)
	2460
	2461	byte_stream = bytearray()
	2462	byte_stream += mapping.int2bytes( 4, irqtype_id )
	2463	byte_stream += mapping.int2bytes( 4, self.srcid )
	2464	byte_stream += mapping.int2bytes( 4, isrtype_id )
	2465	byte_stream += mapping.int2bytes( 4, self.channel )
	2466	byte_stream += mapping.int2bytes( 4, 0 )
	2467	byte_stream += mapping.int2bytes( 4, 0 )
	2468
	2469	if ( verbose ):
	2470	print 'irqtype = %s' % self.irqtype
	2471	print 'srcid = %d' % self.srcid
	2472	print 'isrtype = %s' % self.isrtype
	2473	print 'channel = %d' % self.channel
	2474
	2475	return byte_stream
	2476
[305]	2477	# Local Variables:
	2478	# tab-width: 4;
	2479	# c-basic-offset: 4;
	2480	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	2481	# indent-tabs-mode: nil;
	2482	# End:
	2483	#
	2484	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	2485

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