![(please configure the [header_logo] section in trac.ini)](/trac/giet-vm/chrome/site/your_project_logo.png){kind=logo}
Changeset 165 for soft/giet_vm/boot/reset.S
- Timestamp:
- Jul 4, 2012, 2:51:18 PM (12 years ago)
- File:
-
- 1 edited
-
soft/giet_vm/boot/reset.S (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
soft/giet_vm/boot/reset.S
r162 r165 1 1 /********************************************************************************/ 2 /* File : reset.S 3 /* Author : Alain Greiner & Mohamed karaoui 4 /* Date : 03/06/2012 */2 /* File : reset.S */ 3 /* Author : Alain Greiner & Mohamed karaoui */ 4 /* Date : 03/06/2012 */ 5 5 /********************************************************************************/ 6 6 /* This boot code is for a multi-cluster, multi-processor architecture, */ 7 /* running one or several multi-tasks software application(s) defined in the*/7 /* running one or several multi-tasks software application(s) defined in */ 8 8 /* the mapping_info data-structure. */ 9 /* It uses the mapping_info data structure to build the page tables.*/10 /* Processor 0 is in charge of building all pages tables.*/9 /* Procesor 0 uses the mapping_info data structure to build all page tables */ 10 /* before jumping to the kernel_init code. */ 11 11 /* Other processors are waiting until the mapping_info signature has been */ 12 12 /* modified by processor 0 (done while executing kernel_init code). */ 13 /* Implementation note: */ 13 14 /* The entry point is 0xbfc00000, but the actual boot code starts at address */ 14 15 /* 0xbfc00500, and a minimal boot exception handler is implemented at address */ … … 17 18 18 19 #include <giet_config.h> 19 #include <mips32_registers.h>20 #include "../sys/mips32_registers.h" 20 21 21 22 #define EXCEP_ORG 0x380 … … 44 45 boot_excep: 45 46 la a0, boot_error_string 46 jal boot_ tty_puts47 jal boot_puts 47 48 nop 48 49 mfc0 a0, CP0_TIME 49 jal boot_ tty_putw50 jal boot_putw 50 51 nop 51 52 la a0, boot_lf_string 52 jal boot_tty_puts 53 jal boot_puts 54 nop 55 56 la a0, boot_pid_string 57 jal boot_puts 58 nop 59 mfc0 k0, CP0_PROCID 60 andi a0, k0, 0xFFF 61 jal boot_putw 62 nop 63 la a0, boot_lf_string 64 jal boot_puts 53 65 nop 54 66 55 67 la a0, boot_epc_string 56 jal boot_ tty_puts68 jal boot_puts 57 69 nop 58 70 mfc0 a0, CP0_EPC 59 60 jal boot_tty_putw 71 jal boot_putw 61 72 nop 62 73 la a0, boot_lf_string 63 jal boot_ tty_puts74 jal boot_puts 64 75 nop 65 76 66 77 la a0, boot_cr_string 67 jal boot_ tty_puts78 jal boot_puts 68 79 nop 69 80 mfc0 a0, CP0_CR 70 jal boot_ tty_putw81 jal boot_putw 71 82 nop 72 83 la a0, boot_lf_string 73 jal boot_ tty_puts84 jal boot_puts 74 85 nop 75 86 76 87 la a0, boot_sr_string 77 jal boot_ tty_puts88 jal boot_puts 78 89 nop 79 90 mfc0 a0, CP0_SR 80 jal boot_ tty_putw91 jal boot_putw 81 92 nop 82 93 la a0, boot_lf_string 83 jal boot_ tty_puts94 jal boot_puts 84 95 nop 85 96 86 97 la a0, boot_bar_string 87 jal boot_ tty_puts98 jal boot_puts 88 99 nop 89 100 mfc0 a0, CP0_BAR 90 jal boot_ tty_putw101 jal boot_putw 91 102 nop 92 103 la a0, boot_lf_string 93 jal boot_ tty_puts104 jal boot_puts 94 105 nop 95 106 … … 101 112 /*******************************************/ 102 113 .align 2 103 114 .org START_ORG 104 115 105 116 boot_start: 106 117 /* get the procid */ 107 118 mfc0 k0, CP0_PROCID 108 andi k0, k0, 0x3FF /* no more than 1024processors... */119 andi k0, k0, 0xFFF /* no more than 4096 processors... */ 109 120 110 111 121 /* Only processor 0 does init */ 122 bne k0, zero, boot_wait_signature 112 123 nop 113 124 114 /* temporary stack for procesor 0 : 16K*/115 116 addiu sp, sp, 0x4000 125 /* Processor 0 get a temporary stack */ 126 la sp, seg_boot_stack_base 127 addiu sp, sp, 0x3000 /* SP <= seg_boot_stack + 12K */ 117 128 118 /* plat-form initialisation*/119 jal boot_init129 /* Processor 0 initialises all Page Tables */ 130 jal boot_pt_init 120 131 nop 121 j to_kinit 132 133 /* jump to kernel_init */ 134 j boot_to_kernel_init 122 135 nop 123 136 124 137 boot_wait_signature: 138 139 /* all other processors are waiting signature change */ 125 140 la k0, seg_mapping_base 126 cache 0x11, 0(k0) 127 lw k0, 0(k0) /* k0 <= mapping_info[0]*/141 cache 0x11, 0(k0) /* invalidate local cache copy */ 142 lw k0, 0(k0) /* k0 <= mapping_info[0] */ 128 143 li k1, OUT_MAPPING_SIGNATURE 129 144 bne k1, k0, boot_wait_signature 130 145 nop 131 146 132 to_kinit: 133 /* All processors initialize PTPR / MODE */ 134 /* and jump to kernel_init code. */ 147 /* all other processors get a temporary stack of 256 bytes */ 148 la sp, seg_boot_stack_base 149 addiu sp, sp, 0x3100 150 mfc0 k0, CP0_PROCID 151 andi k0, k0, 0xFFF 152 sll k0, k0, 8 153 addu sp, sp, k0 /* SP <= seg_boot_stack_base + 12K + (pid+1)*256 */ 135 154 136 /* get the procid */ 137 mfc0 s0, CP0_PROCID 138 andi s0, s0, 0x3FF /* no more than 1024 processors... TOFIX*/ 155 boot_to_kernel_init: 139 156 140 /* load a PTPR*/141 157 /* all processors initialize PTPR with PTAB[0] */ 158 la k1, _ptabs 142 159 lw k1, 0(k1) 143 160 srl k1, k1, 13 144 mtc2 k1, CP2_PTPR /* ptpr<= _ptabs[0] */161 mtc2 k1, CP2_PTPR /* PTPR <= _ptabs[0] */ 145 162 146 /* a ctivatesMMU */147 lik1, 0xF148 mtc2 k1, CP2_MODE /* loadMODE register */163 /* all processors activate MMU */ 164 li k1, 0xF 165 mtc2 k1, CP2_MODE /* MODE register */ 149 166 150 167 /* jump to kernel_init */ 151 168 la k0, seg_kernel_init_base 152 169 j k0 153 170 nop 154 171 155 156 boot_ error_string: .asciiz "\n[BOOT] Fatal Error at cycle"172 boot_error_string: .asciiz "\n[BOOT] Fatal Error in reset.S at cycle " 173 boot_pid_string: .asciiz " PID = " 157 174 boot_sr_string: .asciiz " SR = " 158 175 boot_cr_string: .asciiz " CR = "
Note: See TracChangeset
for help on using the changeset viewer.
