Changeset 238 for soft/giet_vm/boot/reset.S

Timestamp:

May 29, 2013, 1:24:09 AM (11 years ago)

Author:

alain

Message:

Major evolution to support physical addresses larger than 32 bits.
The map.xml format has been modified: the vsegs associated to schedulers
are now explicitely defined and mapped in the page tables.

File:

• soft/giet_vm/boot/reset.S (modified) (1 diff)

soft/giet_vm/boot/reset.S

@@ -182 +182 @@
 boot_to_kernel_init:
 
-    # all processors initialise SCHED register with boot_schedulers_paddr[pid] 
+    # all processors initialise the CP0 SCHED register
+    # SCHED contains the schedulers array virtual base address
     mfc0        k0, CP0_PROCID
     andi    k0, k0, 0xFFF
     sll         k0, k0, 2               # k0 <= 4*pid 
-    la          k1, boot_schedulers_paddr
-    addu    k1, k1, k0          # k1 <= &boot_scheduler_paddr[pid] 
-    lw          k1,     0(k1)           
-    mtc0        k1, CP0_SCHED
-
-    # all processors initialize PTPR register with boot_ptabs_paddr[0] 
+    la          k1, boot_schedulers
+    addu    k1, k1, k0          # k1 <= &boot_schedulers[pid] 
+    lw          k0,     0(k1)           
+    mtc0        k0, CP0_SCHED
+
+    # all processors initialize the CP2 PTPR register
+    # At this stage, all PTPR registers contain the physical base
+    # address (13 bits right shifted) of the page table for vspace[0] 
     la      k1, boot_ptabs_paddr
-    lw      k1, 0(k1)   
-    srl     k1, k1, 13
-    mtc2        k1,     CP2_PTPR        
-
-        # all processors activate MMU 
+    lw      k0, 0(k1)           # k0 <= paddr_lsb
+    lw      k1, 4(k1)           # k1 <= paddr_msb
+    srl     k0, k0, 13          # k0 <= paddr_lsb shifted
+    sll     k1, k1, 19          # k1 <= paddr_msb shifted
+    or      k0, k0, k1
+    mtc2        k0,     CP2_PTPR        
+
+        # all processors activate MMU (already done for processor 0)
     li      k1, 0xF
     mtc2    k1, CP2_MODE