Ignore:
Timestamp:
Jan 31, 2014, 2:37:38 PM (10 years ago)
Author:
cfuguet
Message:

Modification of comments format on SPI-SDCARD driver to respect
GIET-VM format

File:
1 edited

Legend:

Unmodified
Added
Removed

  • branch/giet_vm_ioc_drivers/giet_drivers/spi_driver.h

    r283 r284  
    1 /**
    2  * \file  : spi_driver.h
    3  * \date  : 30 August 2012
    4  * \author: Cesar Fuguet <cesar.fuguet-tortolero@lip6.fr>
    5  *
    6  * This file contains the definition of a driver for the SPI controller
    7  */
    8 
    9 #ifndef SPI_DRIVER_H
    10 #define SPI_DRIVER_H
     1///////////////////////////////////////////////////////////////////////////////////
     2// File     : spi_driver.h
     3// Date     : 31/08/2012
     4// Author   : cesar fuguet
     5// Copyright (c) UPMC-LIP6
     6///////////////////////////////////////////////////////////////////////////////////
     7#ifndef _GIET_SPI_DRIVER_H_
     8#define _GIET_SPI_DRIVER_H_
    119
    1210#include <io.h>
    1311#include <mapping_info.h>
    1412
    15 /**
    16  * SPI type definition
    17  */
     13///////////////////////////////////////////////////////////////////////////////
     14// SPI structure definition
     15///////////////////////////////////////////////////////////////////////////////
    1816struct spi_dev
    1917{
    20     /**
    21      * RX/TX registers of the SPI controller
    22      */
     18    // RX/TX registers of the SPI controller
    2319    unsigned int rx_tx[4];
    2420
    25     /**
    26      * Control register of the SPI controller
    27      */
     21    // control register of the SPI controller
    2822    unsigned int ctrl;
    2923
    30     /**
    31      * Divider register for the SPI controller generated clock signal
    32      */
     24    // divider register for the SPI controller generated clock signal
    3325    unsigned int divider;
    3426
    35     /**
    36      * Slave select register of the SPI controller
    37      */
     27    // slave select register of the SPI controller
    3828    unsigned int ss;
     29
     30    // SPI-DMA registers
    3931    unsigned int dma_base;
    4032    unsigned int dma_baseh;
    … …  
    4234};
    4335
    44 /**
    45  * \param   spi     : initialized pointer to a SPI controller.
    46  * \param   byte    : Byte to send to the SPI controller
    47  * \param   index   : index of the TX register in the SPI (TX[index])
    48  *
    49  * \return  void
    50  *
    51  * \brief   Send a byte to one of the tx buffer registers of the
    52  *          SPI controller
    53  */
    5436void spi_put_tx(struct spi_dev * spi, unsigned char byte, int index);
    5537
    56 /**
    57  * \param   spi     : initialized pointer to a SPI controller.
    58  * \param   index   : index of the RX register in the SPI (RX[index])
    59  *
    60  * \return  byte from the RX[index] register
    61  *
    62  * \brief   Get a byte from one of the rx buffer registers of the
    63  *          SPI controller
    64  */
    6538inline volatile unsigned char spi_get_rx(struct spi_dev * spi, int index);
    6639
    67 /**
    68  * \param   spi     : initialized pointer to a SPI controller.
    69  * \param   buf     : buffer to store data read
    70  * \param   count   : byte count to read
    71  *
    72  * \return  void
    73  *
    74  * \brief   get a data block from the SPI controller using 128bits
    75  *          reads if possible
    76  */
    7740unsigned int spi_get_data(struct spi_dev * spi, paddr_t buffer, unsigned int count);
    7841
    79 /**
    80  * \param   spi     : initialized pointer to a SPI controller.
    81  * \param   index   : index of the slave select signal to assert
    82  *
    83  * \return  void
    84  *
    85  * \brief   Set the index selected slave select signal (ss[index] <= '0')
    86  */
    8742inline void spi_ss_assert(struct spi_dev * spi, int index);
    8843
    89 /**
    90  * \param   spi     : initialized pointer to a SPI controller.
    91  * \param   index   : index of the slave select signal to deassert
    92  *
    93  * \return  void
    94  *
    95  * \brief   Unset the index selected slave select signal (ss[index] <= '0')
    96  */
    9744inline void spi_ss_deassert(struct spi_dev * spi, int index);
    9845
    99 /**
    100  * \param   spi         : initialized pointer to a SPI controller.
    101  * \param   spi_freq    : SPI Master to Slave clock frequency (in Hz)
    102  * \param   sys_freq    : System clock frequency (in Hz)
    103  * \param   char_len    : number to bits to transmit in one transfer
    104  * \param   tx_edge     : when 0, the Master Out Slave In signal is changed
    105  *                        on the falling edge of the clock
    106  * \param   rx_edge     : when 0, the Master In Slave Out signal is latched
    107  *                        on the falling edge of the clock
    108  *
    109  * \return  void
    110  *
    111  * \brief   Configure the SPI controller
    112  * \note    Any of the arguments can be less than 0 if you want to keep the old value
    113  */
    114 void _spi_init (
    115         struct spi_dev * spi,
    116         int spi_freq        ,
    117         int sys_freq        ,
    118         int char_len        ,
    119         int tx_edge         ,
    120         int rx_edge         );
     46void _spi_init ( struct spi_dev * spi,
     47                 int spi_freq        ,
     48                 int sys_freq        ,
     49                 int char_len        ,
     50                 int tx_edge         ,
     51                 int rx_edge         );
    12152
    122 /**
    123  * SPI macros and constants
    124  */
    125 #define SPI_TX_POSEDGE         1           /**< MOSI is changed on neg edge   */
    126 #define SPI_TX_NEGEDGE         0           /**< MOSI is changed on pos edge   */
    127 #define SPI_RX_POSEDGE         1           /**< MISO is latched on pos edge   */
    128 #define SPI_RX_NEGEDGE         0           /**< MISO is latched on neg edge   */
     53///////////////////////////////////////////////////////////////////////////////
     54// SPI macros and constants
     55///////////////////////////////////////////////////////////////////////////////
     56#define SPI_TX_POSEDGE         1           // MOSI is changed on neg edge
     57#define SPI_TX_NEGEDGE         0           // MOSI is changed on pos edge
     58#define SPI_RX_POSEDGE         1           // MISO is latched on pos edge
     59#define SPI_RX_NEGEDGE         0           // MISO is latched on neg edge
    12960
    130 #define SPI_CTRL_ASS_EN        ( 1 << 13 ) /**< Auto Slave Sel Assertion      */
    131 #define SPI_CTRL_IE_EN         ( 1 << 12 ) /**< Interrupt Enable              */
    132 #define SPI_CTRL_LSB_EN        ( 1 << 11 ) /**< LSB are sent first            */
    133 #define SPI_CTRL_TXN_EN        ( 1 << 10 ) /**< MOSI is changed on neg edge   */
    134 #define SPI_CTRL_RXN_EN        ( 1 << 9  ) /**< MISO is latched on neg edge   */
    135 #define SPI_CTRL_GO_BSY        ( 1 << 8  ) /**< Start the transfer            */
    136 #define SPI_CTRL_DMA_BSY        (1 << 16)  /***   DMA in progress             */
    137 #define SPI_CTRL_CHAR_LEN_MASK (  0xFF   ) /**< Bits transmited in 1 transfer */
    138 #define SPI_RXTX_MASK          (  0xFF   ) /**< Mask for the an RX/TX value   */
     61#define SPI_CTRL_ASS_EN        ( 1 << 13 ) // Auto Slave Sel Assertion
     62#define SPI_CTRL_IE_EN         ( 1 << 12 ) // Interrupt Enable
     63#define SPI_CTRL_LSB_EN        ( 1 << 11 ) // LSB are sent first
     64#define SPI_CTRL_TXN_EN        ( 1 << 10 ) // MOSI is changed on neg edge
     65#define SPI_CTRL_RXN_EN        ( 1 << 9  ) // MISO is latched on neg edge
     66#define SPI_CTRL_GO_BSY        ( 1 << 8  ) // Start the transfer
     67#define SPI_CTRL_DMA_BSY       ( 1 << 16 ) // DMA in progress
     68#define SPI_CTRL_CHAR_LEN_MASK (  0xFF   ) // Bits transmited in 1 transfer
     69#define SPI_RXTX_MASK          (  0xFF   ) // Mask for the an RX/TX value
    13970
    140 #define SPI_DMA_COUNT_READ      (1 << 0) /* operation is a read (else write) */
     71#define SPI_DMA_COUNT_READ     ( 1 << 0  ) // operation is a read (else write)
    14172
    142 /**
    143  * \param  x : Initialized pointer to the SPI controller
    144  *
    145  * \return 1 if there is an unfinished transfer in the SPI controller
    146  *
    147  * \brief  Check the GO_BUSY bit of the SPI Controller
    148  */
    149 #define SPI_IS_BUSY(x)         ((ioread32(&x->ctrl) & (SPI_CTRL_GO_BSY|SPI_CTRL_DMA_BSY)) != 0) ? 1 : 0
     73///////////////////////////////////////////////////////////////////////////////
     74//      SPI_IS_BUSY()
     75// This macro checks the GO_BSY and DMA_BSY bits of the SPI controller which
     76// indicates an ongoing transfer.
     77//
     78// Returns 1 if there is an unfinished transfer
     79///////////////////////////////////////////////////////////////////////////////
     80#define SPI_IS_BUSY(x) \
     81    ((ioread32(&x->ctrl) & (SPI_CTRL_GO_BSY|SPI_CTRL_DMA_BSY)) != 0) ? 1 : 0
    15082
    15183#endif
    15284
    153 /*
    154  * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4
    155  */
     85// Local Variables:
     86// tab-width: 4
     87// c-basic-offset: 4
     88// c-file-offsets:((innamespace . 0)(inline-open . 0))
     89// indent-tabs-mode: nil
     90// End:
     91// vim: filetype=c:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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