Changeset 406 for soft/giet_vm
- Timestamp:
- Sep 12, 2014, 3:01:34 PM (10 years ago)
- File:
-
- 1 edited
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soft/giet_vm/giet_python/mapping.py
r404 r406 27 27 # or the tasks set is split in several subsets (one subset per vspace), etc... 28 28 # In the C binary data structure used by the giet_vm, all objects of same type 29 # are stored in a linear array (one single array for all psegs for example). 30 # For all objects, we compute and store in the PYTHON object itsel a "global index" 31 # corresponding to the index in this global array, and this index can be used as 29 # are stored in a linear array (one single array for all psegs for example). 30 # For all objects, we compute and store in the PYTHON object itsel a "global index" 31 # corresponding to the index in this global array, and this index can be used as 32 32 # a pseudo-pointer to identify a specific object of a given type. 33 33 ########################################################################################## … … 131 131 ########################################################################################## 132 132 def __init__( self, 133 name, # mapping name 133 name, # mapping name 134 134 x_size, # number of clusters in a row 135 135 y_size, # number of clusters in a column 136 procs_max ,# max number of processors per cluster136 procs_max = 2, # max number of processors per cluster 137 137 x_width = 4, # number of bits encoding x coordinate 138 138 y_width = 4, # number of bits encoding y coordinate 139 p_width = 2, # number of bits encoding local proc id 139 140 paddr_width = 40, # number of bits for physical address 140 141 coherence = 1, # hardware cache coherence when non-zero 141 irq_per_proc = 1, # number or IRQs from XCU to processor 142 irq_per_proc = 1, # number or IRQs from XCU to processor 142 143 use_ramdisk = False, # use ramdisk when true 143 144 x_io = 0, # cluster_io x coordinate … … 148 149 ram_size = 0 ): # RAM size in each cluster (bytes) 149 150 151 assert (procs_max <= (1 << p_width)) 152 150 153 self.signature = 0xDACE2014 151 154 self.name = name 152 self.paddr_width = paddr_width 155 self.paddr_width = paddr_width 153 156 self.coherence = coherence 154 157 self.x_size = x_size 155 158 self.y_size = y_size 159 self.procs_max = procs_max 156 160 self.x_width = x_width 157 161 self.y_width = y_width 162 self.p_width = p_width 158 163 self.irq_per_proc = irq_per_proc 159 self.procs_max = procs_max160 164 self.use_ramdisk = use_ramdisk 161 165 self.x_io = x_io … … 186 190 for y in xrange( self.y_size ): 187 191 cluster = Cluster( x , y ) 188 cluster.index = (x * self.y_size) + y 192 cluster.index = (x * self.y_size) + y 189 193 self.clusters.append( cluster ) 190 194 … … 192 196 193 197 ########################## add a ram pseg in a cluster 194 def addRam( self, 198 def addRam( self, 195 199 name, # pseg name 196 200 base, # pseg base address 197 201 size ): # pseg length (bytes) 198 202 199 203 # check coordinates (obtained from the base address) 200 204 paddr_lsb_width = self.paddr_width - self.x_width - self.y_width 201 205 cluster_xy = base >> paddr_lsb_width 202 206 x = cluster_xy >> (self.y_width); 203 y = cluster_xy & ((1 << self.y_width) - 1) 207 y = cluster_xy & ((1 << self.y_width) - 1) 204 208 205 209 assert (base & 0xFFF) == 0 206 210 207 211 assert (x < self.x_size) and (y < self.y_size) 208 212 209 213 assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base ) 210 214 … … 222 226 223 227 ############################## add a peripheral and the associated pseg in a cluster 224 def addPeriph( self, 228 def addPeriph( self, 225 229 name, # associated pseg name 226 230 base, # associated pseg base address 227 231 size, # associated pseg length (bytes) 228 ptype, # peripheral type 232 ptype, # peripheral type 229 233 subtype = 'NONE', # peripheral subtype 230 234 channels = 1, # number of channels … … 234 238 cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width) 235 239 x = cluster_xy >> (self.y_width); 236 y = cluster_xy & ((1 << self.y_width) - 1) 240 y = cluster_xy & ((1 << self.y_width) - 1) 237 241 238 242 assert (x < self.x_size) and (y < self.y_size) … … 253 257 254 258 # add one periph into mapping 255 periph = Periph( pseg, ptype, subtype, channels, arg ) 259 periph = Periph( pseg, ptype, subtype, channels, arg ) 256 260 self.clusters[cluster_id].periphs.append( periph ) 257 261 periph.index = self.total_periphs … … 271 275 assert index < 32 272 276 273 # add one irq into mapping 277 # add one irq into mapping 274 278 irq = Irq( 'HWI', index , isrtype, channel ) 275 279 periph.irqs.append( irq ) … … 280 284 281 285 ########################## add a processor in a cluster 282 def addProc( self, 286 def addProc( self, 283 287 x, # cluster x coordinate 284 288 y, # cluster y coordinate … … 289 293 cluster_id = (x * self.y_size) + y 290 294 291 # add one proc into mapping 295 # add one proc into mapping 292 296 proc = Processor( x, y, p ) 293 297 self.clusters[cluster_id].procs.append( proc ) … … 298 302 299 303 ############################## add a coprocessor in a cluster 300 def addCoproc( self, 304 def addCoproc( self, 301 305 name, # associated pseg name 302 306 base, # associated pseg base address 303 307 size ): # associated pseg length 304 308 305 309 # check cluster coordinates (obtained from the base address) 306 310 cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width) 307 311 x = cluster_xy >> (self.y_width); 308 y = cluster_xy & ((1 << self.y_width) - 1) 312 y = cluster_xy & ((1 << self.y_width) - 1) 309 313 310 314 assert (x < self.x_size) and (y < self.y_size) … … 319 323 320 324 # add one coproc into mapping 321 periph = Coproc( pseg ) 325 periph = Coproc( pseg ) 322 326 self.clusters[cluster_id].coprocs.append( coproc ) 323 327 periph.index = self.total_coprocs … … 326 330 return coproc 327 331 328 ################################## add a port in a coprocessor 329 def addPort( self, 332 ################################## add a port in a coprocessor 333 def addPort( self, 330 334 coproc, # coprocessor containing the port 331 335 direction, # direction (TO_COPROC / FROM_COPROC) … … 343 347 return port 344 348 345 ############################ add one (or several) global vseg into mapping 346 def addGlobal( self, 349 ############################ add one (or several) global vseg into mapping 350 def addGlobal( self, 347 351 name, # vseg name 348 352 vbase, # virtual base address … … 355 359 identity = False, # identity mapping required if true 356 360 binpath = '', # pathname for binary code 357 local = False ): # non shared vseg when true 361 local = False ): # non shared vseg when true 358 362 359 363 assert mode in VSEGMODES … … 366 370 367 371 # add one vseg into mapping 368 vseg = Vseg( name, vbase, mode, x, y, pseg, 372 vseg = Vseg( name, vbase, mode, x, y, pseg, 369 373 identity = identity, local = local ) 370 374 371 375 self.globs.append( vseg ) 372 376 self.total_globals += 1 373 vseg.index = self.total_vsegs 377 vseg.index = self.total_vsegs 374 378 self.total_vsegs += 1 375 379 376 380 # add one vobj into mapping 377 381 vobj = Vobj( name, size, vtype, binpath, 0, 0 ) … … 383 387 384 388 ################################ add a vspace into mapping 385 def addVspace( self, 389 def addVspace( self, 386 390 name, # vspace name 387 391 startname ): # name of vobj containing start_vector … … 394 398 395 399 return vspace 396 400 397 401 ################################# add a private vseg and a vobj in a vspace 398 402 def addVseg( self, 399 vspace, # vspace containing the vseg 403 vspace, # vspace containing the vseg 400 404 name, # vseg name 401 405 vbase, # virtual base address … … 432 436 433 437 ################################ add a vobj in a private vseg 434 def addVobj( self, 438 def addVobj( self, 435 439 vseg, # vseg containing vobj 436 440 name, # vobj name … … 451 455 return vobj 452 456 453 ################################ add a task in a vspace 454 def addTask( self, 457 ################################ add a task in a vspace 458 def addTask( self, 455 459 vspace, # vspace containing task 456 460 name, # task name … … 467 471 usehba = False, # request a private HBA channel 468 472 usetim = False ): # request a private TIM channel 469 473 470 474 assert (x < self.x_size) and (y < self.y_size) 471 472 475 assert lpid < self.procs_max 473 476 474 # add one task into mapping 477 # add one task into mapping 475 478 task = Task( name, trdid, x, y, lpid, stackname, heapname, startid, 476 479 usetty, usenic, usecma, usehba, usetim ) … … 498 501 499 502 ################################### 500 def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array 503 def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array 501 504 502 505 byte_stream = bytearray() … … 525 528 for x in xrange ( self.x_size ): 526 529 for y in xrange ( self.y_size ): 527 cluster_id = (x * self.y_size) + y 530 cluster_id = (x * self.y_size) + y 528 531 s += self.clusters[cluster_id].xml() 529 532 s += ' </clusterset>\n' … … 549 552 # header 550 553 byte_stream += self.int2bytes(4, self.signature) 551 byte_stream += self.int2bytes(4, self.x_size) 552 byte_stream += self.int2bytes(4, self.y_size) 553 byte_stream += self.int2bytes(4, self.x_width) 554 byte_stream += self.int2bytes(4, self.y_width) 555 byte_stream += self.int2bytes(4, self.x_io) 556 byte_stream += self.int2bytes(4, self.y_io) 557 byte_stream += self.int2bytes(4, self.irq_per_proc) 558 byte_stream += self.int2bytes(4, self.use_ramdisk) 559 byte_stream += self.int2bytes(4, self.total_globals) 560 byte_stream += self.int2bytes(4, self.total_vspaces) 561 byte_stream += self.int2bytes(4, self.total_psegs) 562 byte_stream += self.int2bytes(4, self.total_vsegs) 563 byte_stream += self.int2bytes(4, self.total_vobjs) 564 byte_stream += self.int2bytes(4, self.total_tasks) 565 byte_stream += self.int2bytes(4, self.total_procs) 566 byte_stream += self.int2bytes(4, self.total_irqs) 567 byte_stream += self.int2bytes(4, self.total_coprocs) 568 byte_stream += self.int2bytes(4, self.total_cpports) 569 byte_stream += self.int2bytes(4, self.total_periphs) 554 byte_stream += self.int2bytes(4, self.x_size) 555 byte_stream += self.int2bytes(4, self.y_size) 556 byte_stream += self.int2bytes(4, self.x_width) 557 byte_stream += self.int2bytes(4, self.y_width) 558 byte_stream += self.int2bytes(4, self.x_io) 559 byte_stream += self.int2bytes(4, self.y_io) 560 byte_stream += self.int2bytes(4, self.irq_per_proc) 561 byte_stream += self.int2bytes(4, self.use_ramdisk) 562 byte_stream += self.int2bytes(4, self.total_globals) 563 byte_stream += self.int2bytes(4, self.total_vspaces) 564 byte_stream += self.int2bytes(4, self.total_psegs) 565 byte_stream += self.int2bytes(4, self.total_vsegs) 566 byte_stream += self.int2bytes(4, self.total_vobjs) 567 byte_stream += self.int2bytes(4, self.total_tasks) 568 byte_stream += self.int2bytes(4, self.total_procs) 569 byte_stream += self.int2bytes(4, self.total_irqs) 570 byte_stream += self.int2bytes(4, self.total_coprocs) 571 byte_stream += self.int2bytes(4, self.total_cpports) 572 byte_stream += self.int2bytes(4, self.total_periphs) 570 573 byte_stream += self.str2bytes(32, self.name) 571 574 572 575 if ( verbose ): 573 print '\n' 576 print '\n' 574 577 print 'name = %s' % self.name 575 578 print 'signature = %x' % self.signature … … 578 581 print 'x_width = %d' % self.x_width 579 582 print 'y_width = %d' % self.y_width 580 print 'x_io = %d' % self.x_io 581 print 'y_io = %d' % self.y_io 583 print 'x_io = %d' % self.x_io 584 print 'y_io = %d' % self.y_io 582 585 print 'irq_per_proc = %d' % self.irq_per_proc 583 586 print 'use_ramdisk = %d' % self.use_ramdisk 584 587 print 'total_globals = %d' % self.total_globals 585 print 'total_psegs = %d' % self.total_psegs 586 print 'total_vsegs = %d' % self.total_vsegs 587 print 'total_vobjs = %d' % self.total_vobjs 588 print 'total_tasks = %d' % self.total_tasks 589 print 'total_procs = %d' % self.total_procs 590 print 'total_irqs = %d' % self.total_irqs 588 print 'total_psegs = %d' % self.total_psegs 589 print 'total_vsegs = %d' % self.total_vsegs 590 print 'total_vobjs = %d' % self.total_vobjs 591 print 'total_tasks = %d' % self.total_tasks 592 print 'total_procs = %d' % self.total_procs 593 print 'total_irqs = %d' % self.total_irqs 591 594 print 'total_coprocs = %d' % self.total_coprocs 592 595 print 'total_cpports = %d' % self.total_cpports 593 596 print 'total_periphs = %d' % self.total_periphs 594 print '\n' 597 print '\n' 595 598 596 599 # clusters array … … 605 608 index = 0 606 609 for cluster in self.clusters: 607 for pseg in cluster.psegs: 610 for pseg in cluster.psegs: 608 611 byte_stream += pseg.cbin( self, verbose, index, cluster ) 609 612 index += 1 … … 613 616 # vspaces array 614 617 index = 0 615 for vspace in self.vspaces: 616 byte_stream += vspace.cbin( self, verbose, index ) 618 for vspace in self.vspaces: 619 byte_stream += vspace.cbin( self, verbose, index ) 617 620 index += 1 618 621 … … 625 628 index += 1 626 629 for vspace in self.vspaces: 627 for vseg in vspace.vsegs: 630 for vseg in vspace.vsegs: 628 631 byte_stream += vseg.cbin( self, verbose, index ) 629 632 index += 1 … … 638 641 index += 1 639 642 for vspace in self.vspaces: 640 for vseg in vspace.vsegs: 643 for vseg in vspace.vsegs: 641 644 for vobj in vseg.vobjs: 642 byte_stream += vobj.cbin( self, verbose, index ) 645 byte_stream += vobj.cbin( self, verbose, index ) 643 646 index += 1 644 647 … … 648 651 index = 0 649 652 for vspace in self.vspaces: 650 for task in vspace.tasks: 653 for task in vspace.tasks: 651 654 byte_stream += task.cbin( self, verbose, index, vspace ) 652 655 index += 1 … … 657 660 index = 0 658 661 for cluster in self.clusters: 659 for proc in cluster.procs: 662 for proc in cluster.procs: 660 663 byte_stream += proc.cbin( self, verbose, index ) 661 664 index += 1 662 665 663 666 if ( verbose ): print '\n' 664 667 665 668 # irqs array 666 index = 0 669 index = 0 667 670 for cluster in self.clusters: 668 671 for periph in cluster.periphs: … … 676 679 index = 0 677 680 for cluster in self.clusters: 678 for coproc in cluster.coprocs: 679 byte_stream += coproc.cbin( self, verbose, index ) 681 for coproc in cluster.coprocs: 682 byte_stream += coproc.cbin( self, verbose, index ) 680 683 index += 1 681 684 … … 685 688 index = 0 686 689 for cluster in self.clusters: 687 for coproc in cluster.coprocs: 690 for coproc in cluster.coprocs: 688 691 for port in coproc.ports: 689 692 byte_stream += port.cbin( self, verbose, index ) … … 695 698 index = 0 696 699 for cluster in self.clusters: 697 for periph in cluster.periphs: 700 for periph in cluster.periphs: 698 701 byte_stream += periph.cbin( self, verbose, index ) 699 702 index += 1 … … 701 704 return byte_stream 702 705 # end of cbin() 703 706 704 707 ####################### 705 def giet_vsegs( self ): # compute string for giet_vsegs.ld file 708 def giet_vsegs( self ): # compute string for giet_vsegs.ld file 706 709 # required by giet_vm compilation 707 710 708 # search the vsegs required for the giet_vsegs.ld 711 # search the vsegs required for the giet_vsegs.ld 709 712 boot_code_found = False 710 713 boot_data_found = False … … 716 719 717 720 if ( vseg.name == 'seg_boot_code' ): 718 boot_code_vbase = vseg.vbase 721 boot_code_vbase = vseg.vbase 719 722 boot_code_size = vseg.vobjs[0].length 720 723 boot_code_found = True 721 724 722 if ( vseg.name == 'seg_boot_data' ): 723 boot_data_vbase = vseg.vbase 725 if ( vseg.name == 'seg_boot_data' ): 726 boot_data_vbase = vseg.vbase 724 727 boot_data_size = vseg.vobjs[0].length 725 728 boot_data_found = True 726 729 727 730 if ( vseg.name == 'seg_kernel_uncdata' ): 728 kernel_uncdata_vbase = vseg.vbase 731 kernel_uncdata_vbase = vseg.vbase 729 732 kernel_uncdata_size = vseg.vobjs[0].length 730 733 kernel_uncdata_found = True 731 734 732 735 if ( vseg.name == 'seg_kernel_data' ): 733 kernel_data_vbase = vseg.vbase 736 kernel_data_vbase = vseg.vbase 734 737 kernel_data_size = vseg.vobjs[0].length 735 738 kernel_data_found = True 736 739 737 740 if ( vseg.name == 'seg_kernel_code' ): 738 kernel_code_vbase = vseg.vbase 741 kernel_code_vbase = vseg.vbase 739 742 kernel_code_size = vseg.vobjs[0].length 740 743 kernel_code_found = True 741 744 742 745 if ( vseg.name == 'seg_kernel_init' ): 743 kernel_init_vbase = vseg.vbase 746 kernel_init_vbase = vseg.vbase 744 747 kernel_init_size = vseg.vobjs[0].length 745 748 kernel_init_found = True 746 749 747 750 # check if all required vsegs have been found 748 if ( boot_code_found == False ): 751 if ( boot_code_found == False ): 749 752 print '[genmap error] in giet_vsegs() : seg_boot_code vseg missing' 750 753 sys.exit() 751 754 752 if ( boot_data_found == False ): 755 if ( boot_data_found == False ): 753 756 print '[genmap error] in giet_vsegs() : seg_boot_data vseg missing' 754 757 sys.exit() 755 758 756 if ( kernel_data_found == False ): 759 if ( kernel_data_found == False ): 757 760 print '[genmap error] in giet_vsegs() : seg_kernel_data vseg missing' 758 761 sys.exit() … … 771 774 772 775 # build string 773 s = '/* Generated by genmap for %s */\n' % self.name 774 s += '\n' 775 776 s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase 777 s += 'boot_code_size = 0x%x;\n' % boot_code_size 778 s += '\n' 779 s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase 780 s += 'boot_data_size = 0x%x;\n' % boot_data_size 781 s += '\n' 782 s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase 783 s += 'kernel_code_size = 0x%x;\n' % kernel_code_size 784 s += '\n' 785 s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase 786 s += 'kernel_data_size = 0x%x;\n' % kernel_data_size 787 s += '\n' 788 s += 'kernel_uncdata_vbase = 0x%x;\n' % kernel_uncdata_vbase 789 s += 'kernel_uncdata_size = 0x%x;\n' % kernel_uncdata_size 790 s += '\n' 791 s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase 792 s += 'kernel_init_size = 0x%x;\n' % kernel_init_size 776 s = '/* Generated by genmap for %s */\n' % self.name 777 s += '\n' 778 779 s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase 780 s += 'boot_code_size = 0x%x;\n' % boot_code_size 781 s += '\n' 782 s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase 783 s += 'boot_data_size = 0x%x;\n' % boot_data_size 784 s += '\n' 785 s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase 786 s += 'kernel_code_size = 0x%x;\n' % kernel_code_size 787 s += '\n' 788 s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase 789 s += 'kernel_data_size = 0x%x;\n' % kernel_data_size 790 s += '\n' 791 s += 'kernel_uncdata_vbase = 0x%x;\n' % kernel_uncdata_vbase 792 s += 'kernel_uncdata_size = 0x%x;\n' % kernel_uncdata_size 793 s += '\n' 794 s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase 795 s += 'kernel_init_size = 0x%x;\n' % kernel_init_size 793 796 s += '\n' 794 797 795 798 return s 796 799 797 800 ######################## 798 801 def hard_config( self ): # compute string for hard_config.h file required by … … 804 807 805 808 # for each peripheral type, define default values 806 # for pbase address, size, number of components, and channels 809 # for pbase address, size, number of components, and channels 807 810 nb_cma = 0 808 811 cma_channels = 0 … … 889 892 for cluster in self.clusters: 890 893 for periph in cluster.periphs: 891 if ( periph.ptype == 'CMA' ): 894 if ( periph.ptype == 'CMA' ): 892 895 seg_cma_base = periph.pseg.base & 0xFFFFFFFF 893 896 seg_cma_size = periph.pseg.size … … 895 898 nb_cma +=1 896 899 897 elif ( periph.ptype == 'DMA' ): 898 seg_dma_base = periph.pseg.base & 0xFFFFFFFF 900 elif ( periph.ptype == 'DMA' ): 901 seg_dma_base = periph.pseg.base & 0xFFFFFFFF 899 902 seg_dma_size = periph.pseg.size 900 903 dma_channels = periph.channels 901 904 nb_dma +=1 902 905 903 elif ( periph.ptype == 'FBF' ): 906 elif ( periph.ptype == 'FBF' ): 904 907 seg_fbf_base = periph.pseg.base & 0xFFFFFFFF 905 908 seg_fbf_size = periph.pseg.size … … 908 911 nb_fbf +=1 909 912 910 elif ( periph.ptype == 'ICU' ): 913 elif ( periph.ptype == 'ICU' ): 911 914 seg_icu_base = periph.pseg.base & 0xFFFFFFFF 912 915 seg_icu_size = periph.pseg.size … … 920 923 nb_iob +=1 921 924 922 elif ( periph.ptype == 'IOC' ): 925 elif ( periph.ptype == 'IOC' ): 923 926 seg_ioc_base = periph.pseg.base & 0xFFFFFFFF 924 927 seg_ioc_size = periph.pseg.size … … 956 959 nb_sim +=1 957 960 958 elif ( periph.ptype == 'NIC' ): 961 elif ( periph.ptype == 'NIC' ): 959 962 seg_nic_base = periph.pseg.base & 0xFFFFFFFF 960 963 seg_nic_size = periph.pseg.size … … 962 965 nb_nic +=1 963 966 964 elif ( periph.ptype == 'PIC' ): 967 elif ( periph.ptype == 'PIC' ): 965 968 seg_pic_base = periph.pseg.base & 0xFFFFFFFF 966 969 seg_pic_size = periph.pseg.size 967 970 pic_channels = periph.channels 968 971 nb_pic +=1 969 970 elif ( periph.ptype == 'TIM' ): 972 973 elif ( periph.ptype == 'TIM' ): 971 974 seg_tim_base = periph.pseg.base & 0xFFFFFFFF 972 975 seg_tim_size = periph.pseg.size 973 976 tim_channels = periph.channels 974 977 nb_tim +=1 975 978 976 979 elif ( periph.ptype == 'TTY' ): 977 980 seg_tty_base = periph.pseg.base & 0xFFFFFFFF … … 979 982 tty_channels = periph.channels 980 983 nb_tty +=1 981 982 elif ( periph.ptype == 'XCU' ): 984 985 elif ( periph.ptype == 'XCU' ): 983 986 seg_xcu_base = periph.pseg.base & 0xFFFFFFFF 984 987 seg_xcu_size = periph.pseg.size … … 986 989 xcu_arg = periph.arg 987 990 nb_xcu +=1 988 991 989 992 # don't mix ICU and XCU 990 assert ( nb_icu*nb_xcu == 0 ) 993 assert ( nb_icu*nb_xcu == 0 ) 991 994 992 995 # no more than two access to external peripherals 993 assert ( nb_fbf <= 2 ) 994 assert ( nb_cma <= 2 ) 995 assert ( nb_ioc <= 2 ) 996 assert ( nb_nic <= 2 ) 997 assert ( nb_tim <= 2 ) 998 assert ( nb_tty <= 2 ) 996 assert ( nb_fbf <= 2 ) 997 assert ( nb_cma <= 2 ) 998 assert ( nb_ioc <= 2 ) 999 assert ( nb_nic <= 2 ) 1000 assert ( nb_tim <= 2 ) 1001 assert ( nb_tty <= 2 ) 999 1002 assert ( nb_pic <= 2 ) 1000 1003 … … 1019 1022 for vseg in self.globs: 1020 1023 if ( vseg.name == 'seg_boot_mapping' ): 1021 boot_mapping_base = vseg.vbase 1024 boot_mapping_base = vseg.vbase 1022 1025 boot_mapping_size = vseg.vobjs[0].length 1023 1026 boot_mapping_identity = vseg.identity … … 1025 1028 1026 1029 if ( vseg.name == 'seg_boot_code' ): 1027 boot_code_base = vseg.vbase 1030 boot_code_base = vseg.vbase 1028 1031 boot_code_size = vseg.vobjs[0].length 1029 1032 boot_code_identity = vseg.identity 1030 1033 boot_code_found = True 1031 1034 1032 if ( vseg.name == 'seg_boot_data' ): 1033 boot_data_base = vseg.vbase 1035 if ( vseg.name == 'seg_boot_data' ): 1036 boot_data_base = vseg.vbase 1034 1037 boot_data_size = vseg.vobjs[0].length 1035 1038 boot_data_identity = vseg.identity … … 1037 1040 1038 1041 if ( vseg.name == 'seg_boot_stack' ): 1039 boot_stack_base = vseg.vbase 1042 boot_stack_base = vseg.vbase 1040 1043 boot_stack_size = vseg.vobjs[0].length 1041 1044 boot_stack_identity = vseg.identity … … 1047 1050 sys.exit() 1048 1051 1049 if ( (boot_code_found == False) or (boot_code_identity == False) ): 1052 if ( (boot_code_found == False) or (boot_code_identity == False) ): 1050 1053 print '[genmap error] in hard_config() : seg_boot_code missing or not ident' 1051 1054 sys.exit() 1052 1055 1053 if ( (boot_data_found == False) or (boot_data_identity == False) ): 1056 if ( (boot_data_found == False) or (boot_data_identity == False) ): 1054 1057 print '[genmap error] in hard_config() : seg_boot_data missing or not ident' 1055 1058 sys.exit() … … 1076 1079 1077 1080 # build string 1078 s = '/* Generated by genmap for %s */\n' % self.name 1081 s = '/* Generated by genmap for %s */\n' % self.name 1079 1082 s += '\n' 1080 1083 s += '#ifndef HARD_CONFIG_H\n' … … 1082 1085 s += '\n' 1083 1086 1084 s += '/* General platform parameters */\n' 1087 s += '/* General platform parameters */\n' 1085 1088 s += '\n' 1086 1089 s += '#define X_SIZE %d\n' % self.x_size … … 1088 1091 s += '#define X_WIDTH %d\n' % self.x_width 1089 1092 s += '#define Y_WIDTH %d\n' % self.y_width 1093 s += '#define P_WIDTH %d\n' % self.p_width 1090 1094 s += '#define X_IO %d\n' % self.x_io 1091 s += '#define Y_IO %d\n' % self.y_io 1095 s += '#define Y_IO %d\n' % self.y_io 1092 1096 s += '#define NB_PROCS_MAX %d\n' % self.procs_max 1093 1097 s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc … … 1096 1100 s += '\n' 1097 1101 1098 s += '/* Peripherals */\n' 1102 s += '/* Peripherals */\n' 1099 1103 s += '\n' 1100 1104 s += '#define NB_TTY_CHANNELS %d\n' % tty_channels … … 1123 1127 s += '/* base addresses and sizes for physical segments */\n' 1124 1128 s += '\n' 1125 s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base 1126 s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size 1127 s += '\n' 1128 s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base 1129 s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size 1130 s += '\n' 1131 s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base 1132 s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size 1133 s += '\n' 1134 s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base 1135 s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size 1136 s += '\n' 1137 s += '#define SEG_ICU_BASE 0x%x\n' % seg_icu_base 1138 s += '#define SEG_ICU_SIZE 0x%x\n' % seg_icu_size 1139 s += '\n' 1140 s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base 1141 s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size 1142 s += '\n' 1143 s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base 1144 s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size 1145 s += '\n' 1146 s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base 1147 s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size 1148 s += '\n' 1149 s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base 1150 s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size 1151 s += '\n' 1152 s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base 1153 s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size 1154 s += '\n' 1155 s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base 1156 s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size 1157 s += '\n' 1158 s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base 1159 s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size 1160 s += '\n' 1161 s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base 1162 s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size 1163 s += '\n' 1164 s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base 1165 s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size 1166 s += '\n' 1167 s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base 1168 s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size 1169 s += '\n' 1170 s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base 1171 s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size 1129 s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base 1130 s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size 1131 s += '\n' 1132 s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base 1133 s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size 1134 s += '\n' 1135 s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base 1136 s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size 1137 s += '\n' 1138 s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base 1139 s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size 1140 s += '\n' 1141 s += '#define SEG_ICU_BASE 0x%x\n' % seg_icu_base 1142 s += '#define SEG_ICU_SIZE 0x%x\n' % seg_icu_size 1143 s += '\n' 1144 s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base 1145 s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size 1146 s += '\n' 1147 s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base 1148 s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size 1149 s += '\n' 1150 s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base 1151 s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size 1152 s += '\n' 1153 s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base 1154 s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size 1155 s += '\n' 1156 s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base 1157 s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size 1158 s += '\n' 1159 s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base 1160 s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size 1161 s += '\n' 1162 s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base 1163 s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size 1164 s += '\n' 1165 s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base 1166 s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size 1167 s += '\n' 1168 s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base 1169 s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size 1170 s += '\n' 1171 s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base 1172 s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size 1173 s += '\n' 1174 s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base 1175 s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size 1172 1176 s += '\n' 1173 1177 s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base … … 1192 1196 s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size 1193 1197 s += '#endif\n' 1194 1198 1195 1199 return s 1196 1200 … … 1199 1203 ####################### 1200 1204 def netbsd_dts( self ): # compute string for netbsd.dts file generation, 1201 # used for netbsd configuration 1205 # used for netbsd configuration 1202 1206 # header 1203 1207 s = '/dts-v1/;\n' 1204 1208 s += '\n' 1205 1209 s += '/{\n' 1206 s += ' #address-cells = <2>;\n' 1207 s += ' #size-cells = <1>;\n' 1210 s += ' #address-cells = <2>;\n' 1211 s += ' #size-cells = <1>;\n' 1208 1212 1209 1213 # cpus (for each cluster) … … 1214 1218 for cluster in self.clusters: 1215 1219 for proc in cluster.procs: 1216 proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + proc.lpid1220 proc_id = (((cluster.x << self.y_width) + cluster.y) << self.p_width) + proc.lpid 1217 1221 1218 1222 s += ' Mips,32@0x%x {\n' % proc_id … … 1244 1248 for cluster in self.clusters: 1245 1249 1246 # research XCU component 1250 # research XCU component 1247 1251 found_xcu = False 1248 1252 for periph in cluster.periphs: 1249 if ( (periph.ptype == 'XCU') ): 1253 if ( (periph.ptype == 'XCU') ): 1250 1254 found_xcu = True 1251 1255 xcu = periph … … 1264 1268 for lpid in xrange ( len(cluster.procs) ): # destination processor index 1265 1269 for itid in xrange ( self.irq_per_proc ): # input irq index on processor 1266 proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + lpid 1270 cluster_xy = (cluster.x << self.y_width) + cluster.y 1271 proc_id = (cluster_xy << self.p_width) + lpid 1267 1272 s += ' out@%d {\n' % output_id 1268 1273 s += ' device_type = "soclib:xicu:filter";\n' 1269 1274 s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid) 1270 s += ' output_line = <%d>;\n' % output_id 1275 s += ' output_line = <%d>;\n' % output_id 1271 1276 s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base) 1272 1277 s += ' };\n' … … 1279 1284 found_pic = False 1280 1285 for periph in cluster.periphs: 1281 if ( periph.ptype == 'PIC' ): 1286 if ( periph.ptype == 'PIC' ): 1282 1287 found_pic = True 1283 1288 pic = periph … … 1289 1294 s += ' device_type = "soclib:pic:root";\n' 1290 1295 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1291 s += ' input_lines = <%d>;\n' % periph.channels 1296 s += ' input_lines = <%d>;\n' % periph.channels 1292 1297 s += ' };\n' 1293 1298 1294 1299 if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ): 1295 1300 print '[genmap error] in netbsd_dts() : No XCU/PIC in cluster(%d,%d)' % (cluster.x, cluster.y) 1296 sys.exit(1) 1297 1301 sys.exit(1) 1302 1298 1303 if ( found_pic == True ): irq_tgt = pic 1299 1304 else: irq_tgt = xcu 1300 1305 1301 1306 # get all others peripherals in cluster 1302 1307 for periph in cluster.periphs: … … 1317 1322 hwi_id = 0xFFFFFFFF 1318 1323 for irq in xcu.irqs: 1319 if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ): 1324 if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ): 1320 1325 hwi_id = irq.srcid 1321 1326 if ( hwi_id == 0xFFFFFFFF ): … … 1331 1336 s += ' };\n' 1332 1337 1333 s += ' };\n' 1338 s += ' };\n' 1334 1339 1335 1340 # research MMC component … … 1348 1353 s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in) 1349 1354 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1350 s += ' };\n' 1355 s += ' };\n' 1351 1356 1352 1357 # research FBF component 1353 elif ( periph.ptype == 'FBF' ): 1358 elif ( periph.ptype == 'FBF' ): 1354 1359 1355 1360 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) … … 1362 1367 1363 1368 # research IOC component 1364 elif ( periph.ptype == 'IOC' ): 1369 elif ( periph.ptype == 'IOC' ): 1365 1370 1366 1371 if ( periph.subtype == 'BDV' ): … … 1423 1428 s += ' device_type = "soclib:tty";\n' 1424 1429 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1425 s += ' channel_count = < %d >;\n' % periph.channels 1430 s += ' channel_count = < %d >;\n' % periph.channels 1426 1431 1427 1432 # multi-channels : get HWI index (to XCU or PIC) for each channel … … 1429 1434 hwi_id = 0xFFFFFFFF 1430 1435 for irq in irq_tgt.irqs: 1431 if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ): 1436 if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ): 1432 1437 hwi_id = irq.srcid 1433 1438 if ( hwi_id == 0xFFFFFFFF ): … … 1444 1449 1445 1450 s += ' };\n' 1446 1451 1447 1452 # research IOB component 1448 1453 elif ( periph.ptype == 'IOB' ): … … 1454 1459 1455 1460 # research NIC component 1456 elif ( periph.ptype == 'NIC' ): 1461 elif ( periph.ptype == 'NIC' ): 1457 1462 1458 1463 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) … … 1466 1471 hwi_id = 0xFFFFFFFF 1467 1472 for irq in irq_tgt.irqs: 1468 if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ): 1473 if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ): 1469 1474 hwi_id = irq.srcid 1470 1475 if ( hwi_id == 0xFFFFFFFF ): … … 1482 1487 hwi_id = 0xFFFFFFFF 1483 1488 for irq in irq_tgt.irqs: 1484 if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ): 1489 if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ): 1485 1490 hwi_id = irq.srcid 1486 1491 if ( hwi_id == 0xFFFFFFFF ): … … 1495 1500 s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base) 1496 1501 s += ' };\n' 1497 1502 1498 1503 s += ' };\n' 1499 1504 1500 1505 # research CMA component 1501 elif ( periph.ptype == 'CMA' ): 1506 elif ( periph.ptype == 'CMA' ): 1502 1507 1503 1508 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) … … 1510 1515 hwi_id = 0xFFFFFFFF 1511 1516 for irq in irq_tgt.irqs: 1512 if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ): 1517 if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ): 1513 1518 hwi_id = irq.srcid 1514 1519 if ( hwi_id == 0xFFFFFFFF ): … … 1527 1532 1528 1533 # research TIM component 1529 elif ( periph.ptype == 'TIM' ): 1534 elif ( periph.ptype == 'TIM' ): 1530 1535 1531 1536 print '[genmap error] in netbsd_dts() : TIM peripheral not supported by NetBSD' … … 1539 1544 1540 1545 # research ICU component 1541 elif ( periph.ptype == 'ICU' ): 1546 elif ( periph.ptype == 'ICU' ): 1542 1547 print '[genmap error] in netbsd_dts() : ICU peripheral not supported by NetBSD' 1543 1548 sys.exit(1) … … 1549 1554 s += ' #size-cells = <0>;\n' 1550 1555 for cluster in self.clusters: 1551 s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y) 1556 s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y) 1552 1557 s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y) 1553 1558 s += ' devices = <\n' 1554 1559 1555 offset = ((cluster.x << self.y_width) + cluster.y) * self.procs_max1560 offset = ((cluster.x << self.y_width) + cluster.y) << self.p_width 1556 1561 for proc in cluster.procs: 1557 1562 s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid) … … 1569 1574 ########################### 1570 1575 def almos_archinfo( self ): # compute string for arch.info file generation, 1571 # used for almos configuration 1576 # used for almos configuration 1572 1577 # header 1573 1578 s = '# arch.info file generated by genmap for %s\n' % self.name … … 1594 1599 # search a RAM 1595 1600 for pseg in cluster.psegs: 1596 if ( pseg.segtype == 'RAM' ): 1601 if ( pseg.segtype == 'RAM' ): 1597 1602 ram = pseg 1598 1603 nb_devs += 1 … … 1605 1610 1606 1611 for periph in cluster.periphs: 1607 if ( periph.ptype == 'XCU' ): 1612 if ( periph.ptype == 'XCU' ): 1608 1613 # scan irqs 1609 1614 for irq in periph.irqs: … … 1614 1619 # Build the cluster description 1615 1620 s += '[CLUSTER]\n' 1616 s += ' CID=%d\n' % cluster_id 1617 s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y) 1621 s += ' CID=%d\n' % cluster_id 1622 s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y) 1618 1623 s += ' CPU_NR=%d\n' % nb_cpus 1619 1624 s += ' DEV_NR=%d\n' % nb_devs 1620 1625 1621 1626 1622 1627 # Handling RAM when cluster contain a RAM … … 1625 1630 size = ram.size 1626 1631 irqid = -1 1627 s += ' DEVID=RAM' 1632 s += ' DEVID=RAM' 1628 1633 s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size ) 1629 1634 … … 1633 1638 size = periph.pseg.size 1634 1639 1635 if ( periph.ptype == 'XCU' ): 1636 1637 s += ' DEVID=XICU' 1640 if ( periph.ptype == 'XCU' ): 1641 1642 s += ' DEVID=XICU' 1638 1643 s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size ) 1639 1644 1640 elif ( (periph.ptype == 'TTY') 1645 elif ( (periph.ptype == 'TTY') 1641 1646 and (tty_irq_id != None) ): 1642 1647 1643 s += ' DEVID=TTY' 1648 s += ' DEVID=TTY' 1644 1649 s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id ) 1645 1650 1646 elif ( (periph.ptype == 'DMA') 1651 elif ( (periph.ptype == 'DMA') 1647 1652 and (dma_irq_id != None) ): 1648 1653 … … 1658 1663 and (bdv_irq_id != None) ): 1659 1664 1660 s += ' DEVID=BLKDEV' 1665 s += ' DEVID=BLKDEV' 1661 1666 s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id ) 1662 1667 1663 1668 elif ( periph.ptype == 'PIC' ): 1664 1669 1665 s += ' DEVID=IOPIC' 1670 s += ' DEVID=IOPIC' 1666 1671 s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size ) 1667 1672 … … 1671 1676 print '# peripheral type %s/%s not supported yet\n' \ 1672 1677 % ( periph.ptype, periph.subtype ) 1673 1678 1674 1679 cluster_id += 1 1675 1680 … … 1689 1694 ########################################################################################### 1690 1695 def __init__( self, 1691 x, 1696 x, 1692 1697 y ): 1693 1698 1694 1699 self.index = 0 # global index (set by Mapping constructor) 1695 1700 self.x = x # x coordinate … … 1706 1711 1707 1712 s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y) 1708 for pseg in self.psegs: s += pseg.xml() 1713 for pseg in self.psegs: s += pseg.xml() 1709 1714 for proc in self.procs: s += proc.xml() 1710 for copr in self.coprocs: s += copr.xml() 1711 for peri in self.periphs: s += peri.xml() 1715 for copr in self.coprocs: s += copr.xml() 1716 for peri in self.periphs: s += peri.xml() 1712 1717 s += ' </cluster>\n' 1713 1718 … … 1726 1731 sys.exit(1) 1727 1732 1728 # compute global index for first pseg 1733 # compute global index for first pseg 1729 1734 if ( len(self.psegs) > 0 ): 1730 1735 pseg_id = self.psegs[0].index … … 1732 1737 pseg_id = 0 1733 1738 1734 # compute global index for first proc 1739 # compute global index for first proc 1735 1740 if ( len(self.procs) > 0 ): 1736 1741 proc_id = self.procs[0].index … … 1738 1743 proc_id = 0 1739 1744 1740 # compute global index for first coproc 1745 # compute global index for first coproc 1741 1746 if ( len(self.coprocs) > 0 ): 1742 1747 coproc_id = self.coprocs[0].index … … 1744 1749 coproc_id = 0 1745 1750 1746 # compute global index for first periph 1751 # compute global index for first periph 1747 1752 if ( len(self.periphs) > 0 ): 1748 1753 periph_id = self.periphs[0].index … … 1761 1766 byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number of periphs in cluster 1762 1767 byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index 1763 1768 1764 1769 if ( verbose ): 1765 1770 print 'nb_psegs = %d' % len( self.psegs ) … … 1777 1782 class Vspace( object ): 1778 1783 ########################################################################################### 1779 def __init__( self, 1780 name, 1784 def __init__( self, 1785 name, 1781 1786 startname ): 1782 1787 … … 1784 1789 self.name = name # vspace name 1785 1790 self.startname = startname # name of vobj containing the start_vector 1786 self.vsegs = [] 1791 self.vsegs = [] 1787 1792 self.tasks = [] 1788 1793 … … 1794 1799 s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname ) 1795 1800 for vseg in self.vsegs: s += vseg.xml() 1796 for task in self.tasks: s += task.xml() 1801 for task in self.tasks: s += task.xml() 1797 1802 s += ' </vspace>\n' 1798 1803 … … 1820 1825 % ( self.startname, self.name ) 1821 1826 sys.exit(1) 1822 1827 1823 1828 # compute first vseg, vobj, task global index 1824 1829 first_vseg_id = self.vsegs[0].index 1825 1830 first_vobj_id = self.vsegs[0].vobjs[0].index 1826 1831 first_task_id = self.tasks[0].index 1827 1832 1828 1833 # compute number of vobjs, tasks, vsegs 1829 1834 nb_vsegs = len( self.vsegs ) … … 1835 1840 byte_stream = bytearray() 1836 1841 byte_stream += mapping.str2bytes( 32, self.name ) # vspace name 1837 byte_stream += mapping.int2bytes( 4, vobj_start_id ) # vobj start_vector 1842 byte_stream += mapping.int2bytes( 4, vobj_start_id ) # vobj start_vector 1838 1843 byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs 1839 1844 byte_stream += mapping.int2bytes( 4, nb_vobjs ) # number of vobjs … … 1857 1862 class Task( object ): 1858 1863 ########################################################################################### 1859 def __init__( self, 1860 name, 1861 trdid, 1862 x, 1864 def __init__( self, 1865 name, 1866 trdid, 1867 x, 1863 1868 y, 1864 p, 1865 stackname, 1866 heapname, 1869 p, 1870 stackname, 1871 heapname, 1867 1872 startid, 1868 usetty = False, 1869 usenic = False, 1873 usetty = False, 1874 usenic = False, 1870 1875 usecma = False, 1871 usehba = False, 1876 usehba = False, 1872 1877 usetim = False ): 1873 1878 … … 1875 1880 self.name = name # tsk name 1876 1881 self.trdid = trdid # task index (unique in vspace) 1877 self.x = x # cluster x coordinate 1878 self.y = y # cluster y coordinate 1879 self.p = p # processor local index 1882 self.x = x # cluster x coordinate 1883 self.y = y # cluster y coordinate 1884 self.p = p # processor local index 1880 1885 self.stackname = stackname # name of vobj containing the stack 1881 1886 self.heapname = heapname # name of vobj containing the heap … … 1899 1904 s += ' heapname="%s"' % self.heapname 1900 1905 s += ' startid="%d"' % self.startid 1901 if self.usetty != 0: s += ' usetty="1"' 1902 if self.usenic != 0: s += ' usenic="1"' 1903 if self.usecma != 0: s += ' usehba="1"' 1904 if self.usehba != 0: s += ' usehba="1"' 1905 if self.usetim != 0: s += ' usehba="1"' 1906 s += ' />\n' 1906 if self.usetty != 0: s += ' usetty="1"' 1907 if self.usenic != 0: s += ' usenic="1"' 1908 if self.usecma != 0: s += ' usehba="1"' 1909 if self.usehba != 0: s += ' usehba="1"' 1910 if self.usetim != 0: s += ' usehba="1"' 1911 s += ' />\n' 1907 1912 1908 1913 return s 1909 1914 1910 1915 ##################################################### 1911 def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task 1916 def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task 1912 1917 1913 1918 if ( verbose ): … … 1927 1932 for vseg in vspace.vsegs: 1928 1933 if ( vseg.vobjs[0].name == self.stackname ): 1929 vobj_stack_id = vseg.vobjs[0].index 1934 vobj_stack_id = vseg.vobjs[0].index 1930 1935 if ( vobj_stack_id == 0xFFFFFFFF ): 1931 1936 print '[genmap error] in Task.cbin() : stackname %s not found for task %s in vspace %s' \ … … 1950 1955 byte_stream += mapping.int2bytes( 4, vobj_stack_id ) # stack vobj local index 1951 1956 byte_stream += mapping.int2bytes( 4, vobj_heap_id ) # heap vobj local index 1952 byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector 1953 byte_stream += mapping.int2bytes( 4, self.usetty ) # TTY channel required 1954 byte_stream += mapping.int2bytes( 4, self.usenic ) # NIC channel required 1955 byte_stream += mapping.int2bytes( 4, self.usecma ) # CMA channel required 1956 byte_stream += mapping.int2bytes( 4, self.usehba ) # IOC channel required 1957 byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector 1958 byte_stream += mapping.int2bytes( 4, self.usetty ) # TTY channel required 1959 byte_stream += mapping.int2bytes( 4, self.usenic ) # NIC channel required 1960 byte_stream += mapping.int2bytes( 4, self.usecma ) # CMA channel required 1961 byte_stream += mapping.int2bytes( 4, self.usehba ) # IOC channel required 1957 1962 byte_stream += mapping.int2bytes( 4, self.usetim ) # TIM channel required 1958 1963 … … 1960 1965 print 'clusterid = %d' % cluster_id 1961 1966 print 'lpid = %d' % self.p 1962 print 'trdid = %d' % self.trdid 1963 print 'stackid = %d' % vobj_stack_id 1964 print 'heapid = %d' % vobj_heap_id 1965 print 'startid = %d' % self.startid 1966 1967 print 'trdid = %d' % self.trdid 1968 print 'stackid = %d' % vobj_stack_id 1969 print 'heapid = %d' % vobj_heap_id 1970 print 'startid = %d' % self.startid 1971 1967 1972 return byte_stream 1968 1973 … … 1970 1975 class Vseg( object ): 1971 1976 ########################################################################################### 1972 def __init__( self, 1973 name, 1974 vbase, 1975 mode, 1976 x, 1977 y, 1978 psegname, 1977 def __init__( self, 1978 name, 1979 vbase, 1980 mode, 1981 x, 1982 y, 1983 psegname, 1979 1984 identity = False, 1980 1985 local = False ): … … 1984 1989 self.index = 0 # global index ( set by addVseg() ) 1985 1990 self.name = name # vseg name 1986 self.vbase = vbase & 0xFFFFFFFF # virtual base address in vspace 1991 self.vbase = vbase & 0xFFFFFFFF # virtual base address in vspace 1987 1992 self.mode = mode # CXWU access rights 1988 self.x = x # x coordinate of destination cluster 1993 self.x = x # x coordinate of destination cluster 1989 1994 self.y = y # y coordinate of destination cluster 1990 1995 self.psegname = psegname # name of pseg in destination cluster … … 1995 2000 1996 2001 ################ 1997 def xml( self ): # xml for one vseg 2002 def xml( self ): # xml for one vseg 1998 2003 1999 2004 s = ' <vseg name="%s" vbase="0x%x" mode="%s" x="%d" y="%d" psegname="%s"' \ … … 2033 2038 # compute numerical value for mode 2034 2039 mode_id = 0xFFFFFFFF 2035 for x in xrange( len(VSEGMODES) ): 2036 if ( self.mode == VSEGMODES[x] ): 2040 for x in xrange( len(VSEGMODES) ): 2041 if ( self.mode == VSEGMODES[x] ): 2037 2042 mode_id = x 2038 2043 if ( mode_id == 0xFFFFFFFF ): … … 2041 2046 2042 2047 # compute vobj_id 2043 vobj_id = self.vobjs[0].index 2048 vobj_id = self.vobjs[0].index 2044 2049 2045 2050 byte_stream = bytearray() 2046 byte_stream += mapping.str2bytes( 32, self.name ) # vseg name 2051 byte_stream += mapping.str2bytes( 32, self.name ) # vseg name 2047 2052 byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address 2048 2053 byte_stream += mapping.int2bytes( 8, 0 ) # physical base address … … 2051 2056 byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags 2052 2057 byte_stream += mapping.int2bytes( 4, len(self.vobjs) ) # number of vobjs in vseg 2053 byte_stream += mapping.int2bytes( 4, vobj_id ) # first vobj global index 2058 byte_stream += mapping.int2bytes( 4, vobj_id ) # first vobj global index 2054 2059 byte_stream += mapping.int2bytes( 4, 0 ) # linked list of vsegs on same pseg 2055 2060 byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero … … 2063 2068 print 'mode = %s' % self.mode 2064 2069 print 'nb_vobjs = %d' % len(self.vobjs) 2065 print 'vobj_id = %d' % vobj_id 2066 2070 print 'vobj_id = %d' % vobj_id 2071 2067 2072 return byte_stream 2068 2073 … … 2071 2076 ########################################################################################### 2072 2077 def __init__( self, 2073 name, 2074 length, 2075 vtype, 2076 binpath = '', 2077 align = 0, 2078 name, 2079 length, 2080 vtype, 2081 binpath = '', 2082 align = 0, 2078 2083 init = 0 ): 2079 2084 … … 2118 2123 # compute numerical value for vtype 2119 2124 vtype_int = 0xFFFFFFFF 2120 for x in xrange( len(VOBJTYPES) ): 2121 if ( self.vtype == VOBJTYPES[x] ): 2125 for x in xrange( len(VOBJTYPES) ): 2126 if ( self.vtype == VOBJTYPES[x] ): 2122 2127 vtype_int = x 2123 2128 if ( vtype_int == 0xFFFFFFFF ): … … 2126 2131 2127 2132 byte_stream = bytearray() 2128 byte_stream += mapping.str2bytes( 32, self.name ) # vobj name 2133 byte_stream += mapping.str2bytes( 32, self.name ) # vobj name 2129 2134 byte_stream += mapping.str2bytes( 64, self.binpath ) # pathname for .elf file 2130 2135 byte_stream += mapping.int2bytes( 4 , vtype_int ) # vobj type … … 2134 2139 byte_stream += mapping.int2bytes( 8 , 0 ) # physical base address 2135 2140 byte_stream += mapping.int2bytes( 4 , self.init ) # init value 2136 2141 2137 2142 if ( verbose ): 2138 2143 print 'binpath = %s' % self.binpath 2139 2144 print 'type = %s' % self.vtype 2140 2145 print 'length = %x' % self.length 2141 2146 2142 2147 return byte_stream 2143 2148 … … 2146 2151 ########################################################################################### 2147 2152 def __init__( self, 2148 x, 2149 y, 2153 x, 2154 y, 2150 2155 lpid ): 2151 2156 … … 2158 2163 2159 2164 ################ 2160 def xml( self ): # xml for a processor 2165 def xml( self ): # xml for a processor 2161 2166 return ' <proc index="%d" />\n' % (self.lpid) 2162 2167 … … 2175 2180 byte_stream = bytearray() 2176 2181 byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index 2177 2182 2178 2183 return byte_stream 2179 2184 … … 2181 2186 class Pseg ( object ): 2182 2187 ########################################################################################### 2183 def __init__( self, 2184 name, 2185 base, 2186 size, 2188 def __init__( self, 2189 name, 2190 base, 2191 size, 2187 2192 x, 2188 2193 y, … … 2195 2200 self.base = base # physical base address 2196 2201 self.size = size # segment size (bytes) 2197 self.x = x # cluster x coordinate 2198 self.y = y # cluster y coordinate 2202 self.x = x # cluster x coordinate 2203 self.y = y # cluster y coordinate 2199 2204 self.segtype = segtype # RAM / PERI (defined in mapping_info.h) 2200 2205 2201 2206 return 2202 2207 2203 2208 ################ 2204 2209 def xml( self ): # xml for a pseg … … 2219 2224 % (self.index, expected ) 2220 2225 sys.exit(1) 2221 2226 2222 2227 # compute numerical value for segtype 2223 2228 segtype_int = 0xFFFFFFFF 2224 for x in xrange( len(PSEGTYPES) ): 2225 if ( self.segtype == PSEGTYPES[x] ): 2229 for x in xrange( len(PSEGTYPES) ): 2230 if ( self.segtype == PSEGTYPES[x] ): 2226 2231 segtype_int = x 2227 2232 if ( segtype_int == 0xFFFFFFFF ): … … 2230 2235 2231 2236 byte_stream = bytearray() 2232 byte_stream += mapping.str2bytes( 32, self.name ) # pseg name 2237 byte_stream += mapping.str2bytes( 32, self.name ) # pseg name 2233 2238 byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address 2234 2239 byte_stream += mapping.int2bytes( 8 , self.size ) # segment length 2235 2240 byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type 2236 2241 byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index 2237 byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs 2242 byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs 2238 2243 2239 2244 if ( verbose ): … … 2241 2246 print 'size = %x' % self.size 2242 2247 print 'type = %s' % self.segtype 2243 2248 2244 2249 return byte_stream 2245 2250 … … 2247 2252 class Periph ( object ): 2248 2253 ########################################################################################### 2249 def __init__( self, 2254 def __init__( self, 2250 2255 pseg, # associated pseg 2251 2256 ptype, # peripheral type … … 2259 2264 2260 2265 self.index = 0 # global index ( set by addPeriph() ) 2261 self.channels = channels 2262 self.ptype = ptype 2263 self.subtype = subtype 2266 self.channels = channels 2267 self.ptype = ptype 2268 self.subtype = subtype 2264 2269 self.arg = arg 2265 2270 self.pseg = pseg … … 2305 2310 # compute numerical value for ptype 2306 2311 ptype_id = 0xFFFFFFFF 2307 for x in xrange( len(PERIPHTYPES) ): 2312 for x in xrange( len(PERIPHTYPES) ): 2308 2313 if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x 2309 2314 if ( ptype_id == 0xFFFFFFFF ): … … 2313 2318 # compute numerical value for subtype 2314 2319 subtype_id = 0xFFFFFFFF 2315 for x in xrange( len(PERIPHSUBTYPES) ): 2320 for x in xrange( len(PERIPHSUBTYPES) ): 2316 2321 if ( self.subtype == PERIPHSUBTYPES[x] ): subtype_id = x 2317 2322 2318 2323 # compute 2319 2324 byte_stream = bytearray() 2320 byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type 2325 byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type 2321 2326 byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype 2322 byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index 2327 byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index 2323 2328 byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels 2324 2329 byte_stream += mapping.int2bytes( 4 , self.arg ) # optionnal argument 2325 byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs 2326 byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index 2330 byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs 2331 byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index 2327 2332 2328 2333 if ( verbose ): … … 2330 2335 print 'pseg_id = %d' % pseg_id 2331 2336 print 'nb_irqs = %d' % len( self.irqs ) 2332 print 'irq_id = %d' % irq_id 2337 print 'irq_id = %d' % irq_id 2333 2338 return byte_stream 2334 2339 … … 2336 2341 class Irq ( object ): 2337 2342 ########################################################################################### 2338 def __init__( self, 2343 def __init__( self, 2339 2344 irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only) 2340 2345 srcid, # input IRQ index (for XCU or PIC) … … 2347 2352 2348 2353 self.index = 0 # global index ( set by addIrq() ) 2349 self.irqtype = irqtype # IRQ type 2354 self.irqtype = irqtype # IRQ type 2350 2355 self.srcid = srcid # source IRQ index 2351 self.isrtype = isrtype # ISR type 2356 self.isrtype = isrtype # ISR type 2352 2357 self.channel = channel # channel index (for multi-channels ISR) 2353 2358 return … … 2363 2368 2364 2369 if ( verbose ): 2365 print '*** cbin for irq[%d]' % (self.index) 2370 print '*** cbin for irq[%d]' % (self.index) 2366 2371 2367 2372 # check index … … 2374 2379 irqtype_id = 0xFFFFFFFF 2375 2380 for x in xrange( len(IRQTYPES) ): 2376 if ( self.irqtype == IRQTYPES[x] ): 2381 if ( self.irqtype == IRQTYPES[x] ): 2377 2382 irqtype_id = x 2378 2383 if ( irqtype_id == 0xFFFFFFFF ): … … 2382 2387 # compute numerical value for isrtype 2383 2388 isrtype_id = 0xFFFFFFFF 2384 for x in xrange( len(ISRTYPES) ): 2385 if ( self.isrtype == ISRTYPES[x] ): 2389 for x in xrange( len(ISRTYPES) ): 2390 if ( self.isrtype == ISRTYPES[x] ): 2386 2391 isrtype_id = x 2387 2392 if ( isrtype_id == 0xFFFFFFFF ): … … 2408 2413 class Coproc ( object ): 2409 2414 ########################################################################################### 2410 def __init__( self, 2411 pseg ): # associated pseg 2415 def __init__( self, 2416 pseg ): # associated pseg 2412 2417 2413 2418 self.index = 0 # global index value set by addCoproc() … … 2418 2423 2419 2424 ################ 2420 def xml( self ): # xml for Coproc 2425 def xml( self ): # xml for Coproc 2421 2426 2422 2427 print '[genmap error] in Coproc.xml() : not defined yet' 2423 2428 sys.exit(1) 2424 2429 2425 return 2430 return 2426 2431 2427 2432 ############################################# … … 2445 2450 byte_stream = bytearray() 2446 2451 byte_stream += mapping.str2bytes( 32, self.pseg.name ) # probablement inutile (AG) 2447 byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index 2448 byte_stream += mapping.int2bytes( 4 , len( self.ports ) ) # number of input irqs 2449 byte_stream += mapping.int2bytes( 4 , port_id ) # first port global index 2450 2452 byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index 2453 byte_stream += mapping.int2bytes( 4 , len( self.ports ) ) # number of input irqs 2454 byte_stream += mapping.int2bytes( 4 , port_id ) # first port global index 2455 2451 2456 if ( verbose ): 2452 2457 print 'irqtype = %s' % self.irqtype … … 2454 2459 print 'nb_ports = %d' % len( self.ports ) 2455 2460 print 'port_id %d' % port_id 2456 2461 2457 2462 return byte_stream 2458 2463 … … 2460 2465 class Cpport ( object ): 2461 2466 ########################################################################################### 2462 def __init__( self, 2463 direction, 2464 vspacename, 2467 def __init__( self, 2468 direction, 2469 vspacename, 2465 2470 mwmrname ): 2466 2471 … … 2478 2483 sys.exit(1) 2479 2484 2480 return 2485 return 2481 2486 2482 2487 ############################################# … … 2501 2506 vspace_id = 0xFFFFFFFF 2502 2507 for vspace in mapping.vspaces: 2503 if ( self.vspacename == vspace.name ): 2508 if ( self.vspacename == vspace.name ): 2504 2509 vspace_id = vspace.index 2505 2510 if (vspace_id == 0xFFFFFFFF): … … 2512 2517 for vseg in mapping.vspace[vspace_id].vsegs: 2513 2518 for vobj in vseg.vobjs: 2514 if (self.mwmrname == vobj.name): 2519 if (self.mwmrname == vobj.name): 2515 2520 mwmr_id = vobj.index 2516 2521 if (mwmr_id == 0xFFFFFFFF): … … 2520 2525 2521 2526 byte_stream = bytearray() 2522 byte_stream += mapping.int2bytes( 4 , dir_int ) # pseg global index 2523 byte_stream += mapping.int2bytes( 4 , vspace_id ) # vspace global index 2524 byte_stream += mapping.int2bytes( 4 , mwmr_id ) # mwmr vobj global index 2525 2527 byte_stream += mapping.int2bytes( 4 , dir_int ) # pseg global index 2528 byte_stream += mapping.int2bytes( 4 , vspace_id ) # vspace global index 2529 byte_stream += mapping.int2bytes( 4 , mwmr_id ) # mwmr vobj global index 2530 2526 2531 if ( verbose ): 2527 2532 print 'direction = %s' % self.direction
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