Changeset 481 for soft/giet_vm/giet_drivers/nic_driver.h

Timestamp:

Jan 1, 2015, 8:23:48 PM (9 years ago)

Author:

alain

Message:

1) The NIC, IOC, DMA and HBA drivers have been adapted to support the new _v2p_translate() function prototype (returns void).
2) The _mmc_inval() and _mmc_sync() functions does not use anymore the hard lock in the MMC, but use a soft spin_lock.
3) The NIC driver does not use anymore the GIET_NIC_BUFSIZE, GIET_NIC_NBUFS, and GIET_NIC_TIMEOUT parameters (removed from giet_config.h file).
4) The NIC driver registers map has been modified to support 64 bytes buffer descriptors for chained buffers.

File:

• soft/giet_vm/giet_drivers/nic_driver.h (modified) (1 diff)

soft/giet_vm/giet_drivers/nic_driver.h

@@ -76 +76 @@
 };
 
-/////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
 //            Channel Addressable Registers
-// A container descriptor has the following form: 
-// LOW WORD  : 32 LSB bits of the container physical base address     
-// HIGH WORD : 16 MSB bits of the container physical base address + status (bit 31)  
-/////////////////////////////////////////////////////////////////////////////////////
+// A buffer descriptor occupies 64 bytes, but only 8 bytes (two 32 bits words) are useful:
+// LOW WORD   contains the 32 LSB bits of the buffer paddr                
+// HIGH WORD  contains the 16 MSB bits of the buffer paddr, plus status (bit 31)
+//////////////////////////////////////////////////////////////////////////////////////////////
+
 enum SoclibMultiNicChannelRegisters 
 {
     NIC_RX_DESC_LO_0          = 0,   // RX_0 descriptor low word         (Read/Write)
     NIC_RX_DESC_HI_0          = 1,   // RX_0 descriptor high word        (Read/Write)
-    NIC_RX_DESC_LO_1          = 2,   // RX_1 descriptor low word         (Read/Write)
-    NIC_RX_DESC_HI_1          = 3,   // RX_1 descriptor high word        (Read/Write) 
-    NIC_TX_DESC_LO_0          = 4,   // TX_0 descriptor low word         (Read/Write)
-    NIC_TX_DESC_HI_0          = 5,   // TX_0 descriptor high word        (Read/Write) 
-    NIC_TX_DESC_LO_1          = 6,   // TX_1 descriptor low word         (Read/Write)
-    NIC_TX_DESC_HI_1          = 7,   // TX_1 descriptor high word        (Read/Write) 
-    NIC_MAC_4                 = 8,   // channel mac address 32 LSB bits  (Read Only)
-    NIC_MAC_2                 = 9,   // channel mac address 16 LSB bits  (Read Only)
-    NIC_RX_RUN                = 10,  // RX packets can be received       (write_only)
-    NIC_TX_RUN                = 11,  // TX packets can be transmitted    (write_only)
+    NIC_RX_DESC_LO_1          = 16,  // RX_1 descriptor low word         (Read/Write)
+    NIC_RX_DESC_HI_1          = 17,  // RX_1 descriptor high word        (Read/Write) 
+    NIC_TX_DESC_LO_0          = 32,  // TX_0 descriptor low word         (Read/Write)
+    NIC_TX_DESC_HI_0          = 33,  // TX_0 descriptor high word        (Read/Write) 
+    NIC_TX_DESC_LO_1          = 48,  // TX_1 descriptor low word         (Read/Write)
+    NIC_TX_DESC_HI_1          = 49,  // TX_1 descriptor high word        (Read/Write) 
+    NIC_MAC_4                 = 64,  // channel mac address 32 LSB bits  (Read Only)
+    NIC_MAC_2                 = 65,  // channel mac address 16 LSB bits  (Read Only)
+    NIC_RX_RUN                = 66,  // RX packets can be received       (write_only)
+    NIC_TX_RUN                = 67,  // TX packets can be transmitted    (write_only)
 };