Changeset 490 for soft/giet_vm/giet_common/utils.c

Timestamp:

Jan 16, 2015, 1:24:18 PM (10 years ago)

Author:

haoliu

Message:

Implemented a new way to construct the ptabs in boot. In the map.bin file,
each physical segment in cluster[x][y] is handled by the processor[x][y][0]. So
the constrcuting of page table is done in parrallel by all the
processor[x][y][0] at the same time.

This way spents less time than the constructing sequential by one processor(
the processor[0][0][0])

File:

• soft/giet_vm/giet_common/utils.c (modified) (1 diff)

soft/giet_vm/giet_common/utils.c

@@ -409 +409 @@
 }
 
-
+///////////////////////////////////////////////////////////////////////////////////
+//                      barrier functions
+///////////////////////////////////////////////////////////////////////////////////
+void _barrier_init( _giet_barrier_t* barrier, 
+                   unsigned int    ntasks ) 
+{
+    barrier->ntasks = ntasks;
+    barrier->count  = ntasks;
+    barrier->sense  = 0;
+
+    asm volatile ("sync" ::: "memory");
+}
+
+////////////////////////////////////////////
+void _barrier_wait( _giet_barrier_t* barrier ) 
+{
+
+    // compute expected sense value 
+    unsigned int expected;
+    if ( barrier->sense == 0 ) expected = 1;
+    else                       expected = 0;
+
+    // parallel decrement barrier counter using atomic instructions LL/SC
+    // - input : pointer on the barrier counter (pcount)
+    // - output : counter value (count)
+    volatile unsigned int* pcount  = (unsigned int *)&barrier->count;
+    volatile unsigned int  count    = 0;  // avoid a warning
+
+    asm volatile( "addu   $2,     %1,        $0      \n"
+                  "barrier_llsc:                     \n"
+                  "ll     $8,     0($2)              \n"
+                  "addi   $9,     $8,        -1      \n"
+                  "sc     $9,     0($2)              \n"
+                  "beqz   $9,     barrier_llsc       \n"
+                  "addu   %0,     $8,        $0      \n"
+                  : "=r" (count)
+                  : "r" (pcount)
+                  : "$2", "$8", "$9", "memory" );
+
+    // the last task re-initializes count and toggle sense,
+    // waking up all other waiting tasks
+    if (count == 1)   // last task
+    {
+        barrier->count = barrier->ntasks;
+        barrier->sense = expected;
+    }
+    else              // other tasks busy waiting the sense flag
+    {
+        // polling sense flag
+        // input: pointer on the sens flag (psense)
+        // input: expected sense value (expected)
+        volatile unsigned int* psense  = (unsigned int *)&barrier->sense;
+        asm volatile ( "barrier_sense:                   \n"
+                       "lw    $3,   0(%0)                \n"
+                       "bne   $3,   %1,    barrier_sense \n"
+                       :
+                       : "r"(psense), "r"(expected)
+                       : "$3" );
+    }
+
+    asm volatile ("sync" ::: "memory");
+}
+
+///////////////////////////////////////////////////////////////////////////////////
+//                      Locks access functions
+///////////////////////////////////////////////////////////////////////////////////
+
+///////////////////////////////////
+void _get_lock( _giet_lock_t* lock ) 
+{
+    register unsigned int* plock = &(lock->value);
+
+#if NO_HARD_CC
+
+    register unsigned int delay  = (_get_proctime() ^ _get_procid() << 4) & 0xFF;
+    if (delay == 0) delay = 0x80;
+
+    asm volatile (
+            "_lock_llsc:             \n"
+            "    ll   $2,    0(%0)       \n" /* $2 <= lock current value         */
+            "    bnez $2,    _lock_delay \n" /* delay if lock already taken      */
+            "    li   $3,    1           \n" /* $3 <= argument for sc            */
+            "    sc   $3,    0(%0)       \n" /* try to set lock                  */
+            "    bnez $3,    _lock_ok    \n" /* exit if atomic                   */
+            "    _lock_delay:            \n"
+            "    move $4,    %1          \n" /* $4 <= delay                      */
+            "    _lock_loop:             \n"
+            "    addi $4,    $4,    -1   \n" /* $4 <= $4 - 1                     */
+            "    bnez $4,    _lock_loop  \n" /* test end delay                   */
+            "    nop                     \n"
+            "    j           _lock_llsc  \n" /* retry                            */
+            "    nop                     \n"
+            "    _lock_ok:               \n"
+            :
+            :"r"(plock), "r"(delay)
+            :"$2", "$3", "$4", "memory");
+#else
+
+    asm volatile (
+            "_lock_llsc:                 \n"
+            "    lw   $2,    0(%0)       \n" /* $2 <= lock current value         */
+            "    bnez $2,    _lock_llsc  \n" /* retry if lock already taken      */
+            "    nop                     \n"
+            "    ll   $2,    0(%0)       \n" /* ll_buffer <= lock current value  */
+            "    bnez $2,    _lock_llsc  \n" /* retry if lock already taken      */
+            "    li   $3,    1           \n" /* $3 <= argument for sc            */
+            "    sc   $3,    0(%0)       \n" /* try to set lock                  */
+            "    beqz $3,    _lock_llsc  \n" /* retry if sc failure              */
+            "    nop                     \n"
+            :
+            :"r"(plock)
+            :"$2", "$3", "memory");
+#endif
+
+}
+
+///////////////////////////////////////
+void _release_lock( _giet_lock_t* lock ) 
+{
+    asm volatile ( "sync\n" ::: "memory" ); 
+    // sync is necessary because of the TSAR consistency model 
+    lock->value = 0;
+}
 
 ////////////////////////////////////////////////////////////////////////////////////