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Changeset 523 for soft/giet_vm/giet_common/utils.c
- Timestamp:
- Mar 10, 2015, 3:21:01 PM (10 years ago)
- File:
-
- 1 edited
-
soft/giet_vm/giet_common/utils.c (modified) (16 diffs)
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soft/giet_vm/giet_common/utils.c
r514 r523 1 /////////////////////////////////////////////////////////////////////////// ////////1 /////////////////////////////////////////////////////////////////////////// 2 2 // File : utils.c 3 3 // Date : 18/10/2013 4 4 // Author : alain greiner 5 5 // Copyright (c) UPMC-LIP6 6 /////////////////////////////////////////////////////////////////////////// ////////6 /////////////////////////////////////////////////////////////////////////// 7 7 // The utils.c and utils.h files are part of the GIET-VM nano-kernel. 8 /////////////////////////////////////////////////////////////////////////// ////////8 /////////////////////////////////////////////////////////////////////////// 9 9 10 10 #include <utils.h> … … 16 16 #include <ctx_handler.h> 17 17 18 // This globalvariable is allocated in the boot.c file or in kernel_init.c file18 // This variable is allocated in the boot.c file or in kernel_init.c file 19 19 extern static_scheduler_t* _schedulers[X_SIZE][Y_SIZE][NB_PROCS_MAX]; 20 20 21 /////////////////////////////////////////////////////////////////////////// ////////21 /////////////////////////////////////////////////////////////////////////// 22 22 // CP0 registers access functions 23 /////////////////////////////////////////////////////////////////////////// ////////23 /////////////////////////////////////////////////////////////////////////// 24 24 25 25 ///////////////////////// … … 119 119 120 120 121 /////////////////////////////////////////////////////////////////////////// ////////121 /////////////////////////////////////////////////////////////////////////// 122 122 // CP2 registers access functions 123 /////////////////////////////////////////////////////////////////////////// ////////123 /////////////////////////////////////////////////////////////////////////// 124 124 125 125 //////////////////////////// … … 165 165 166 166 167 /////////////////////////////////////////////////////////////////////////// /167 /////////////////////////////////////////////////////////////////////////// 168 168 // Physical addressing related functions 169 /////////////////////////////////////////////////////////////////////////// /169 /////////////////////////////////////////////////////////////////////////// 170 170 171 171 /////////////////////////////////////////////////////// … … 179 179 _it_disable(&sr); 180 180 181 asm volatile( "mfc2 $2, $1 \n"/* $2 <= MMU_MODE */182 "andi $3, $2, 0xb\n"183 "mtc2 $3, $1 \n"/* DTLB off */184 185 "mtc2 %2, $24 \n"/* PADDR_EXT <= msb */186 "lw %0, 0(%1) \n"/* value <= *paddr */187 "mtc2 $0, $24 \n"/* PADDR_EXT <= 0 */188 189 "mtc2 $2, $1 \n"/* restore MMU_MODE */181 asm volatile( "mfc2 $2, $1 \n" /* $2 <= MMU_MODE */ 182 "andi $3, $2, 0xb \n" 183 "mtc2 $3, $1 \n" /* DTLB off */ 184 185 "mtc2 %2, $24 \n" /* PADDR_EXT <= msb */ 186 "lw %0, 0(%1) \n" /* value <= *paddr */ 187 "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ 188 189 "mtc2 $2, $1 \n" /* restore MMU_MODE */ 190 190 : "=r" (value) 191 191 : "r" (lsb), "r" (msb) … … 205 205 _it_disable(&sr); 206 206 207 asm volatile( "mfc2 $2, $1 \n"/* $2 <= MMU_MODE */208 "andi $3, $2, 0xb\n"209 "mtc2 $3, $1 \n"/* DTLB off */210 211 "mtc2 %2, $24 \n"/* PADDR_EXT <= msb */212 "sw %0, 0(%1) \n"/* *paddr <= value */213 "mtc2 $0, $24 \n"/* PADDR_EXT <= 0 */214 215 "mtc2 $2, $1 \n"/* restore MMU_MODE */216 "sync 207 asm volatile( "mfc2 $2, $1 \n" /* $2 <= MMU_MODE */ 208 "andi $3, $2, 0xb \n" 209 "mtc2 $3, $1 \n" /* DTLB off */ 210 211 "mtc2 %2, $24 \n" /* PADDR_EXT <= msb */ 212 "sw %0, 0(%1) \n" /* *paddr <= value */ 213 "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ 214 215 "mtc2 $2, $1 \n" /* restore MMU_MODE */ 216 "sync \n" 217 217 : 218 218 : "r" (value), "r" (lsb), "r" (msb) … … 233 233 _it_disable(&sr); 234 234 235 asm volatile( "mfc2 $2, $1 \n"/* $2 <= MMU_MODE */236 "andi $3, $2, 0xb\n"237 "mtc2 $3, $1 \n"/* DTLB off */238 239 "mtc2 %3, $24 \n"/* PADDR_EXT <= msb */240 "lw %0, 0(%2) \n"/* data_lsb <= *paddr */241 "lw %1, 4(%2) \n"/* data_msb <= *paddr+4 */242 "mtc2 $0, $24 \n"/* PADDR_EXT <= 0 */243 244 "mtc2 $2, $1 \n"/* restore MMU_MODE */235 asm volatile( "mfc2 $2, $1 \n" /* $2 <= MMU_MODE */ 236 "andi $3, $2, 0xb \n" 237 "mtc2 $3, $1 \n" /* DTLB off */ 238 239 "mtc2 %3, $24 \n" /* PADDR_EXT <= msb */ 240 "lw %0, 0(%2) \n" /* data_lsb <= *paddr */ 241 "lw %1, 4(%2) \n" /* data_msb <= *paddr+4 */ 242 "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ 243 244 "mtc2 $2, $1 \n" /* restore MMU_MODE */ 245 245 : "=r" (data_lsb), "=r"(data_msb) 246 246 : "r" (addr_lsb), "r" (addr_msb) … … 265 265 _it_disable(&sr); 266 266 267 asm volatile( "mfc2 $2, $1 \n"/* $2 <= MMU_MODE */268 "andi $3, $2, 0xb\n"269 "mtc2 $3, $1 \n"/* DTLB off */270 271 "mtc2 %3, $24 \n"/* PADDR_EXT <= msb */272 "sw %0, 0(%2) \n"/* *paddr <= value */273 "sw %1, 4(%2) \n"/* *paddr+4 <= value */274 "mtc2 $0, $24 \n"/* PADDR_EXT <= 0 */275 276 "mtc2 $2, $1 \n"/* restore MMU_MODE */277 "sync 267 asm volatile( "mfc2 $2, $1 \n" /* $2 <= MMU_MODE */ 268 "andi $3, $2, 0xb \n" 269 "mtc2 $3, $1 \n" /* DTLB off */ 270 271 "mtc2 %3, $24 \n" /* PADDR_EXT <= msb */ 272 "sw %0, 0(%2) \n" /* *paddr <= value */ 273 "sw %1, 4(%2) \n" /* *paddr+4 <= value */ 274 "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ 275 276 "mtc2 $2, $1 \n" /* restore MMU_MODE */ 277 "sync \n" 278 278 : 279 : "r" (data_lsb), "r" (data_msb), "r" (addr_lsb), "r"(addr_msb)279 : "r"(data_lsb),"r"(data_msb),"r"(addr_lsb),"r"(addr_msb) 280 280 : "$2", "$3" ); 281 281 … … 284 284 285 285 //////////////////////////////////////////////////// 286 void _physical_memcpy( unsigned long long dst_paddr, // dest inationbuffer paddr286 void _physical_memcpy( unsigned long long dst_paddr, // dest buffer paddr 287 287 unsigned long long src_paddr, // source buffer paddr 288 288 unsigned int size ) // bytes … … 305 305 _it_disable(&sr); 306 306 307 asm volatile( "mfc2 $2, $1 \n"/* $2 <= current MMU_MODE */308 "andi $3, $2, 0xb \n"/* $3 <= new MMU_MODE */309 "mtc2 $3, $1 \n"/* DTLB off */310 311 "move $4, %5 \n"/* $4 < iter */312 "move $5, %1 \n"/* $5 < src_lsb */313 "move $6, %3 \n"/* $6 < src_lsb */314 315 "ph_memcpy_loop: 316 "mtc2 %2, $24 \n"/* PADDR_EXT <= src_msb */317 "lw %0, 0($5) \n"/* data <= *src_paddr */318 "mtc2 %4, $24 \n"/* PADDR_EXT <= dst_msb */319 "sw %0, 0($6) \n"/* *dst_paddr <= data */320 321 "addi $4, $4, -1 \n"/* iter = iter - 1 */322 "addi $5, $5, 4 \n"/* src_lsb += 4 */323 "addi $6, $6, 4 \n"/* dst_lsb += 4 */307 asm volatile( "mfc2 $2, $1 \n" /* $2 <= current MMU_MODE */ 308 "andi $3, $2, 0xb \n" /* $3 <= new MMU_MODE */ 309 "mtc2 $3, $1 \n" /* DTLB off */ 310 311 "move $4, %5 \n" /* $4 < iter */ 312 "move $5, %1 \n" /* $5 < src_lsb */ 313 "move $6, %3 \n" /* $6 < src_lsb */ 314 315 "ph_memcpy_loop: \n" 316 "mtc2 %2, $24 \n" /* PADDR_EXT <= src_msb */ 317 "lw %0, 0($5) \n" /* data <= *src_paddr */ 318 "mtc2 %4, $24 \n" /* PADDR_EXT <= dst_msb */ 319 "sw %0, 0($6) \n" /* *dst_paddr <= data */ 320 321 "addi $4, $4, -1 \n" /* iter = iter - 1 */ 322 "addi $5, $5, 4 \n" /* src_lsb += 4 */ 323 "addi $6, $6, 4 \n" /* dst_lsb += 4 */ 324 324 "bne $4, $0, ph_memcpy_loop \n" 325 "nop 326 327 "mtc2 $0, $24 \n"/* PADDR_EXT <= 0 */328 "mtc2 $2, $1 \n"/* restore MMU_MODE */325 "nop \n" 326 327 "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ 328 "mtc2 $2, $1 \n" /* restore MMU_MODE */ 329 329 : "=r" (data) 330 : "r" (src_lsb), "r" (src_msb), "r" (dst_lsb), "r"(dst_msb), "r"(iter) 330 : "r"(src_lsb),"r"(src_msb),"r"(dst_lsb), 331 "r"(dst_msb), "r"(iter) 331 332 : "$2", "$3", "$4", "$5", "$6" ); 332 333 … … 335 336 336 337 //////////////////////////////////////////////// 337 void _physical_memset( unsigned long long paddr, // dest inationbuffer paddr338 void _physical_memset( unsigned long long paddr, // dest buffer paddr 338 339 unsigned int size, // bytes 339 340 unsigned int data ) // written value … … 352 353 _it_disable(&sr); 353 354 354 asm volatile( "mfc2 $8, $1 \n"/* $8 <= current MMU_MODE */355 "andi $9, $8, 0xb \n"/* $9 <= new MMU_MODE */356 "mtc2 $9, $1 \n"/* DTLB off */357 "mtc2 %3, $24 \n"/* PADDR_EXT <= msb */358 359 "1: \n"/* set 8 bytes per iter */360 "sw %2, 0(%0) \n"/* *src_paddr = data */361 "sw %2, 4(%0) \n"/* *(src_paddr+4) = data */362 "addi %1, %1, -8 \n"/* size -= 8 */363 "addi %0, %0, 8 \n"/* src_paddr += 8 */364 "bnez %1, 1b \n"/* loop while size != 0 */365 366 "mtc2 $0, $24 \n"/* PADDR_EXT <= 0 */367 "mtc2 $8, $1 \n"/* restore MMU_MODE */355 asm volatile( "mfc2 $8, $1 \n" /* $8 <= current MMU_MODE */ 356 "andi $9, $8, 0xb \n" /* $9 <= new MMU_MODE */ 357 "mtc2 $9, $1 \n" /* DTLB off */ 358 "mtc2 %3, $24 \n" /* PADDR_EXT <= msb */ 359 360 "1: \n" /* set 8 bytes per iter */ 361 "sw %2, 0(%0) \n" /* *src_paddr = data */ 362 "sw %2, 4(%0) \n" /* *(src_paddr+4) = data */ 363 "addi %1, %1, -8 \n" /* size -= 8 */ 364 "addi %0, %0, 8 \n" /* src_paddr += 8 */ 365 "bnez %1, 1b \n" /* loop while size != 0 */ 366 367 "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ 368 "mtc2 $8, $1 \n" /* restore MMU_MODE */ 368 369 : "+r"(lsb), "+r"(size) 369 370 : "r"(data), "r" (msb) … … 409 410 } 410 411 411 /////////////////////////////////////////////////////////////////////////////////// 412 // barrier functions 413 /////////////////////////////////////////////////////////////////////////////////// 414 void _barrier_init( _giet_barrier_t* barrier, 415 unsigned int ntasks ) 416 { 417 barrier->ntasks = ntasks; 418 barrier->count = ntasks; 419 barrier->sense = 0; 420 421 asm volatile ("sync" ::: "memory"); 422 } 423 424 //////////////////////////////////////////// 425 void _barrier_wait( _giet_barrier_t* barrier ) 426 { 427 428 // compute expected sense value 429 unsigned int expected; 430 if ( barrier->sense == 0 ) expected = 1; 431 else expected = 0; 432 433 // parallel decrement barrier counter using atomic instructions LL/SC 434 // - input : pointer on the barrier counter (pcount) 435 // - output : counter value (count) 436 volatile unsigned int* pcount = (unsigned int *)&barrier->count; 437 volatile unsigned int count = 0; // avoid a warning 438 439 asm volatile( "addu $2, %1, $0 \n" 440 "barrier_llsc: \n" 441 "ll $8, 0($2) \n" 442 "addi $9, $8, -1 \n" 443 "sc $9, 0($2) \n" 444 "beqz $9, barrier_llsc \n" 445 "addu %0, $8, $0 \n" 446 : "=r" (count) 447 : "r" (pcount) 448 : "$2", "$8", "$9", "memory" ); 449 450 // the last task re-initializes count and toggle sense, 451 // waking up all other waiting tasks 452 if (count == 1) // last task 453 { 454 barrier->count = barrier->ntasks; 455 barrier->sense = expected; 456 } 457 else // other tasks busy waiting the sense flag 458 { 459 // polling sense flag 460 // input: pointer on the sens flag (psense) 461 // input: expected sense value (expected) 462 volatile unsigned int* psense = (unsigned int *)&barrier->sense; 463 asm volatile ( "barrier_sense: \n" 464 "lw $3, 0(%0) \n" 465 "bne $3, %1, barrier_sense \n" 466 : 467 : "r"(psense), "r"(expected) 468 : "$3" ); 469 } 470 471 asm volatile ("sync" ::: "memory"); 472 } 473 474 /////////////////////////////////////////////////////////////////////////////////// 475 // Locks access functions 476 /////////////////////////////////////////////////////////////////////////////////// 477 478 /////////////////////////////////// 479 void _get_lock( _giet_lock_t* lock ) 480 { 481 unsigned int* plock = (unsigned int*)&(lock->value); 482 483 #if NO_HARD_CC 484 485 register unsigned int delay = (_get_proctime() ^ _get_procid() << 4) & 0xFF; 486 if (delay == 0) delay = 0x80; 487 488 asm volatile ( 489 "_lock_llsc: \n" 490 " ll $2, 0(%0) \n" /* $2 <= lock current value */ 491 " bnez $2, _lock_delay \n" /* delay if lock already taken */ 492 " li $3, 1 \n" /* $3 <= argument for sc */ 493 " sc $3, 0(%0) \n" /* try to set lock */ 494 " bnez $3, _lock_ok \n" /* exit if atomic */ 495 " _lock_delay: \n" 496 " move $4, %1 \n" /* $4 <= delay */ 497 " _lock_loop: \n" 498 " addi $4, $4, -1 \n" /* $4 <= $4 - 1 */ 499 " bnez $4, _lock_loop \n" /* test end delay */ 500 " nop \n" 501 " j _lock_llsc \n" /* retry */ 502 " nop \n" 503 " _lock_ok: \n" 504 : 505 :"r"(plock), "r"(delay) 506 :"$2", "$3", "$4", "memory"); 507 #else 508 509 asm volatile ( 510 "_lock_llsc: \n" 511 " lw $2, 0(%0) \n" /* $2 <= lock current value */ 512 " bnez $2, _lock_llsc \n" /* retry if lock already taken */ 513 " nop \n" 514 " ll $2, 0(%0) \n" /* ll_buffer <= lock current value */ 515 " bnez $2, _lock_llsc \n" /* retry if lock already taken */ 516 " li $3, 1 \n" /* $3 <= argument for sc */ 517 " sc $3, 0(%0) \n" /* try to set lock */ 518 " beqz $3, _lock_llsc \n" /* retry if sc failure */ 519 " nop \n" 520 : 521 :"r"(plock) 522 :"$2", "$3", "memory"); 523 #endif 524 525 } 526 527 /////////////////////////////////////// 528 void _release_lock( _giet_lock_t* lock ) 529 { 530 asm volatile ( "sync\n" ::: "memory" ); 531 // sync is necessary because of the TSAR consistency model 532 lock->value = 0; 533 } 534 535 //////////////////////////////////////////////////////////////////////////////////// 412 //////////////////////////////////////////////////////////////////////////// 536 413 // Scheduler and tasks context access functions 537 //////////////////////////////////////////////////////////////////////////// ////////414 //////////////////////////////////////////////////////////////////////////// 538 415 539 416 … … 652 529 MAPPING_PROC_SIZE * header->procs); 653 530 } 654 ///////////////////////////////////////////////////////////// 655 mapping_ coproc_t *_get_coproc_base(mapping_header_t * header)656 { 657 return (mapping_ coproc_t *) ((char *) header +531 /////////////////////////////////////////////////////////////// 532 mapping_periph_t *_get_periph_base(mapping_header_t * header) 533 { 534 return (mapping_periph_t *) ((char *) header + 658 535 MAPPING_HEADER_SIZE + 659 536 MAPPING_CLUSTER_SIZE * X_SIZE * Y_SIZE + … … 665 542 MAPPING_IRQ_SIZE * header->irqs); 666 543 } 667 /////////////////////////////////////////////////////////////// 668 mapping_cp_port_t *_get_cp_port_base(mapping_header_t * header) 669 { 670 return (mapping_cp_port_t *) ((char *) header + 671 MAPPING_HEADER_SIZE + 672 MAPPING_CLUSTER_SIZE * X_SIZE * Y_SIZE + 673 MAPPING_PSEG_SIZE * header->psegs + 674 MAPPING_VSPACE_SIZE * header->vspaces + 675 MAPPING_VSEG_SIZE * header->vsegs + 676 MAPPING_TASK_SIZE * header->tasks + 677 MAPPING_PROC_SIZE * header->procs + 678 MAPPING_IRQ_SIZE * header->irqs + 679 MAPPING_COPROC_SIZE * header->coprocs); 680 } 681 ///////////////////////////////////////////////////////////// 682 mapping_periph_t *_get_periph_base(mapping_header_t * header) 683 { 684 return (mapping_periph_t *) ((char *) header + 685 MAPPING_HEADER_SIZE + 686 MAPPING_CLUSTER_SIZE * X_SIZE * Y_SIZE + 687 MAPPING_PSEG_SIZE * header->psegs + 688 MAPPING_VSPACE_SIZE * header->vspaces + 689 MAPPING_VSEG_SIZE * header->vsegs + 690 MAPPING_TASK_SIZE * header->tasks + 691 MAPPING_PROC_SIZE * header->procs + 692 MAPPING_IRQ_SIZE * header->irqs + 693 MAPPING_COPROC_SIZE * header->coprocs + 694 MAPPING_CP_PORT_SIZE * header->cp_ports); 695 } 696 697 /////////////////////////////////////////////////////////////////////////////////// 544 545 /////////////////////////////////////////////////////////////////////////// 698 546 // Miscelaneous functions 699 /////////////////////////////////////////////////////////////////////////// ////////547 /////////////////////////////////////////////////////////////////////////// 700 548 701 549 ////////////////////////////////////// 702 550 __attribute__((noreturn)) void _exit() 703 551 { 704 unsigned int procid 705 unsigned int x 706 unsigned int y 707 unsigned int lpid 552 unsigned int procid = _get_procid(); 553 unsigned int x = (procid >> (Y_WIDTH + P_WIDTH)) & ((1<<X_WIDTH)-1); 554 unsigned int y = (procid >> P_WIDTH) & ((1<<Y_WIDTH)-1); 555 unsigned int lpid = procid & ((1<<P_WIDTH)-1); 708 556 709 557 … … 835 683 836 684 837 /////////////////////////////////////////////////////////////////////////// ////////685 /////////////////////////////////////////////////////////////////////////// 838 686 // Required by GCC 839 /////////////////////////////////////////////////////////////////////////// ////////687 /////////////////////////////////////////////////////////////////////////// 840 688 841 689 ////////////////////////////////
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