source: trunk/IPs/systemC/Environment/include/Environment_Parameters.h@ 100

Last change on this file since 100 was 88, checked in by rosiere, 18 years ago

Almost complete design
with Test and test platform
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1#ifndef ENVIRONMENT_PARAMETERS_H
2#define ENVIRONMENT_PARAMETERS_H
3
4#include "../Cache/include/Cache_Parameters.h"
5#include "../Data/include/Data_Parameters.h"
6#include "../Queue/include/Parameters.h"
7#include "../TTY/include/TTY_Parameters.h"
8#include "../RamLock/include/RamLock_Parameters.h"
9#include "../Sim2OS/include/Sim2OS_Parameters.h"
10#include "../../processor/Morpheo/Common/include/ToString.h"
11
12namespace environment {
13
14 class Parameters
15 {
16 public : uint32_t nb_iport ;
17 public : uint32_t nb_dport ;
18 public : uint32_t nb_entity ;
19 public : uint32_t * icache_dedicated_nb_port; //[nb_entity]
20 public : uint32_t * dcache_dedicated_nb_port; //[nb_entity]
21
22 public : uint32_t * iaccess_nb_context ; //[nb_entity]
23 public : uint32_t * iaccess_nb_packet ; //[nb_entity]
24 public : uint32_t * iaccess_size_address ; //[nb_entity]
25 public : uint32_t * iaccess_nb_instruction ; //[nb_entity]
26 public : uint32_t * iaccess_size_instruction; //[nb_entity]
27
28 public : uint32_t * daccess_nb_context ; //[nb_entity]
29 public : uint32_t * daccess_nb_packet ; //[nb_entity]
30 public : uint32_t * daccess_size_address ; //[nb_entity]
31 public : uint32_t * daccess_size_data ; //[nb_entity]
32
33 // Parameters cache
34 public : cache::Parameters * param_cache ;
35 // Parameters tty
36 public : uint32_t nb_component_tty ;
37 public : uint32_t * tty_address ; //[nb_component_tty]
38 public : tty::Parameters ** param_tty ; //[nb_component_tty]
39 // Parameters ramlock
40 public : uint32_t nb_component_ramlock ;
41 public : uint32_t * ramlock_address ; //[nb_component_ramlock]
42 public : ramlock::Parameters ** param_ramlock ; //[nb_component_ramlock]
43 // Parameters sim2OS
44 public : uint32_t sim2os_address ;
45 public : uint32_t sim2os_size ;
46 public : sim2os::Parameters * param_sim2os ;
47 // Parameters data
48 public : data::Parameters * param_data ;
49
50 // Parameters buffer_respons
51 public : queue::Parameters ** param_buffer_irsp ; //[nb_entity]
52 public : queue::Parameters ** param_buffer_drsp ; //[nb_entity]
53
54 public : Parameters (// General
55 uint32_t nb_cache_dedicated,
56
57 uint32_t * iaccess_nb_context,
58 uint32_t * iaccess_nb_instruction,
59 uint32_t * iaccess_nb_packet,
60 uint32_t * iaccess_size_address,
61 uint32_t * iaccess_size_instruction,
62
63 uint32_t * daccess_nb_context,
64 uint32_t * daccess_nb_packet,
65 uint32_t * daccess_size_address,
66 uint32_t * daccess_size_data,
67
68 // buffer
69 uint32_t * buffer_irsp_size,
70 uint32_t * buffer_drsp_size,
71
72 // Cache
73 uint32_t * icache_dedicated_nb_level ,
74 uint32_t * icache_dedicated_nb_port ,
75 uint32_t ** icache_dedicated_nb_line ,
76 uint32_t ** icache_dedicated_size_line ,
77 uint32_t ** icache_dedicated_size_word ,
78 uint32_t ** icache_dedicated_associativity,
79 uint32_t ** icache_dedicated_hit_latence ,
80 uint32_t ** icache_dedicated_miss_penality,
81 uint32_t * dcache_dedicated_nb_level ,
82 uint32_t * dcache_dedicated_nb_port ,
83 uint32_t ** dcache_dedicated_nb_line ,
84 uint32_t ** dcache_dedicated_size_line ,
85 uint32_t ** dcache_dedicated_size_word ,
86 uint32_t ** dcache_dedicated_associativity,
87 uint32_t ** dcache_dedicated_hit_latence ,
88 uint32_t ** dcache_dedicated_miss_penality,
89 uint32_t cache_shared_nb_level ,
90// uint32_t cache_shared_nb_port ,
91 uint32_t * cache_shared_nb_line ,
92 uint32_t * cache_shared_size_line ,
93 uint32_t * cache_shared_size_word ,
94 uint32_t * cache_shared_associativity ,
95 uint32_t * cache_shared_hit_latence ,
96 uint32_t * cache_shared_miss_penality ,
97
98 // TTY
99 uint32_t nb_component_tty,
100 uint32_t * tty_address,
101 uint32_t * nb_tty,
102 std::string ** name_tty,
103 bool with_xtty,
104
105 // RAMLOCK
106 uint32_t nb_component_ramlock,
107 uint32_t * ramlock_address,
108 uint32_t * nb_lock,
109
110 // SIM2OS
111 uint32_t sim2os_address,
112 uint32_t sim2os_size,
113 SOCLIB_SEGMENT_TABLE * segment_table
114 )
115 {
116 this->nb_entity = nb_cache_dedicated;
117
118 this->icache_dedicated_nb_port = icache_dedicated_nb_port;
119 this->dcache_dedicated_nb_port = dcache_dedicated_nb_port;
120
121 this->iaccess_nb_context = iaccess_nb_context ;
122 this->iaccess_nb_instruction = iaccess_nb_instruction ;
123 this->iaccess_nb_packet = iaccess_nb_packet ;
124 this->iaccess_size_address = iaccess_size_address ;
125 this->iaccess_size_instruction = iaccess_size_instruction;
126 this->daccess_nb_context = daccess_nb_context ;
127 this->daccess_nb_packet = daccess_nb_packet ;
128 this->daccess_size_address = daccess_size_address ;
129 this->daccess_size_data = daccess_size_data ;
130
131 param_cache = new cache::Parameters
132 (nb_cache_dedicated ,
133 icache_dedicated_nb_level ,
134 icache_dedicated_nb_port ,
135 icache_dedicated_nb_line ,
136 icache_dedicated_size_line ,
137 icache_dedicated_size_word ,
138 icache_dedicated_associativity,
139 icache_dedicated_hit_latence ,
140 icache_dedicated_miss_penality,
141 dcache_dedicated_nb_level ,
142 dcache_dedicated_nb_port ,
143 dcache_dedicated_nb_line ,
144 dcache_dedicated_size_line ,
145 dcache_dedicated_size_word ,
146 dcache_dedicated_associativity,
147 dcache_dedicated_hit_latence ,
148 dcache_dedicated_miss_penality,
149 cache_shared_nb_level ,
150// cache_shared_nb_port ,
151 cache_shared_nb_line ,
152 cache_shared_size_line ,
153 cache_shared_size_word ,
154 cache_shared_associativity ,
155 cache_shared_hit_latence ,
156 cache_shared_miss_penality
157 );
158
159 nb_iport = 0;
160 nb_dport = 0;
161 for (uint32_t i=0; i<nb_cache_dedicated; i++)
162 {
163 nb_iport += icache_dedicated_nb_port [i];
164 nb_dport += dcache_dedicated_nb_port [i];
165 }
166
167 this->nb_component_tty = nb_component_tty;
168 this->tty_address = tty_address;
169
170 param_tty = new tty::Parameters * [nb_component_tty];
171 for (uint32_t i=0; i<nb_component_tty; i++)
172 {
173 uint32_t tty_size = nb_tty [i] * 16; // 4 32bit-register by tty
174
175// std::ostringstream str("");
176// str << "tty_" << i;
177 segment_table->addSegment("tty",tty_address[i],tty_size,0,0,true);
178
179 param_tty [i] = new tty::Parameters (nb_tty [i],
180 name_tty [i],
181 with_xtty );
182 }
183
184 this->nb_component_ramlock = nb_component_ramlock;
185 this->ramlock_address = ramlock_address;
186
187 param_ramlock = new ramlock::Parameters * [nb_component_ramlock];
188 for (uint32_t i=0; i<nb_component_ramlock; i++)
189 {
190 uint32_t ramlock_size = nb_lock[i]; // registre 8 bits because it's min size access
191// std::ostringstream str ("");
192// str << "ramlock" << i;
193 segment_table->addSegment("ramlock",ramlock_address[i],ramlock_size,0,0,true);
194
195 param_ramlock [i] = new ramlock::Parameters (nb_lock [i]);
196 }
197
198 this->sim2os_address = sim2os_address ;
199 this->sim2os_size = sim2os_size ;
200
201 segment_table->addSegment("sim2os",sim2os_address,sim2os_size,0,0,true);
202 param_sim2os = new sim2os::Parameters (segment_table);
203
204 param_data = new data::Parameters (16,0,0, segment_table);
205
206 param_buffer_irsp = new queue::Parameters * [nb_entity];
207 for (uint32_t i=0; i<nb_entity; i++)
208 param_buffer_irsp [i] = new queue::Parameters (buffer_irsp_size [i]);
209
210 param_buffer_drsp = new queue::Parameters * [nb_entity];
211 for (uint32_t i=0; i<nb_entity; i++)
212 param_buffer_drsp [i] = new queue::Parameters (buffer_drsp_size [i]);
213 }
214
215 public : ~Parameters (void)
216 {
217 for (uint32_t i=0; i<nb_entity; i++)
218 delete param_buffer_irsp [i];
219 delete [] param_buffer_irsp;
220
221 for (uint32_t i=0; i<nb_entity; i++)
222 delete param_buffer_drsp [i];
223 delete [] param_buffer_drsp;
224
225 delete param_data ;
226 delete param_sim2os;
227 for (uint32_t i=0; i<nb_component_ramlock; i++)
228 delete param_ramlock [i];
229 delete [] param_ramlock;
230 for (uint32_t i=0; i<nb_component_tty; i++)
231 delete param_tty [i];
232 delete [] param_tty;
233 delete param_cache;
234 }
235
236 public : std::string print (uint32_t depth)
237 {
238 std::string tab = std::string(depth,'\t');
239 std::string str = "";
240
241 str+=tab+"nb_entity : "+morpheo::toString(nb_entity)+"\n";
242 str+=tab+"nb_iport : "+morpheo::toString(nb_iport )+"\n";
243 str+=tab+"nb_dport : "+morpheo::toString(nb_dport )+"\n";
244 for (uint32_t i=0; i<nb_entity; ++i)
245 {
246 str+=tab+"ENTITY ["+morpheo::toString(i)+"]\n";
247 str+=tab+" * icache_dedicated_nb_port : "+morpheo::toString(icache_dedicated_nb_port[i])+"\n";
248 str+=tab+" * dcache_dedicated_nb_port : "+morpheo::toString(dcache_dedicated_nb_port[i])+"\n";
249 str+=tab+" * iaccess_nb_context : "+morpheo::toString(iaccess_nb_context [i])+"\n";
250 str+=tab+" * iaccess_nb_packet : "+morpheo::toString(iaccess_nb_packet [i])+"\n";
251 str+=tab+" * iaccess_size_address : "+morpheo::toString(iaccess_size_address [i])+"\n";
252 str+=tab+" * iaccess_nb_instruction : "+morpheo::toString(iaccess_nb_instruction [i])+"\n";
253 str+=tab+" * iaccess_size_instruction : "+morpheo::toString(iaccess_size_instruction[i])+"\n";
254 str+=tab+" * daccess_nb_context : "+morpheo::toString(daccess_nb_context [i])+"\n";
255 str+=tab+" * daccess_nb_packet : "+morpheo::toString(daccess_nb_packet [i])+"\n";
256 str+=tab+" * daccess_size_address : "+morpheo::toString(daccess_size_address [i])+"\n";
257 str+=tab+" * daccess_size_data : "+morpheo::toString(daccess_size_data [i])+"\n";
258 }
259
260 str+=tab+"CACHE\n";
261 str+=param_cache->print(depth+1);
262
263// str+=tab+"nb_component_tty : "+morpheo::toString(nb_component_tty )+"\n";
264// for (uint32_t i=0; i<nb_component_tty; ++i)
265// {
266// str+=tab+"TTY ["+morpheo::toString(i)+"]\n";
267// str+=tab+" * tty_address : "+morpheo::toString(tty_address [i])+"\n";
268// str+=param_tty->print(depth+1);
269// }
270
271// str+=tab+"nb_component_ramlock : "+morpheo::toString(nb_component_ramlock )+"\n";
272// for (uint32_t i=0; i<nb_component_ramlock; ++i)
273// {
274// str+=tab+"RAMLOCK ["+morpheo::toString(i)+"]\n";
275// str+=tab+" * ramlock_address : "+morpheo::toString(ramlock_address [i])+"\n";
276// str+=param_ramlock->print(depth+1);
277// }
278
279// str+=tab+"SIM2OS\n";
280// str+=tab+"sim2os_address : "+morpheo::toString(sim2os_address)+"\n";
281// str+=tab+"sim2os_size : "+morpheo::toString(sim2os_size )+"\n";
282// str+=param_sim2os->print(depth+1);
283
284// str+=tab+"DATA\n";
285// str+=param_data->print(depth+1);
286
287// for (uint32_t i=0; i<nb_entity; ++i)
288// {
289// str+=tab+"BUFFER_IRSP ["+morpheo::toString(i)+"]\n";
290// str+=param_buffer_irsp[i]_data->print(depth+1);
291// }
292
293// for (uint32_t i=0; i<nb_entity; ++i)
294// {
295// str+=tab+"BUFFER_DRSP ["+morpheo::toString(i)+"]\n";
296// str+=param_buffer_drsp[i]_data->print(depth+1);
297// }
298
299 return str;
300 }
301
302// public : friend std::ostream& operator<< (std::ostream& output, const Parameters &x)
303// {
304// x.print(0);
305// return output;
306// }
307 };
308
309};
310#endif
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