Changeset 88 for trunk/IPs/systemC/Environment/include/Environment_Parameters.h

Timestamp:

Dec 10, 2008, 7:31:39 PM (16 years ago)

Author:

rosiere

Message:

Almost complete design
with Test and test platform

File:

• trunk/IPs/systemC/Environment/include/Environment_Parameters.h (modified) (3 diffs)

trunk/IPs/systemC/Environment/include/Environment_Parameters.h

@@ -8 +8 @@
 #include "../RamLock/include/RamLock_Parameters.h"
 #include "../Sim2OS/include/Sim2OS_Parameters.h"
+#include "../../processor/Morpheo/Common/include/ToString.h"
 
 namespace environment {
@@ -13 +14 @@
   class Parameters
   {
-  public : uint32_t    nb_iport;
-  public : uint32_t    nb_dport;
-  public : uint32_t    nb_entity;
-  public : uint32_t  * icache_dedicated_nb_port;
-  public : uint32_t  * dcache_dedicated_nb_port;
-
-  public : uint32_t  * iaccess_nb_context    ;
-  public : uint32_t  * iaccess_nb_packet     ;
-  public : uint32_t  * iaccess_size_address  ;
-  public : uint32_t  * iaccess_nb_instruction;
-  public : uint32_t  * iaccess_size_instruction;
-
-  public : uint32_t  * daccess_nb_context    ;
-  public : uint32_t  * daccess_nb_packet     ;
-  public : uint32_t  * daccess_size_address  ;
-  public : uint32_t  * daccess_size_data     ;
+  public : uint32_t                nb_iport                ;
+  public : uint32_t                nb_dport                ;
+  public : uint32_t                nb_entity               ;
+  public : uint32_t              * icache_dedicated_nb_port; //[nb_entity]
+  public : uint32_t              * dcache_dedicated_nb_port; //[nb_entity]
+                               
+  public : uint32_t              * iaccess_nb_context      ; //[nb_entity]
+  public : uint32_t              * iaccess_nb_packet       ; //[nb_entity]
+  public : uint32_t              * iaccess_size_address    ; //[nb_entity]
+  public : uint32_t              * iaccess_nb_instruction  ; //[nb_entity]
+  public : uint32_t              * iaccess_size_instruction; //[nb_entity]
+                               
+  public : uint32_t              * daccess_nb_context      ; //[nb_entity]
+  public : uint32_t              * daccess_nb_packet       ; //[nb_entity]
+  public : uint32_t              * daccess_size_address    ; //[nb_entity]
+  public : uint32_t              * daccess_size_data       ; //[nb_entity]
 
     // Parameters cache
-  public : cache::Parameters                     * param_cache;
+  public : cache::Parameters     * param_cache             ;
     // Parameters tty
-  public : uint32_t                                nb_component_tty;
-  public : uint32_t                              * tty_address;
-  public : tty::Parameters                      ** param_tty;
+  public : uint32_t                nb_component_tty        ;
+  public : uint32_t              * tty_address             ; //[nb_component_tty]
+  public : tty::Parameters      ** param_tty               ; //[nb_component_tty]
     // Parameters ramlock
-  public : uint32_t                                nb_component_ramlock;
-  public : uint32_t                              * ramlock_address;
-  public : ramlock::Parameters                  ** param_ramlock;
+  public : uint32_t                nb_component_ramlock    ;
+  public : uint32_t              * ramlock_address         ; //[nb_component_ramlock]
+  public : ramlock::Parameters  ** param_ramlock           ; //[nb_component_ramlock]
     // Parameters sim2OS
-  public : uint32_t                                sim2os_address;
-  public : uint32_t                                sim2os_size;
-  public : sim2os::Parameters                    * param_sim2os;
+  public : uint32_t                sim2os_address          ;
+  public : uint32_t                sim2os_size             ;
+  public : sim2os::Parameters    * param_sim2os            ;
     // Parameters data
-  public : data::Parameters                      * param_data;
+  public : data::Parameters      * param_data              ;
 
     // Parameters buffer_respons
-  public : queue::Parameters                    ** param_buffer_irsp;
-  public : queue::Parameters                    ** param_buffer_drsp;
+  public : queue::Parameters    ** param_buffer_irsp       ; //[nb_entity]
+  public : queue::Parameters    ** param_buffer_drsp       ; //[nb_entity]
 
   public : Parameters (// General
@@ -232 +233 @@
       delete param_cache;
     }
+
+  public : std::string print (uint32_t depth)
+    {
+      std::string tab = std::string(depth,'\t');
+      std::string str = "";
+
+      str+=tab+"nb_entity                    : "+morpheo::toString(nb_entity)+"\n";
+      str+=tab+"nb_iport                     : "+morpheo::toString(nb_iport )+"\n";
+      str+=tab+"nb_dport                     : "+morpheo::toString(nb_dport )+"\n";
+      for (uint32_t i=0; i<nb_entity; ++i)
+        {
+      str+=tab+"ENTITY ["+morpheo::toString(i)+"]\n";
+      str+=tab+"  * icache_dedicated_nb_port : "+morpheo::toString(icache_dedicated_nb_port[i])+"\n";
+      str+=tab+"  * dcache_dedicated_nb_port : "+morpheo::toString(dcache_dedicated_nb_port[i])+"\n";
+      str+=tab+"  * iaccess_nb_context       : "+morpheo::toString(iaccess_nb_context      [i])+"\n";
+      str+=tab+"  * iaccess_nb_packet        : "+morpheo::toString(iaccess_nb_packet       [i])+"\n";
+      str+=tab+"  * iaccess_size_address     : "+morpheo::toString(iaccess_size_address    [i])+"\n";
+      str+=tab+"  * iaccess_nb_instruction   : "+morpheo::toString(iaccess_nb_instruction  [i])+"\n";
+      str+=tab+"  * iaccess_size_instruction : "+morpheo::toString(iaccess_size_instruction[i])+"\n";
+      str+=tab+"  * daccess_nb_context       : "+morpheo::toString(daccess_nb_context      [i])+"\n";
+      str+=tab+"  * daccess_nb_packet        : "+morpheo::toString(daccess_nb_packet       [i])+"\n";
+      str+=tab+"  * daccess_size_address     : "+morpheo::toString(daccess_size_address    [i])+"\n";
+      str+=tab+"  * daccess_size_data        : "+morpheo::toString(daccess_size_data       [i])+"\n";
+        }
+
+      str+=tab+"CACHE\n";
+      str+=param_cache->print(depth+1);
+
+//       str+=tab+"nb_component_tty             : "+morpheo::toString(nb_component_tty           )+"\n";
+//       for (uint32_t i=0; i<nb_component_tty; ++i)
+//         {
+//       str+=tab+"TTY ["+morpheo::toString(i)+"]\n";
+//       str+=tab+"  * tty_address              : "+morpheo::toString(tty_address             [i])+"\n";
+//       str+=param_tty->print(depth+1);
+//         }      
+
+//       str+=tab+"nb_component_ramlock         : "+morpheo::toString(nb_component_ramlock       )+"\n";
+//       for (uint32_t i=0; i<nb_component_ramlock; ++i)
+//         {
+//       str+=tab+"RAMLOCK ["+morpheo::toString(i)+"]\n";
+//       str+=tab+"  * ramlock_address          : "+morpheo::toString(ramlock_address         [i])+"\n";
+//       str+=param_ramlock->print(depth+1);
+//         }      
+
+//       str+=tab+"SIM2OS\n";
+//       str+=tab+"sim2os_address               : "+morpheo::toString(sim2os_address)+"\n";
+//       str+=tab+"sim2os_size                  : "+morpheo::toString(sim2os_size   )+"\n";
+//       str+=param_sim2os->print(depth+1);
+
+//       str+=tab+"DATA\n";
+//       str+=param_data->print(depth+1);
+
+//       for (uint32_t i=0; i<nb_entity; ++i)
+//         {
+//       str+=tab+"BUFFER_IRSP ["+morpheo::toString(i)+"]\n";
+//       str+=param_buffer_irsp[i]_data->print(depth+1);
+//         }
+
+//       for (uint32_t i=0; i<nb_entity; ++i)
+//         {
+//       str+=tab+"BUFFER_DRSP ["+morpheo::toString(i)+"]\n";
+//       str+=param_buffer_drsp[i]_data->print(depth+1);
+//         }
+
+      return str;
+    }
+
+//   public : friend std::ostream& operator<< (std::ostream& output, const Parameters &x)
+//     {
+//       x.print(0);
+//       return output;
+//     }
   };