[81] | 1 | #include "../include/Environment.h" |
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| 2 | |
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[88] | 3 | using namespace morpheo; |
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| 4 | |
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[81] | 5 | namespace environment { |
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| 6 | |
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| 7 | void Environment::genMoore (void) |
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| 8 | { |
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| 9 | //Scan all entity and for each entity scan all port |
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| 10 | for (uint32_t i = 0; i < param->nb_entity; i++) |
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| 11 | { |
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| 12 | //============================================================================= |
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| 13 | //===== [ ICACHE ]============================================================= |
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| 14 | //============================================================================= |
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| 15 | |
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| 16 | //----------------------------------------------------------------------------- |
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| 17 | //----- [ Request ]------------------------------------------------------------ |
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| 18 | //----------------------------------------------------------------------------- |
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| 19 | { |
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| 20 | uint32_t nb_slot_free = component_buffer_irsp [i]->nb_slot_free (); |
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| 21 | for (uint32_t j=0; j<param->icache_dedicated_nb_port [i]; j ++) |
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| 22 | { |
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| 23 | icache_req_ack [i][j] = (j < nb_slot_free); |
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| 24 | ICACHE_REQ_ACK [i][j]->write (icache_req_ack [i][j]); |
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| 25 | } |
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| 26 | } |
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| 27 | |
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| 28 | //----------------------------------------------------------------------------- |
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| 29 | //----- [ Respons ]------------------------------------------------------------ |
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| 30 | //----------------------------------------------------------------------------- |
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| 31 | { |
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| 32 | for (uint32_t j = 0; j < param->icache_dedicated_nb_port [i]; j ++) |
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| 33 | { |
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| 34 | // Test the number of element in the respons's buffer |
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| 35 | if (j >= component_buffer_irsp [i]->nb_slot_use()) |
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| 36 | { |
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| 37 | icache_rsp_val [i][j] = 0; // No respons |
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| 38 | } |
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| 39 | else |
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| 40 | { |
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| 41 | queue::slot_t<irsp_t*> slot = component_buffer_irsp [i]->read(j); |
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| 42 | |
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| 43 | bool val = (slot._delay == 0); |
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| 44 | |
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| 45 | icache_rsp_val [i][j] = (val); // respons if have a result |
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| 46 | |
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| 47 | if (val) |
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| 48 | { |
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| 49 | ICACHE_RSP_CONTEXT_ID [i][j]->write(slot._data->trdid); // TODO : test if exist |
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| 50 | ICACHE_RSP_PACKET_ID [i][j]->write(slot._data->pktid); // TODO : test if exist |
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| 51 | ICACHE_RSP_ERROR [i][j]->write(slot._data->error); |
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| 52 | |
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| 53 | for (uint32_t k = 0; k < param->iaccess_nb_instruction[i]; k ++) |
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| 54 | { |
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| 55 | Ticache_instruction_t data = 0; |
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| 56 | |
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| 57 | atoi (slot._data->data[k], data, param->iaccess_size_instruction[i]/8); |
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| 58 | |
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| 59 | ICACHE_RSP_INSTRUCTION [i][j][k]->write(data); |
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| 60 | } |
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| 61 | } |
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| 62 | } |
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| 63 | |
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| 64 | ICACHE_RSP_VAL [i][j]->write (icache_rsp_val [i][j]); |
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| 65 | } |
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| 66 | } |
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| 67 | |
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| 68 | //============================================================================= |
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| 69 | //===== [ DCACHE ]============================================================= |
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| 70 | //============================================================================= |
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| 71 | |
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| 72 | //----------------------------------------------------------------------------- |
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| 73 | //----- [ Request ]------------------------------------------------------------ |
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| 74 | //----------------------------------------------------------------------------- |
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| 75 | { |
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| 76 | uint32_t nb_slot_free = component_buffer_drsp [i]->nb_slot_free (); |
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| 77 | for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++) |
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| 78 | { |
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| 79 | dcache_req_ack [i][j] = (j < nb_slot_free); |
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| 80 | DCACHE_REQ_ACK [i][j]->write (dcache_req_ack [i][j]); |
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| 81 | } |
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| 82 | } |
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| 83 | |
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| 84 | //----------------------------------------------------------------------------- |
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| 85 | //----- [ Respons ]------------------------------------------------------------ |
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| 86 | //----------------------------------------------------------------------------- |
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| 87 | { |
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| 88 | for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++) |
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| 89 | { |
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| 90 | // Test the number of element in the respons's buffer |
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| 91 | if (j >= component_buffer_drsp [i]->nb_slot_use()) |
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| 92 | { |
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| 93 | dcache_rsp_val [i][j] = 0; // No respons |
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| 94 | } |
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| 95 | else |
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| 96 | { |
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| 97 | queue::slot_t<drsp_t*> slot = component_buffer_drsp [i]->read(j); |
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| 98 | |
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| 99 | bool val = (slot._delay == 0); // respons if have a result |
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| 100 | |
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| 101 | dcache_rsp_val [i][j] = (val); // respons if have a result |
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| 102 | |
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| 103 | if (val) |
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| 104 | { |
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| 105 | DCACHE_RSP_CONTEXT_ID [i][j]->write(slot._data->trdid); // TODO : test if exist |
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| 106 | DCACHE_RSP_PACKET_ID [i][j]->write(slot._data->pktid); // TODO : test if exist |
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| 107 | DCACHE_RSP_ERROR [i][j]->write(slot._data->error); |
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| 108 | |
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| 109 | Tdcache_data_t data = 0; |
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| 110 | atoi (slot._data->data[0], data, param->daccess_size_data[i]/8); |
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| 111 | |
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| 112 | DCACHE_RSP_RDATA [i][j]->write(data); |
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| 113 | } |
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| 114 | } |
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| 115 | DCACHE_RSP_VAL [i][j]->write (dcache_rsp_val [i][j]); |
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| 116 | } |
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| 117 | } |
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| 118 | } |
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| 119 | } |
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| 120 | |
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| 121 | }; |
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