[81] | 1 | #include "../include/Environment.h" |
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[128] | 2 | #include "../../processor/Morpheo/Common/include/Systemc.h" |
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[81] | 3 | |
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[88] | 4 | using namespace morpheo; |
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| 5 | |
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[81] | 6 | namespace environment { |
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| 7 | |
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| 8 | void Environment::genMoore (void) |
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| 9 | { |
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[128] | 10 | _cout(ENVIRONMENT, " [%d] <Environment::genMoore>\n",static_cast<uint32_t>(simulation_cycle())); |
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| 11 | |
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[81] | 12 | //Scan all entity and for each entity scan all port |
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| 13 | for (uint32_t i = 0; i < param->nb_entity; i++) |
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| 14 | { |
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| 15 | //============================================================================= |
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| 16 | //===== [ ICACHE ]============================================================= |
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| 17 | //============================================================================= |
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| 18 | |
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| 19 | //----------------------------------------------------------------------------- |
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| 20 | //----- [ Request ]------------------------------------------------------------ |
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| 21 | //----------------------------------------------------------------------------- |
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| 22 | { |
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| 23 | uint32_t nb_slot_free = component_buffer_irsp [i]->nb_slot_free (); |
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| 24 | for (uint32_t j=0; j<param->icache_dedicated_nb_port [i]; j ++) |
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| 25 | { |
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| 26 | icache_req_ack [i][j] = (j < nb_slot_free); |
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| 27 | ICACHE_REQ_ACK [i][j]->write (icache_req_ack [i][j]); |
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| 28 | } |
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| 29 | } |
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| 30 | |
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| 31 | //----------------------------------------------------------------------------- |
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| 32 | //----- [ Respons ]------------------------------------------------------------ |
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| 33 | //----------------------------------------------------------------------------- |
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| 34 | { |
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[124] | 35 | // init |
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[81] | 36 | for (uint32_t j = 0; j < param->icache_dedicated_nb_port [i]; j ++) |
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[128] | 37 | { |
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| 38 | icache_rsp_val [i][j] = 0; |
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| 39 | icache_rsp_num [i][j] = 0; |
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| 40 | } |
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[124] | 41 | |
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[128] | 42 | _cout(ENVIRONMENT, " * buffer_irsp [%d] : nb_slot_use %d\n",i,component_buffer_irsp [i]->nb_slot_use()); |
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[127] | 43 | for (uint32_t j = 0; j+1 <= component_buffer_irsp [i]->nb_slot_use(); j ++) |
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[81] | 44 | { |
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| 45 | // Test the number of element in the respons's buffer |
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[124] | 46 | |
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| 47 | queue::slot_t<irsp_t*> slot = component_buffer_irsp [i]->read(j); |
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| 48 | |
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| 49 | uint32_t port = slot._data->port; |
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| 50 | |
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| 51 | bool val = ((slot._delay == 0) and (icache_rsp_val [i][port] == 0)); |
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[81] | 52 | |
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[128] | 53 | _cout(ENVIRONMENT, " * buffer_irsp [%d][%d] - delay %d - port %d\n",i,j,slot._delay,port); |
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[81] | 54 | |
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[124] | 55 | |
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| 56 | if (val) |
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| 57 | { |
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[128] | 58 | _cout(ENVIRONMENT, " * ICACHE_RSP [%d][%d] - respons valid\n",i,port); |
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[124] | 59 | |
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| 60 | icache_rsp_val [i][port] = 1; |
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[128] | 61 | icache_rsp_num [i][port] = j; |
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[124] | 62 | |
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| 63 | ICACHE_RSP_CONTEXT_ID [i][port]->write(slot._data->trdid); // TODO : test if exist |
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| 64 | ICACHE_RSP_PACKET_ID [i][port]->write(slot._data->pktid); // TODO : test if exist |
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| 65 | ICACHE_RSP_ERROR [i][port]->write(slot._data->error); |
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| 66 | |
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| 67 | for (uint32_t k = 0; k < param->iaccess_nb_instruction[i]; k ++) |
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| 68 | { |
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| 69 | Ticache_instruction_t data = 0; |
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| 70 | |
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| 71 | atoi (slot._data->data[k], data, param->iaccess_size_instruction[i]/8); |
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| 72 | |
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| 73 | ICACHE_RSP_INSTRUCTION [i][port][k]->write(data); |
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| 74 | } |
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| 75 | } |
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| 76 | } |
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| 77 | |
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| 78 | for (uint32_t j = 0; j < param->icache_dedicated_nb_port [i]; j ++) |
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| 79 | ICACHE_RSP_VAL [i][j]->write (icache_rsp_val [i][j]); |
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[81] | 80 | } |
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| 81 | |
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| 82 | //============================================================================= |
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| 83 | //===== [ DCACHE ]============================================================= |
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| 84 | //============================================================================= |
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| 85 | |
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| 86 | //----------------------------------------------------------------------------- |
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| 87 | //----- [ Request ]------------------------------------------------------------ |
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| 88 | //----------------------------------------------------------------------------- |
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| 89 | { |
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| 90 | uint32_t nb_slot_free = component_buffer_drsp [i]->nb_slot_free (); |
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| 91 | for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++) |
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| 92 | { |
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| 93 | dcache_req_ack [i][j] = (j < nb_slot_free); |
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| 94 | DCACHE_REQ_ACK [i][j]->write (dcache_req_ack [i][j]); |
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| 95 | } |
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| 96 | } |
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| 97 | |
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| 98 | //----------------------------------------------------------------------------- |
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| 99 | //----- [ Respons ]------------------------------------------------------------ |
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| 100 | //----------------------------------------------------------------------------- |
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| 101 | { |
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[128] | 102 | // init |
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[81] | 103 | for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++) |
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[128] | 104 | { |
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| 105 | dcache_rsp_val [i][j] = 0; |
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| 106 | dcache_rsp_num [i][j] = 0; |
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| 107 | } |
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| 108 | |
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| 109 | for (uint32_t j = 0; j+1 <= component_buffer_drsp [i]->nb_slot_use(); j ++) |
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[81] | 110 | { |
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[128] | 111 | queue::slot_t<drsp_t*> slot = component_buffer_drsp [i]->read(j); |
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| 112 | |
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| 113 | uint32_t port = slot._data->port; |
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| 114 | bool val = ((slot._delay == 0) and (dcache_rsp_val [i][port] == 0)); |
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| 115 | |
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| 116 | if (val) |
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| 117 | { |
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| 118 | _cout(ENVIRONMENT, " * DCACHE_RSP [%d][%d] - respons valid\n",i,port); |
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| 119 | |
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| 120 | dcache_rsp_val [i][port] = 1; |
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| 121 | dcache_rsp_num [i][port] = j; |
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| 122 | |
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| 123 | DCACHE_RSP_CONTEXT_ID [i][port]->write(slot._data->trdid); // TODO : test if exist |
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| 124 | DCACHE_RSP_PACKET_ID [i][port]->write(slot._data->pktid); // TODO : test if exist |
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| 125 | DCACHE_RSP_ERROR [i][port]->write(slot._data->error); |
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[81] | 126 | |
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[128] | 127 | Tdcache_data_t data = 0; |
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| 128 | atoi (slot._data->data[0], data, param->daccess_size_data[i]/8); |
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| 129 | |
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| 130 | DCACHE_RSP_RDATA [i][port]->write(data); |
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| 131 | } |
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| 132 | } |
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[81] | 133 | |
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[128] | 134 | for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++) |
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| 135 | DCACHE_RSP_VAL [i][j]->write (dcache_rsp_val [i][j]); |
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[81] | 136 | } |
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| 137 | } |
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| 138 | } |
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| 139 | |
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| 140 | }; |
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