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source: trunk/IPs/systemC/Environment/src/Environment_transition.cpp @ 117

Last change on this file since 117 was 117, checked in by rosiere, 15 years ago
1) Platforms : add new organization for test 2) Load_Store_Unit : add array to count nb_check in store_queue 3) Issue_queue and Core_Glue : rewrite the issue network 4) Special_Register_Unit : add reset value to register CID 5) Softwares : add multicontext test 6) Softwares : add SPECINT 7) Softwares : add MiBench? 7) Read_queue : inhib access for r0 8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
Property svn:keywords set to `Id`
File size: 30.9 KB

Line
1	#include "../include/Environment.h"
2
3	#define CYCLE_MAX 0
4	#include "../../processor/Morpheo/Common/include/Test.h"
5
6	using namespace morpheo;
7
8	namespace environment {
9
10	void Environment::transition (void)
11	{
12	if (NRESET->read() == 0)
13	{
14	reset ();
15	}
16	else
17	{
18	//=============================================================================
19	//===== [ ICACHE - RESPONS ]===================================================
20	//=============================================================================
21	for (uint32_t i = 0; i < param->nb_entity; i++)
22	for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--)
23	if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read())
24	{
25	delete component_buffer_irsp [i]->read(j)._data;
26	component_buffer_irsp [i]->pop(j);
27	}
28	//=============================================================================
29	//===== [ DCACHE - RESPONS ]===================================================
30	//=============================================================================
31	for (uint32_t i = 0; i < param->nb_entity; i++)
32	for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--)
33	if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read())
34	{
35	delete component_buffer_drsp [i]->read(j)._data;
36	component_buffer_drsp [i]->pop(j);
37	}
38
39	//=============================================================================
40	//===== [ ICACHE - RESPONS ]===================================================
41	//=============================================================================
42	for (uint32_t i=0; i<param->nb_entity; i++)
43	for (uint32_t j=0; j <param->icache_dedicated_nb_port [i]; j++)
44	if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j])
45	{
46	_cout(ENVIRONMENT, "ICACHE_REQ [%d] : Transaction accepted\n",i);
47
48	Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
49	Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
50	Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read()<<2;
51	Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read();
52	uint32_t size = (param->iaccess_size_address [i]+2)/8;
53
54	_cout(ENVIRONMENT," * information\n");
55	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
56	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
57	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
58	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
59	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
60
61	// search the entity
62	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
63
64	bool uncached ;
65	bool bus_error;
66	bool must_read = (type == ICACHE_TYPE_LOAD);
67	bool must_ack = (type == ICACHE_TYPE_LOAD);
68	bool must_ack_on_error = (type == ICACHE_TYPE_LOAD);
69
70	// Test the type of the address : if != MEMORY -> error
71	if ((entity.present == true) and
72	(entity.segment->getType() == data::TYPE_TARGET_MEMORY))
73	{
74	_cout(ENVIRONMENT," * OK !\n");
75	bus_error = false;
76	uncached = entity.segment->getUncached();
77
78	if (must_read == true) // Test if must read the ram
79	{
80	_cout(ENVIRONMENT," * must read\n");
81	// Read all instruction
82	for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++)
83	{
84	uint32_t addr = address+k*(size);
85	_cout(ENVIRONMENT," * addr : %.8x\n",addr);
86
87	bus_error \|= !component_data->read(addr,size,read_iram[k]);
88
89	// Swap if endienness is different
90	if (endianness::isSameEndianness(context) == false)
91	{
92	read_iram[k] = endianness::swapBytes(read_iram[k],size,size);
93	}
94
95	_cout(ENVIRONMENT," * inst :");
96	for (int32_t cpt=(param->iaccess_size_instruction[i]/8)-1; cpt>=0; --cpt)
97	__cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt]));
98	__cout(ENVIRONMENT, "\n");
99	}
100	}
101	}
102	else
103	{
104	_cout(ENVIRONMENT, " * KO !\n");
105	_cout(ENVIRONMENT, " * present : %d\n",entity.present);
106	if (entity.present)
107	_cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY);
108
109	// entity is not present, or is present but is not a memory : have a bus error
110	bus_error = true;
111	uncached = true;
112	}
113
114	Cache_Access cache_type = ireq_type2cache_type (type,uncached);
115	uint32_t latence = component_cache->latence(cache::INSTRUCTION_CACHE,
116	i,
117	j,
118	address,
119	context,
120	cache_type.type,
121	cache_type.direction);
122
123	_cout(ENVIRONMENT, " * latence : %d\n",latence);
124
125	// If is a respons -> compute the latence and push in the write_buffer
126	if (must_ack or (must_ack_on_error and bus_error))
127	{
128	_cout(ENVIRONMENT, " * must ack\n");
129
130	if (bus_error == true)
131	{
132	_cout(ENVIRONMENT," * Icache : have a bus error\n");
133	_cout(ENVIRONMENT," * entity : %d\n",i);
134	_cout(ENVIRONMENT," * port : %d\n",j);
135	_cout(ENVIRONMENT," * req_addr : %x\n",address);
136	_cout(ENVIRONMENT," * req_trdid : %d\n",context);
137	_cout(ENVIRONMENT," * req_pktid : %d\n",packet );
138
139	// Write in instruction [0] the bad address (only 32bit ....)
140	itoa<Ticache_address_t>(address,read_iram[0],param->iaccess_size_instruction[i]/8);
141	}
142
143	// Simplification : the size of a line is a multiple of size_iword (no test)
144	_cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i);
145
146	irsp_t * rsp = new irsp_t(context,
147	packet,
148	param->iaccess_nb_instruction[i],
149	size,
150	read_iram,
151	(bus_error==true)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
152	component_buffer_irsp [i]->push(latence,rsp);
153	}
154
155	_cout(ENVIRONMENT, " * End request\n");
156	}
157
158	//=============================================================================
159	//===== [ DCACHE - REQUEST ]===================================================
160	//=============================================================================
161	for (uint32_t i=0; i<param->nb_entity; i++)
162	for (uint32_t j=0; j <param->dcache_dedicated_nb_port [i]; j++)
163	if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j])
164	{
165	_cout(ENVIRONMENT, "DCACHE_REQ [%d] : Transaction accepted\n",i);
166
167	Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
168	Tdcache_packet_t packet = DCACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
169	Tdcache_address_t address = DCACHE_REQ_ADDRESS [i][j]->read();
170	Tdcache_data_t wdata = DCACHE_REQ_WDATA [i][j]->read();
171	Tdcache_type_t type = DCACHE_REQ_TYPE [i][j]->read();
172	uint32_t size = param->daccess_size_data [i]/8;
173
174	_cout(ENVIRONMENT," * information\n");
175	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
176	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
177	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
178	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
179	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
180
181	bool uncached = false;
182	bool bus_error = false;
183
184	uint32_t nb_bytes = size;
185	bool must_read ;
186	bool must_write;
187	bool must_ack ;
188	bool must_ack_on_error;
189
190	switch (type)
191	{
192	case DCACHE_TYPE_LOAD_8 :{nb_bytes=1; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
193	case DCACHE_TYPE_LOAD_16 :{nb_bytes=2; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
194	case DCACHE_TYPE_LOAD_32 :{nb_bytes=4; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
195	case DCACHE_TYPE_LOAD_64 :{nb_bytes=8; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
196	case DCACHE_TYPE_LOCK :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
197	case DCACHE_TYPE_INVALIDATE :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
198	case DCACHE_TYPE_PREFETCH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
199	case DCACHE_TYPE_FLUSH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
200	case DCACHE_TYPE_SYNCHRONIZATION :{ must_read=false; must_write=false; must_ack=true ; must_ack_on_error=false; break;}
201	case DCACHE_TYPE_STORE_8 :{nb_bytes=1; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
202	case DCACHE_TYPE_STORE_16 :{nb_bytes=2; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
203	case DCACHE_TYPE_STORE_32 :{nb_bytes=4; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
204	case DCACHE_TYPE_STORE_64 :{nb_bytes=8; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
205	default :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
206	}
207
208	// search the entity
209	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),nb_bytes);
210
211	// std::cout << entity << std::endl;
212
213	// Test the type of the address
214	if (entity.present == true)
215	{
216	switch (entity.segment->getType())
217	{
218	//**************************************************************
219	//***[ TTY ]************************************************
220	//**************************************************************
221	case data::TYPE_TARGET_TTY :
222	{
223	// Can't read a tty, must write
224	if (must_write == false)
225	{
226	bus_error = true;
227	break;
228	}
229
230	uint32_t num_tty = (address - entity.segment->getBase())>>4;
231	uint32_t num_print = ((address>>2) & 0x3);
232	_cout(true," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print);
233
234	switch (num_print)
235	{
236	case 0 : // Write TTY
237	{
238	uint32_t num_component_tty = entity.segment->getIndex();
239	char char_write = static_cast<char>(wdata&0xff);
240	bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
241	break;
242	}
243	case 1 : // STOP
244	{
245	_cout(true,"\n");
246	_cout(true,"***********************************************************************************************\n");
247	_cout(true,"*** [ STOP ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
248	,static_cast<uint32_t>(sc_simulation_time())
249	,static_cast<uint32_t>(address )
250	,static_cast<uint32_t>((wdata>>24)&0xff)
251	,static_cast<uint32_t>((wdata>>16)&0xff)
252	,static_cast<uint32_t>((wdata>> 8)&0xff)
253	,static_cast<uint32_t>((wdata>> 0)&0xff)
254	);
255	_cout(true,"***********************************************************************************************\n");
256	_cout(true,"\n");
257	_cout(true,"%s\n",(wdata == 0)?STR_OK:STR_KO);
258	_cout(true,"\n");
259
260	stop (context);
261
262	break;
263	}
264	case 2 : // PRINT
265	{
266	_cout(true,"\n");
267	_cout(true,"-----------------------------------------------------------------------------------------------\n");
268	_cout(true,"----- [ PRINT ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
269	,static_cast<uint32_t>(sc_simulation_time())
270	,static_cast<uint32_t>(address )
271	,static_cast<uint32_t>((wdata>>24)&0xff)
272	,static_cast<uint32_t>((wdata>>16)&0xff)
273	,static_cast<uint32_t>((wdata>> 8)&0xff)
274	,static_cast<uint32_t>((wdata>> 0)&0xff)
275	);
276	_cout(true,"-----------------------------------------------------------------------------------------------\n");
277	_cout(true,"\n");
278
279	break;
280	}
281	default :
282	{
283	_cout(true,"[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print);
284	bus_error = true;
285	}
286	}
287	break;
288	}
289
290	//**************************************************************
291	//***[ MEMORY ]*********************************************
292	//**************************************************************
293	case data::TYPE_TARGET_MEMORY :
294	{
295	_cout(ENVIRONMENT," * TYPE_TARGET_MEMORY\n");
296	_cout(ENVIRONMENT," * access : %x\n",address);
297
298	if (must_read == true)
299	{
300	// Read
301	_cout(ENVIRONMENT," * Read (%d bytes)\n",size);
302	bus_error \|= !component_data->read(address,nb_bytes,read_dram[0]); // always read a complete word
303
304	// Multiple copy
305	for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes)
306	memcpy(&(read_dram[0][it_size_data]),&(read_dram[0][0]),nb_bytes);
307
308	// Permutation if problem of endianness
309	if (endianness::isSameEndianness(context) == false)
310	read_dram[0] = endianness::swapBytes(read_dram[0] , size, nb_bytes);
311	}
312
313	if (must_write == true)
314	{
315	// Write
316	_cout(ENVIRONMENT," * Write (%d bytes)\n",size);
317	_cout(ENVIRONMENT," * Wdata : %x\n",wdata);
318	itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes);
319
320	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < size; it_nb_bytes ++)
321	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
322	}
323
324	break;
325	}
326	//**************************************************************
327	//***[ RAMLOCK ]********************************************
328	//**************************************************************
329	case data::TYPE_TARGET_RAMLOCK :
330	{
331	_cout(ENVIRONMENT," * TYPE_TARGET_RAMLOCK\n");
332
333	// Access is on a byte, else error
334	if (nb_bytes != 1)
335	{
336	bus_error = true;
337	break;
338	}
339
340	uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access
341	uint32_t num_component_ramlock = entity.segment->getIndex();
342
343	_cout(ENVIRONMENT," * num_ramlock : %d\n",num_ramlock );
344	_cout(ENVIRONMENT," * num_component_ramlock : %d\n",num_component_ramlock);
345
346	// No test : because out of range
347
348	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
349
350	// if (bus_error == true)
351	// break;
352
353	memset (read_dram[0],0,size);
354
355	if (must_read == true)
356	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock));
357	if (must_write == true)
358	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock));
359
360	break;
361	}
362
363	//**************************************************************
364	//***[ SIM2OS ]*********************************************
365	//**************************************************************
366	case data::TYPE_TARGET_SIM2OS :
367	{
368	_cout(ENVIRONMENT," * TYPE_TARGET_SIM2OS\n");
369
370	// Mapping :
371	// [0] number of service - Wonly - A write in this register lunch the execution of service
372	// [1] result - Ronly - Content the result of the service
373	// [2] error - Ronly - Content the code of errno
374	// [3+] argument - Wonly - it's all argument to execute the service
375
376	uint32_t num_reg = (address - entity.segment->getBase())>>2;
377
378	_cout(ENVIRONMENT," * num_reg : %d\n",num_reg);
379
380	switch (num_reg)
381	{
382	case 0 : // ---> number of service
383	{
384	if (must_write == false)
385	{
386	_cerr("<Environment::transition> SIM2OS[0] is not accessible in Read\n");
387	bus_error = true;
388	}
389	else
390	{
391	_cout(ENVIRONMENT," * service : %x\n",wdata);
392	component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata)));
393	}
394	break;
395	}
396	case 1 : // ---> result
397	{
398	if (must_read == false)
399	{
400	_cerr("<Environment::transition> SIM2OS[1] is not accessible in Write\n");
401	bus_error = true;
402	}
403	else
404	{
405	// Decomposition en groupe octect
406	Tdcache_data_t result = static_cast<Tdcache_data_t>(reinterpret_cast<uint64_t>(component_sim2os->result));
407	_cout(ENVIRONMENT," * result : %x\n",result);
408
409	itoa<Tdcache_data_t>(result,read_dram[0],size);
410	}
411	break;
412	}
413	case 2 : // ---> error
414	{
415	if (must_read == false)
416	{
417	_cerr("<Environment::transition> SIM2OS[2] is not accessible in Write\n");
418	bus_error = true;
419	}
420	else
421	{
422	// Decomposition en groupe octect
423	Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error;
424	_cout(ENVIRONMENT," * error : %x\n",error);
425
426	itoa<Tdcache_data_t>(error,read_dram[0],size);
427	}
428
429	break;
430	}
431	default : //---> argument
432	{
433	if (must_write == false)
434	{
435	_cerr("<Environment::transition> SIM2OS[%d] is not accessible in Read\n",num_reg);
436	bus_error = true;
437	}
438	else
439	{
440	_cout(ENVIRONMENT," * argument[%d] : %x\n",num_reg-1,wdata);
441	component_sim2os->parameter(num_reg-2,(void *)wdata);
442	}
443	break;
444	}
445	}
446
447	break;
448	}
449
450	default :
451	{
452	_cerr("<Environment::transition> Dcache_req : Unknow type\n");
453	exit(1);
454	break;
455	}
456	}
457	uncached \|= entity.segment->getUncached();
458	}
459	else
460	{
461	// entity is not present, or is present but is not a memory : have a bus error
462	bus_error = true;
463	uncached = true;
464	}
465
466	if ((must_write == true) and (bus_error == false))
467	{
468	// Permutation if problem of endianness
469	if (endianness::isSameEndianness(context) == false)
470	write_dram = endianness::swapBytes(write_dram, size, nb_bytes);
471
472	bus_error \|= !component_data->write(address, nb_bytes, write_dram); // take the good access
473	}
474
475	// Acces at the cache !!!
476	// Cache WRITE ALLOCATE (becauce compute latence always; )
477	Cache_Access cache_type = dreq_type2cache_type (type,uncached);
478	uint32_t latence = component_cache->latence(cache::DATA_CACHE,
479	i,
480	j,
481	address,
482	context,
483	cache_type.type,
484	cache_type.direction);
485
486	// If is a respons -> compute the latence and push in the write_buffer
487	if (must_ack or (must_ack_on_error and bus_error))
488	{
489	if (bus_error == true)
490	{
491	_cout(ENVIRONMENT," * Dcache : have a bus error\n");
492	_cout(ENVIRONMENT," * entity : %d\n",i);
493	_cout(ENVIRONMENT," * port : %d\n",j);
494	_cout(ENVIRONMENT," * req_addr : 0x%x\n",address);
495	_cout(ENVIRONMENT," * req_trdid : %d\n",context);
496	_cout(ENVIRONMENT," * req_pktid : %d\n",packet );
497
498	// Write in data [0] the bad address (32bit or 64bits )
499	itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8);
500	}
501
502	_cout(ENVIRONMENT," * Rdata : ");
503	for (uint32_t i=0; i<nb_bytes; i++)
504	__cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][i]));
505	_cout(ENVIRONMENT,".\n");
506
507	// Simplification : the size of a line is a multiple of size_iword (no test)
508	drsp_t * rsp = new drsp_t(context,
509	packet,
510	1,
511	size,
512	read_dram,
513	(bus_error==true)?DCACHE_ERROR_BUS_ERROR:DCACHE_ERROR_NONE);
514	component_buffer_drsp [i]->push(latence,rsp);
515	}
516	}
517
518	//=============================================================================
519	//===== [ OTHERS ]=============================================================
520	//=============================================================================
521
522	// Transition for each component
523	component_cache -> transition();
524	for (uint32_t i=0; i<param->nb_entity; i++)
525	{
526	component_buffer_irsp [i]->transition();
527	component_buffer_drsp [i]->transition();
528	}
529	component_sim2os->transition();
530	}
531	}
532
533	// // ******************
534	// // *** DCACHE ***
535	// // ******************
536
537	// for (uint32_t j = 0; j < nb_dport [i]; j ++)
538	// {
539	// // Test if transaction
540
541	// if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false)
542	// continue;
543
544	// entity_t entity = component_data->entity((uint32_t)DCACHE [i][j].REQ_ADDR.read(), SIZE_DDATA/8);
545
546	// bool uncached = DCACHE [i][j].REQ_UNC.read();
547	// bool bus_error = false;
548
549	// uint32_t addr = (uint32_t) DCACHE [i][j].REQ_ADDR.read();
550	// sc_uint<SIZE_DDATA> wdata = DCACHE[i][j].REQ_WDATA .read();
551	// sc_uint<3> type = DCACHE[i][j].REQ_TYPE .read();
552	// uint32_t nb_bytes = access_nb_bytes(DCACHE[i][j].REQ_ACCESS.read());
553	// // A lot of flag
554	// bool must_read = ((type == DTYPE_READ ));
555	// bool must_write = ((type == DTYPE_WRITE ) \|\|
556	// (type == DTYPE_WRITE_ACK ) );
557	// bool must_ack = ((type == DTYPE_READ ) \|\|
558	// (type == DTYPE_WRITE_ACK ) );
559
560	// // Test the type of the address
561	// if (entity.present == true)
562	// {
563	// switch (entity.segment->getType())
564	// {
565	// // ACCESS AT A RAM
566	// case data::TYPE_TARGET_MEMORY :
567	// {
568	// if (must_read == true)
569	// {
570	// // Read
571	// bus_error \|= !component_data->read(addr ,
572	// SIZE_DDATA/8 , // always read a complete word
573	// read_dram );
574
575	// for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes)
576	// memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes);
577
578	// // Permutation if problem of endianness
579	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
580	// read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes);
581	// }
582
583	// if (must_write == true)
584	// {
585	// // Write
586	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
587	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
588	// }
589	// break;
590	// }
591	// //ACCESS AT THE TTY
592	// case TYPE_TTY :
593	// {
594	// if (must_write == false)
595	// {
596	// bus_error = true;
597	// break;
598	// }
599	// uint32_t num_tty = (addr - entity.segment->getBase())>>4;
600	// uint32_t num_print = ((addr>>2) & 0x3);
601
602	// switch (num_print)
603	// {
604	// case 0 : // Write TTY
605	// {
606	// uint32_t num_component_tty = entity.segment->getIndex();
607	// char char_write = (char)wdata.range( 7, 0);
608	// bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
609	// break;
610	// }
611	// case 1 : // STOP
612	// {
613	// cout("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
614	// ,(unsigned int)sc_simulation_time()
615	// ,(unsigned int)addr
616	// ,(unsigned int)wdata.range(31,24)
617	// ,(unsigned int)wdata.range(23,16)
618	// ,(unsigned int)wdata.range(15, 8)
619	// ,(unsigned int)wdata.range( 7, 0)
620	// );
621
622	// uint32_t trdid = (uint32_t) DCACHE[i][j].REQ_TRDID.read();
623
624	// if (context_stop [trdid] == false)
625	// {
626	// context_stop [trdid] = true;
627	// nb_context_stop ++;
628
629	// if (nb_context_stop >= nb_context)
630	// sc_stop();
631	// }
632
633	// break;
634	// }
635	// case 2 : // PRINT
636	// {
637	// cout("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
638	// ,(unsigned int)sc_simulation_time()
639	// ,(unsigned int)addr
640	// ,(unsigned int)wdata.range(31,24)
641	// ,(unsigned int)wdata.range(23,16)
642	// ,(unsigned int)wdata.range(15, 8)
643	// ,(unsigned int)wdata.range( 7, 0)
644	// );
645
646	// break;
647	// }
648	// default :
649	// {
650	// cout("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);
651	// exit(1);
652	// }
653	// }
654
655	// break;
656	// }
657	// case TYPE_RAMLOCK :
658	// {
659	// // Access is on a byte, else error
660	// if (nb_bytes != 1)
661	// {
662	// bus_error = true;
663	// break;
664	// }
665	// uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access
666	// uint32_t num_component_ramlock = entity.segment->getIndex();
667	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
668
669	// if (bus_error == true)
670	// break;
671
672	// memset (read_dram,0,SIZE_DDATA/8);
673
674	// if (must_read == true)
675	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock);
676	// if (must_write == true)
677	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock);
678
679	// /*
680	// cout("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time());
681	// cout(" * addr : %.8x\n" ,(uint32_t)addr);
682	// cout(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read());
683	// cout(" * r/w : %d/%d\n",must_read,must_write);
684	// cout(" * val : %d\n" ,(uint32_t)read_dram[0]);
685	// */
686	// break;
687	// }
688	// case TYPE_SIM2OS :
689	// {
690	// // Mapping :
691	// // [0] number of service - Wonly - A write in this register lunch the execution of service
692	// // [1] result - Ronly - Content the result of the service
693	// // [2] error - Ronly - Content the code of errno
694	// // [3+] argument - Wonly - it's all argument to execute the service
695
696	// uint32_t num_reg = (addr - entity.segment->getBase())>>2;
697
698	// switch (num_reg)
699	// {
700	// case 0 : // ---> number of service
701	// {
702	// if (must_write == false)
703	// {
704	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl;
705	// bus_error = true;
706	// }
707	// else
708	// {
709	// cout("<sim2os> service : %.8x\n",(uint32_t)wdata);
710	// component_sim2os->execute(int2service((uint32_t)wdata));
711	// }
712	// break;
713	// }
714	// case 1 : // ---> result
715	// {
716	// if (must_read == false)
717	// {
718	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl;
719	// bus_error = true;
720	// }
721	// else
722	// {
723	// // Decomposition en groupe octect
724	// uint32_t result = (uint32_t) component_sim2os->result;
725	// cout("<sim2os> result : %.8x (%d)\n",result,result);
726
727	// read_dram = itoa(result,read_dram,SIZE_DDATA/8);
728	// }
729	// break;
730	// }
731	// case 2 : // ---> error
732	// {
733	// if (must_read == false)
734	// {
735	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl;
736	// bus_error = true;
737	// }
738	// else
739	// {
740	// // Decomposition en groupe octect
741	// uint32_t error = (uint32_t) component_sim2os->error;
742	// cout("<sim2os> error : %.8x\n",error);
743	// read_dram = itoa(error ,read_dram,SIZE_DDATA/8);
744	// }
745	// break;
746	// }
747	// default : // ---> argument
748	// {
749	// if (must_write == false)
750	// {
751	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl;
752	// bus_error = true;
753	// }
754	// else
755	// {
756	// uint32_t data = (uint32_t)wdata;
757	// cout("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);
758	// component_sim2os->parameter(num_reg-2,(void *)data);
759	// }
760	// break;
761	// }
762	// }//end switch num_reg
763
764	// break;
765	// }
766	// default :
767	// {
768	// // Have a bus error
769	// bus_error = true;
770	// break;
771	// }
772	// }// switch
773	// uncached \|= entity.segment->getUncached();
774	// }
775	// else
776	// uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist
777
778
779	// if ((must_write == true) && (bus_error == false))
780	// {
781	// // Permutation if problem of endianness
782	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
783	// write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes);
784
785	// bus_error \|= !component_data->write(addr ,
786	// nb_bytes, // take the good access
787	// write_dram );
788	// }
789
790
791	// // Acces at the cache !!!
792	// Cache_Access cache_type = dreq_type2cache_type (type, uncached);
793
794	// uint32_t latence = component_cache->latence(DATA_CACHE ,
795	// i ,
796	// j ,
797	// (uint32_t)DCACHE [i][j].REQ_ADDR .read() ,
798	// (uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
799	// cache_type.type ,
800	// cache_type.direction );
801
802	// // If is a respons -> compute the latence and push in the write_buffer
803	// if ( must_ack == true)
804	// {
805	// if (bus_error == true)
806	// cout("Dcache : have a bus error");
807	// component_buffer_drsp [i]->push(latence,
808	// Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
809	// (uint32_t)DCACHE [i][j].REQ_PKTID.read() ,
810	// 1 ,
811	// SIZE_DDATA/8 ,
812	// &read_dram ,
813	// (bus_error==true)?ERR_BUS:ERR_NO )
814	// );
815	// }
816	// }// dnb_port
817	// }//i
818
819
820	};

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