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source: trunk/IPs/systemC/Environment/src/Environment_transition.cpp @ 114

Last change on this file since 114 was 114, checked in by rosiere, 15 years ago
1) Fix bug with previous commit 2) Add test libc 3) Change Dhrystone
Property svn:keywords set to `Id`
File size: 30.1 KB

Line
1	#include "../include/Environment.h"
2
3	#define CYCLE_MAX 0
4	#include "../../processor/Morpheo/Common/include/Test.h"
5
6	using namespace morpheo;
7
8	namespace environment {
9
10	void Environment::transition (void)
11	{
12	if (NRESET->read() == 0)
13	{
14	reset ();
15	}
16	else
17	{
18	//=============================================================================
19	//===== [ ICACHE - RESPONS ]===================================================
20	//=============================================================================
21	for (uint32_t i = 0; i < param->nb_entity; i++)
22	for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--)
23	if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read())
24	{
25	delete component_buffer_irsp [i]->read(j)._data;
26	component_buffer_irsp [i]->pop(j);
27	}
28	//=============================================================================
29	//===== [ DCACHE - RESPONS ]===================================================
30	//=============================================================================
31	for (uint32_t i = 0; i < param->nb_entity; i++)
32	for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--)
33	if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read())
34	{
35	delete component_buffer_drsp [i]->read(j)._data;
36	component_buffer_drsp [i]->pop(j);
37	}
38
39	//=============================================================================
40	//===== [ ICACHE - RESPONS ]===================================================
41	//=============================================================================
42	for (uint32_t i=0; i<param->nb_entity; i++)
43	for (uint32_t j=0; j <param->icache_dedicated_nb_port [i]; j++)
44	if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j])
45	{
46	_cout(ENVIRONMENT, "ICACHE_REQ [%d] : Transaction accepted\n",i);
47
48	Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
49	Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
50	Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read()<<2;
51	Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read();
52	uint32_t size = (param->iaccess_size_address [i]+2)/8;
53
54	_cout(ENVIRONMENT," * information\n");
55	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
56	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
57	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
58	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
59	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
60
61	// search the entity
62	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
63
64	bool uncached ;
65	bool bus_error;
66	bool must_read = (type == ICACHE_TYPE_LOAD);
67	bool must_ack = (type == ICACHE_TYPE_LOAD);
68	bool must_ack_on_error = (type == ICACHE_TYPE_LOAD);
69
70	// Test the type of the address : if != MEMORY -> error
71	if ((entity.present == true) and
72	(entity.segment->getType() == data::TYPE_TARGET_MEMORY))
73	{
74	_cout(ENVIRONMENT," * OK !\n");
75	bus_error = false;
76	uncached = entity.segment->getUncached();
77
78	if (must_read == true) // Test if must read the ram
79	{
80	_cout(ENVIRONMENT," * must read\n");
81	// Read all instruction
82	for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++)
83	{
84	uint32_t addr = address+k*(size);
85	_cout(ENVIRONMENT," * addr : %.8x\n",addr);
86
87	bus_error \|= !component_data->read(addr,size,read_iram[k]);
88
89	// Swap if endienness is different
90	if (endianness::isSameEndianness(context) == false)
91	{
92	read_iram[k] = endianness::swapBytes(read_iram[k],size,size);
93	}
94
95	_cout(ENVIRONMENT," * inst :");
96	for (int32_t cpt=(param->iaccess_size_instruction[context]/8)-1; cpt>=0; --cpt)
97	_cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt]));
98	_cout(ENVIRONMENT, "\n");
99	}
100	}
101	}
102	else
103	{
104	_cout(ENVIRONMENT, " * KO !\n");
105	_cout(ENVIRONMENT, " * present : %d\n",entity.present);
106	if (entity.present)
107	_cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY);
108
109	// entity is not present, or is present but is not a memory : have a bus error
110	bus_error = true;
111	uncached = true;
112	}
113
114	Cache_Access cache_type = ireq_type2cache_type (type,uncached);
115	uint32_t latence = component_cache->latence(cache::INSTRUCTION_CACHE,
116	i,
117	j,
118	address,
119	context,
120	cache_type.type,
121	cache_type.direction);
122
123	_cout(ENVIRONMENT, " * latence : %d\n",latence);
124
125	// If is a respons -> compute the latence and push in the write_buffer
126	if (must_ack or (must_ack_on_error and bus_error))
127	{
128	_cout(ENVIRONMENT, " * must ack\n");
129
130	if (bus_error == true)
131	{
132	_cout(ENVIRONMENT," * Icache : have a bus error\n");
133	_cout(ENVIRONMENT," * entity : %d\n",i);
134	_cout(ENVIRONMENT," * port : %d\n",j);
135	_cout(ENVIRONMENT," * req_addr : %x\n",address);
136	_cout(ENVIRONMENT," * req_trdid : %d\n",context);
137	_cout(ENVIRONMENT," * req_pktid : %d\n",packet );
138
139	// Write in instruction [0] the bad address (only 32bit ....)
140	itoa<Ticache_address_t>(address,read_iram[0],param->iaccess_size_instruction[i]/8);
141	}
142
143	// Simplification : the size of a line is a multiple of size_iword (no test)
144	_cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i);
145
146	irsp_t * rsp = new irsp_t(context,
147	packet,
148	param->iaccess_nb_instruction[i],
149	size,
150	read_iram,
151	(bus_error==true)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
152	component_buffer_irsp [i]->push(latence,rsp);
153	}
154
155	_cout(ENVIRONMENT, " * End request\n");
156	}
157
158	//=============================================================================
159	//===== [ DCACHE - REQUEST ]===================================================
160	//=============================================================================
161	for (uint32_t i=0; i<param->nb_entity; i++)
162	for (uint32_t j=0; j <param->dcache_dedicated_nb_port [i]; j++)
163	if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j])
164	{
165	_cout(ENVIRONMENT, "DCACHE_REQ [%d] : Transaction accepted\n",i);
166
167	Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
168	Tdcache_packet_t packet = DCACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
169	Tdcache_address_t address = DCACHE_REQ_ADDRESS [i][j]->read();
170	Tdcache_data_t wdata = DCACHE_REQ_WDATA [i][j]->read();
171	Tdcache_type_t type = DCACHE_REQ_TYPE [i][j]->read();
172	uint32_t size = param->daccess_size_data [i]/8;
173
174	_cout(ENVIRONMENT," * information\n");
175	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
176	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
177	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
178	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
179	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
180
181	bool uncached = false;
182	bool bus_error = false;
183
184	uint32_t nb_bytes = size;
185	bool must_read ;
186	bool must_write;
187	bool must_ack ;
188	bool must_ack_on_error;
189
190	switch (type)
191	{
192	case DCACHE_TYPE_LOAD_8 :{nb_bytes=1; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
193	case DCACHE_TYPE_LOAD_16 :{nb_bytes=2; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
194	case DCACHE_TYPE_LOAD_32 :{nb_bytes=4; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
195	case DCACHE_TYPE_LOAD_64 :{nb_bytes=8; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
196	case DCACHE_TYPE_LOCK :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
197	case DCACHE_TYPE_INVALIDATE :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
198	case DCACHE_TYPE_PREFETCH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
199	case DCACHE_TYPE_FLUSH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
200	case DCACHE_TYPE_SYNCHRONIZATION :{ must_read=false; must_write=false; must_ack=true ; must_ack_on_error=false; break;}
201	case DCACHE_TYPE_STORE_8 :{nb_bytes=1; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
202	case DCACHE_TYPE_STORE_16 :{nb_bytes=2; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
203	case DCACHE_TYPE_STORE_32 :{nb_bytes=4; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
204	case DCACHE_TYPE_STORE_64 :{nb_bytes=8; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
205	default :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
206	}
207
208	// search the entity
209	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),nb_bytes);
210
211	// std::cout << entity << std::endl;
212
213	// Test the type of the address
214	if (entity.present == true)
215	{
216	switch (entity.segment->getType())
217	{
218	//**************************************************************
219	//***[ TTY ]************************************************
220	//**************************************************************
221	case data::TYPE_TARGET_TTY :
222	{
223	// Can't read a tty, must write
224	if (must_write == false)
225	{
226	bus_error = true;
227	break;
228	}
229
230	uint32_t num_tty = (address - entity.segment->getBase())>>4;
231	uint32_t num_print = ((address>>2) & 0x3);
232	_cout(ENVIRONMENT," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print);
233
234	switch (num_print)
235	{
236	case 0 : // Write TTY
237	{
238	uint32_t num_component_tty = entity.segment->getIndex();
239	char char_write = static_cast<char>(wdata&0xff);
240	bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
241	break;
242	}
243	case 1 : // STOP
244	{
245	printf("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
246	,static_cast<uint32_t>(sc_simulation_time())
247	,static_cast<uint32_t>(address )
248	,static_cast<uint32_t>((wdata>>24)&0xff)
249	,static_cast<uint32_t>((wdata>>16)&0xff)
250	,static_cast<uint32_t>((wdata>> 8)&0xff)
251	,static_cast<uint32_t>((wdata>> 0)&0xff)
252	);
253
254	if (wdata == 0)
255	std::cout << STR_OK << std::endl;
256	else
257	std::cout << STR_KO << std::endl;
258
259	stop (context);
260
261	break;
262	}
263	case 2 : // PRINT
264	{
265	printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
266	,static_cast<uint32_t>(sc_simulation_time())
267	,static_cast<uint32_t>(address )
268	,static_cast<uint32_t>((wdata>>24)&0xff)
269	,static_cast<uint32_t>((wdata>>16)&0xff)
270	,static_cast<uint32_t>((wdata>> 8)&0xff)
271	,static_cast<uint32_t>((wdata>> 0)&0xff)
272	);
273
274	break;
275	}
276	default :
277	{
278	printf("[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print);
279	bus_error = true;
280	}
281	}
282	break;
283	}
284
285	//**************************************************************
286	//***[ MEMORY ]*********************************************
287	//**************************************************************
288	case data::TYPE_TARGET_MEMORY :
289	{
290	_cout(ENVIRONMENT,"MEMORY\n");
291	_cout(ENVIRONMENT,"access : %x\n",address);
292
293	if (must_read == true)
294	{
295	// Read
296	_cout(ENVIRONMENT," * Read (%d bytes)\n",size);
297	bus_error \|= !component_data->read(address,nb_bytes,read_dram[0]); // always read a complete word
298
299	_cout(ENVIRONMENT," * Rdata : ");
300	for (uint32_t i=0; i<nb_bytes; i++)
301	_cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][i]));
302	_cout(ENVIRONMENT,".\n");
303
304	// Multiple copy
305	for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes)
306	memcpy(&(read_dram[0][it_size_data]),&(read_dram[0][0]),nb_bytes);
307
308	// Permutation if problem of endianness
309	if (endianness::isSameEndianness(context) == false)
310	read_dram[0] = endianness::swapBytes(read_dram[0] , size, nb_bytes);
311	}
312
313	if (must_write == true)
314	{
315	// Write
316	_cout(ENVIRONMENT," * Write (%d bytes)\n",size);
317	_cout(ENVIRONMENT," * Wdata : %x\n",wdata);
318	itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes);
319
320	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < size; it_nb_bytes ++)
321	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
322	}
323
324	break;
325	}
326	//**************************************************************
327	//***[ RAMLOCK ]********************************************
328	//**************************************************************
329	case data::TYPE_TARGET_RAMLOCK :
330	{
331	// Access is on a byte, else error
332	if (nb_bytes != 1)
333	{
334	bus_error = true;
335	break;
336	}
337
338	uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access
339	uint32_t num_component_ramlock = entity.segment->getIndex();
340
341	// No test : because out of range
342
343	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
344
345	// if (bus_error == true)
346	// break;
347
348	memset (read_dram[0],0,size);
349
350	if (must_read == true)
351	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock));
352	if (must_write == true)
353	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock));
354
355	break;
356	}
357
358	//**************************************************************
359	//***[ SIM2OS ]*********************************************
360	//**************************************************************
361	case data::TYPE_TARGET_SIM2OS :
362	{
363	// Mapping :
364	// [0] number of service - Wonly - A write in this register lunch the execution of service
365	// [1] result - Ronly - Content the result of the service
366	// [2] error - Ronly - Content the code of errno
367	// [3+] argument - Wonly - it's all argument to execute the service
368
369	uint32_t num_reg = (address - entity.segment->getBase())>>2;
370
371	switch (num_reg)
372	{
373	case 0 : // ---> number of service
374	{
375	if (must_write == false)
376	{
377	_cerr("<Environment::transition> SIM2OS[0] is not accessible in Read\n");
378	bus_error = true;
379	}
380	else
381	{
382	_cout(ENVIRONMENT,"<sim2os> service : %x\n",wdata);
383	component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata)));
384	}
385	break;
386	}
387	case 1 : // ---> result
388	{
389	if (must_read == false)
390	{
391	_cerr("<Environment::transition> SIM2OS[1] is not accessible in Write\n");
392	bus_error = true;
393	}
394	else
395	{
396	// Decomposition en groupe octect
397	Tdcache_data_t result = static_cast<Tdcache_data_t>(reinterpret_cast<uint64_t>(component_sim2os->result));
398	_cout(ENVIRONMENT,"<sim2os> result : %x\n",result);
399
400	itoa<Tdcache_data_t>(result,read_dram[0],size);
401	}
402	break;
403	}
404	case 2 : // ---> error
405	{
406	if (must_read == false)
407	{
408	_cerr("<Environment::transition> SIM2OS[2] is not accessible in Write\n");
409	bus_error = true;
410	}
411	else
412	{
413	// Decomposition en groupe octect
414	Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error;
415	_cout(ENVIRONMENT,"<sim2os> error : %x\n",error);
416
417	itoa<Tdcache_data_t>(error,read_dram[0],size);
418	}
419
420	break;
421	}
422	default : //---> argument
423	{
424	if (must_write == false)
425	{
426	_cerr("<Environment::transition> SIM2OS[%d] is not accessible in Read\n",num_reg);
427	bus_error = true;
428	}
429	else
430	{
431	_cout(ENVIRONMENT,"<sim2os> argument[%d] : %x\n",num_reg-1,wdata);
432	component_sim2os->parameter(num_reg-2,(void *)wdata);
433	}
434	break;
435	}
436	}
437
438	break;
439	}
440
441	default :
442	{
443	_cerr("<Environment::transition> Dcache_req : Unknow type\n");
444	exit(1);
445	break;
446	}
447	}
448	uncached \|= entity.segment->getUncached();
449	}
450	else
451	{
452	// entity is not present, or is present but is not a memory : have a bus error
453	bus_error = true;
454	uncached = true;
455	}
456
457	if ((must_write == true) and (bus_error == false))
458	{
459	// Permutation if problem of endianness
460	if (endianness::isSameEndianness(context) == false)
461	write_dram = endianness::swapBytes(write_dram, size, nb_bytes);
462
463	bus_error \|= !component_data->write(address, nb_bytes, write_dram); // take the good access
464	}
465
466	// Acces at the cache !!!
467	// Cache WRITE ALLOCATE (becauce compute latence always; )
468	Cache_Access cache_type = dreq_type2cache_type (type,uncached);
469	uint32_t latence = component_cache->latence(cache::DATA_CACHE,
470	i,
471	j,
472	address,
473	context,
474	cache_type.type,
475	cache_type.direction);
476
477	// If is a respons -> compute the latence and push in the write_buffer
478	if (must_ack or (must_ack_on_error and bus_error))
479	{
480	if (bus_error == true)
481	{
482	_cout(ENVIRONMENT," * Dcache : have a bus error\n");
483	_cout(ENVIRONMENT," * entity : %d\n",i);
484	_cout(ENVIRONMENT," * port : %d\n",j);
485	_cout(ENVIRONMENT," * req_addr : 0x%x\n",address);
486	_cout(ENVIRONMENT," * req_trdid : %d\n",context);
487	_cout(ENVIRONMENT," * req_pktid : %d\n",packet );
488
489	// Write in data [0] the bad address (32bit or 64bits )
490	itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8);
491	}
492
493	// Simplification : the size of a line is a multiple of size_iword (no test)
494	drsp_t * rsp = new drsp_t(context,
495	packet,
496	1,
497	size,
498	read_dram,
499	(bus_error==true)?DCACHE_ERROR_BUS_ERROR:DCACHE_ERROR_NONE);
500	component_buffer_drsp [i]->push(latence,rsp);
501	}
502	}
503	//=============================================================================
504	//===== [ OTHERS ]=============================================================
505	//=============================================================================
506
507	// Transition for each component
508	component_cache -> transition();
509	for (uint32_t i=0; i<param->nb_entity; i++)
510	{
511	component_buffer_irsp [i]->transition();
512	component_buffer_drsp [i]->transition();
513	}
514	component_sim2os->transition();
515	}
516	}
517
518	// // ******************
519	// // *** DCACHE ***
520	// // ******************
521
522	// for (uint32_t j = 0; j < nb_dport [i]; j ++)
523	// {
524	// // Test if transaction
525	// // cout << "[" << i << "]"
526	// // << "[" << j << "] "
527	// // << "dreq_val : " << DCACHE [i][j].REQ_VAL.read() << " "
528	// // << "dreq_ack : " << dreq_ack [i][j] << endl;
529
530	// if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false)
531	// continue;
532
533	// entity_t entity = component_data->entity((uint32_t)DCACHE [i][j].REQ_ADDR.read(), SIZE_DDATA/8);
534
535	// bool uncached = DCACHE [i][j].REQ_UNC.read();
536	// bool bus_error = false;
537
538	// uint32_t addr = (uint32_t) DCACHE [i][j].REQ_ADDR.read();
539	// sc_uint<SIZE_DDATA> wdata = DCACHE[i][j].REQ_WDATA .read();
540	// sc_uint<3> type = DCACHE[i][j].REQ_TYPE .read();
541	// uint32_t nb_bytes = access_nb_bytes(DCACHE[i][j].REQ_ACCESS.read());
542	// // A lot of flag
543	// bool must_read = ((type == DTYPE_READ ));
544	// bool must_write = ((type == DTYPE_WRITE ) \|\|
545	// (type == DTYPE_WRITE_ACK ) );
546	// bool must_ack = ((type == DTYPE_READ ) \|\|
547	// (type == DTYPE_WRITE_ACK ) );
548
549	// // Test the type of the address
550	// if (entity.present == true)
551	// {
552	// switch (entity.segment->getType())
553	// {
554	// // ACCESS AT A RAM
555	// case data::TYPE_TARGET_MEMORY :
556	// {
557	// if (must_read == true)
558	// {
559	// // Read
560	// bus_error \|= !component_data->read(addr ,
561	// SIZE_DDATA/8 , // always read a complete word
562	// read_dram );
563
564	// for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes)
565	// memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes);
566
567	// // Permutation if problem of endianness
568	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
569	// read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes);
570	// }
571
572	// if (must_write == true)
573	// {
574	// // Write
575	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
576	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
577	// }
578	// break;
579	// }
580	// //ACCESS AT THE TTY
581	// case TYPE_TTY :
582	// {
583	// if (must_write == false)
584	// {
585	// bus_error = true;
586	// break;
587	// }
588	// uint32_t num_tty = (addr - entity.segment->getBase())>>4;
589	// uint32_t num_print = ((addr>>2) & 0x3);
590
591	// switch (num_print)
592	// {
593	// case 0 : // Write TTY
594	// {
595	// uint32_t num_component_tty = entity.segment->getIndex();
596	// char char_write = (char)wdata.range( 7, 0);
597	// bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
598	// break;
599	// }
600	// case 1 : // STOP
601	// {
602	// printf("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
603	// ,(unsigned int)sc_simulation_time()
604	// ,(unsigned int)addr
605	// ,(unsigned int)wdata.range(31,24)
606	// ,(unsigned int)wdata.range(23,16)
607	// ,(unsigned int)wdata.range(15, 8)
608	// ,(unsigned int)wdata.range( 7, 0)
609	// );
610
611	// uint32_t trdid = (uint32_t) DCACHE[i][j].REQ_TRDID.read();
612
613	// if (context_stop [trdid] == false)
614	// {
615	// context_stop [trdid] = true;
616	// nb_context_stop ++;
617
618	// if (nb_context_stop >= nb_context)
619	// sc_stop();
620	// }
621
622	// break;
623	// }
624	// case 2 : // PRINT
625	// {
626	// printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
627	// ,(unsigned int)sc_simulation_time()
628	// ,(unsigned int)addr
629	// ,(unsigned int)wdata.range(31,24)
630	// ,(unsigned int)wdata.range(23,16)
631	// ,(unsigned int)wdata.range(15, 8)
632	// ,(unsigned int)wdata.range( 7, 0)
633	// );
634
635	// break;
636	// }
637	// default :
638	// {
639	// printf("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);
640	// exit(1);
641	// }
642	// }
643
644	// break;
645	// }
646	// case TYPE_RAMLOCK :
647	// {
648	// // Access is on a byte, else error
649	// if (nb_bytes != 1)
650	// {
651	// bus_error = true;
652	// break;
653	// }
654	// uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access
655	// uint32_t num_component_ramlock = entity.segment->getIndex();
656	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
657
658	// if (bus_error == true)
659	// break;
660
661	// memset (read_dram,0,SIZE_DDATA/8);
662
663	// if (must_read == true)
664	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock);
665	// if (must_write == true)
666	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock);
667
668	// /*
669	// printf("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time());
670	// printf(" * addr : %.8x\n" ,(uint32_t)addr);
671	// printf(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read());
672	// printf(" * r/w : %d/%d\n",must_read,must_write);
673	// printf(" * val : %d\n" ,(uint32_t)read_dram[0]);
674	// */
675	// break;
676	// }
677	// case TYPE_SIM2OS :
678	// {
679	// // Mapping :
680	// // [0] number of service - Wonly - A write in this register lunch the execution of service
681	// // [1] result - Ronly - Content the result of the service
682	// // [2] error - Ronly - Content the code of errno
683	// // [3+] argument - Wonly - it's all argument to execute the service
684
685	// uint32_t num_reg = (addr - entity.segment->getBase())>>2;
686
687	// switch (num_reg)
688	// {
689	// case 0 : // ---> number of service
690	// {
691	// if (must_write == false)
692	// {
693	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl;
694	// bus_error = true;
695	// }
696	// else
697	// {
698	// printf("<sim2os> service : %.8x\n",(uint32_t)wdata);
699	// component_sim2os->execute(int2service((uint32_t)wdata));
700	// }
701	// break;
702	// }
703	// case 1 : // ---> result
704	// {
705	// if (must_read == false)
706	// {
707	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl;
708	// bus_error = true;
709	// }
710	// else
711	// {
712	// // Decomposition en groupe octect
713	// uint32_t result = (uint32_t) component_sim2os->result;
714	// printf("<sim2os> result : %.8x (%d)\n",result,result);
715
716	// read_dram = itoa(result,read_dram,SIZE_DDATA/8);
717	// }
718	// break;
719	// }
720	// case 2 : // ---> error
721	// {
722	// if (must_read == false)
723	// {
724	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl;
725	// bus_error = true;
726	// }
727	// else
728	// {
729	// // Decomposition en groupe octect
730	// uint32_t error = (uint32_t) component_sim2os->error;
731	// printf("<sim2os> error : %.8x\n",error);
732	// read_dram = itoa(error ,read_dram,SIZE_DDATA/8);
733	// }
734	// break;
735	// }
736	// default : // ---> argument
737	// {
738	// if (must_write == false)
739	// {
740	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl;
741	// bus_error = true;
742	// }
743	// else
744	// {
745	// uint32_t data = (uint32_t)wdata;
746	// printf("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);
747	// component_sim2os->parameter(num_reg-2,(void *)data);
748	// }
749	// break;
750	// }
751	// }//end switch num_reg
752
753	// break;
754	// }
755	// default :
756	// {
757	// // Have a bus error
758	// bus_error = true;
759	// break;
760	// }
761	// }// switch
762	// uncached \|= entity.segment->getUncached();
763	// }
764	// else
765	// uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist
766
767
768	// if ((must_write == true) && (bus_error == false))
769	// {
770	// // Permutation if problem of endianness
771	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
772	// write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes);
773
774	// bus_error \|= !component_data->write(addr ,
775	// nb_bytes, // take the good access
776	// write_dram );
777	// }
778
779
780	// // Acces at the cache !!!
781	// Cache_Access cache_type = dreq_type2cache_type (type, uncached);
782
783	// uint32_t latence = component_cache->latence(DATA_CACHE ,
784	// i ,
785	// j ,
786	// (uint32_t)DCACHE [i][j].REQ_ADDR .read() ,
787	// (uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
788	// cache_type.type ,
789	// cache_type.direction );
790
791	// // If is a respons -> compute the latence and push in the write_buffer
792	// if ( must_ack == true)
793	// {
794	// if (bus_error == true)
795	// cout << "Dcache : have a bus error" << endl;
796	// component_buffer_drsp [i]->push(latence,
797	// Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
798	// (uint32_t)DCACHE [i][j].REQ_PKTID.read() ,
799	// 1 ,
800	// SIZE_DDATA/8 ,
801	// &read_dram ,
802	// (bus_error==true)?ERR_BUS:ERR_NO )
803	// );
804	// }
805	// }// dnb_port
806	// }//i
807
808
809	};

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