source: trunk/IPs/systemC/Environment/src/Environment_transition.cpp@ 127

Last change on this file since 127 was 124, checked in by rosiere, 17 years ago

1) Add test and configuration
2) Fix Bug
3) Add log file in load store unit
4) Fix Bug in environment
  • Property svn:keywords set to Id
File size: 31.6 KB
Line 
1#include "../include/Environment.h"
2
3#define CYCLE_MAX 0
4#include "../../processor/Morpheo/Common/include/Test.h"
5
6using namespace morpheo;
7
8namespace environment {
9
10 void Environment::transition (void)
11 {
12 if (NRESET->read() == 0)
13 {
14 reset ();
15 }
16 else
17 {
18 //=============================================================================
19 //===== [ ICACHE - RESPONS ]===================================================
20 //=============================================================================
21 for (uint32_t i = 0; i < param->nb_entity; i++)
22 for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--)
23 if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read())
24 {
25 delete component_buffer_irsp [i]->read(j)._data;
26 component_buffer_irsp [i]->pop(j);
27 }
28 //=============================================================================
29 //===== [ DCACHE - RESPONS ]===================================================
30 //=============================================================================
31 for (uint32_t i = 0; i < param->nb_entity; i++)
32 for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--)
33 if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read())
34 {
35 delete component_buffer_drsp [i]->read(j)._data;
36 component_buffer_drsp [i]->pop(j);
37 }
38
39 //=============================================================================
40 //===== [ ICACHE - RESPONS ]===================================================
41 //=============================================================================
42 for (uint32_t i=0; i<param->nb_entity; i++)
43 for (uint32_t j=0; j <param->icache_dedicated_nb_port [i]; j++)
44 if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j])
45 {
46 _cout(ENVIRONMENT, "ICACHE_REQ [%d][%d] : Transaction accepted\n",i,j);
47
48 Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
49 Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
50 Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read()<<2;
51 Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read();
52 uint32_t size = (param->iaccess_size_address [i]+2)/8;
53
54 _cout(ENVIRONMENT," * information\n");
55 _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
56 _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
57 _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
58 _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
59 _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
60
61 // search the entity
62 data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
63
64 bool uncached ;
65 bool bus_error;
66 bool must_read = (type == ICACHE_TYPE_LOAD);
67 bool must_ack = (type == ICACHE_TYPE_LOAD);
68 bool must_ack_on_error = (type == ICACHE_TYPE_LOAD);
69
70 // Test the type of the address : if != MEMORY -> error
71 if ((entity.present == true) and
72 (entity.segment->getType() == data::TYPE_TARGET_MEMORY))
73 {
74 _cout(ENVIRONMENT," * OK !\n");
75 bus_error = false;
76 uncached = entity.segment->getUncached();
77
78 if (must_read == true) // Test if must read the ram
79 {
80 _cout(ENVIRONMENT," * must read\n");
81 // Read all instruction
82 for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++)
83 {
84 uint32_t addr = address+k*(size);
85 _cout(ENVIRONMENT," * addr : %.8x - ",addr);
86
87 bus_error |= !component_data->read(addr,size,read_iram[k]);
88
89 // Swap if endienness is different
90 if (endianness::isSameEndianness(context) == false)
91 {
92 read_iram[k] = endianness::swapBytes(read_iram[k],size,size);
93 }
94
95 //_cout(ENVIRONMENT," * inst : ");
96 for (int32_t cpt=(param->iaccess_size_instruction[i]/8)-1; cpt>=0; --cpt)
97 __cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt]));
98 __cout(ENVIRONMENT, "\n");
99 }
100 }
101 }
102 else
103 {
104 _cout(ENVIRONMENT, " * KO !\n");
105 _cout(ENVIRONMENT, " * present : %d\n",entity.present);
106 if (entity.present)
107 _cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY);
108
109 // entity is not present, or is present but is not a memory : have a bus error
110 bus_error = true;
111 uncached = true;
112 }
113
114 Cache_Access cache_type = ireq_type2cache_type (type,uncached);
115 uint32_t latence = component_cache->latence(cache::INSTRUCTION_CACHE,
116 i,
117 j,
118 address,
119 context,
120 cache_type.type,
121 cache_type.direction);
122
123 _cout(ENVIRONMENT, " * latence : %d\n",latence);
124
125 // If is a respons -> compute the latence and push in the write_buffer
126 if (must_ack or (must_ack_on_error and bus_error))
127 {
128 _cout(ENVIRONMENT, " * must ack\n");
129
130 if (bus_error == true)
131 {
132 _cout(ENVIRONMENT," * Icache : have a bus error\n");
133 _cout(ENVIRONMENT," * entity : %d\n",i);
134 _cout(ENVIRONMENT," * port : %d\n",j);
135 _cout(ENVIRONMENT," * req_addr : %x\n",address);
136 _cout(ENVIRONMENT," * req_trdid : %d\n",context);
137 _cout(ENVIRONMENT," * req_pktid : %d\n",packet );
138
139 // Write in instruction [0] the bad address (only 32bit ....)
140 itoa<Ticache_address_t>(address,read_iram[0],param->iaccess_size_instruction[i]/8);
141 }
142
143 // Simplification : the size of a line is a multiple of size_iword (no test)
144 _cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i);
145
146 irsp_t * rsp = new irsp_t(j,
147 context,
148 packet,
149 param->iaccess_nb_instruction[i],
150 size,
151 read_iram,
152 (bus_error==true)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
153 component_buffer_irsp [i]->push(latence,rsp);
154 }
155
156 _cout(ENVIRONMENT, " * End request\n");
157 }
158
159 //=============================================================================
160 //===== [ DCACHE - REQUEST ]===================================================
161 //=============================================================================
162 for (uint32_t i=0; i<param->nb_entity; i++)
163 for (uint32_t j=0; j <param->dcache_dedicated_nb_port [i]; j++)
164 if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j])
165 {
166 _cout(ENVIRONMENT, "DCACHE_REQ [%d][%d] : Transaction accepted\n",i,j);
167
168 Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
169 Tdcache_packet_t packet = DCACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
170 Tdcache_address_t address = DCACHE_REQ_ADDRESS [i][j]->read();
171 Tdcache_data_t wdata = DCACHE_REQ_WDATA [i][j]->read();
172 Tdcache_type_t type = DCACHE_REQ_TYPE [i][j]->read();
173 uint32_t size = param->daccess_size_data [i]/8;
174
175 _cout(ENVIRONMENT," * information\n");
176 _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
177 _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
178 _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
179 _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
180 _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
181
182 bool uncached = false;
183 bool bus_error = false;
184
185 uint32_t nb_bytes = size;
186 bool must_read ;
187 bool must_write;
188 bool must_ack ;
189 bool must_ack_on_error;
190
191 switch (type)
192 {
193 case DCACHE_TYPE_LOAD_8 :{nb_bytes=1; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
194 case DCACHE_TYPE_LOAD_16 :{nb_bytes=2; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
195 case DCACHE_TYPE_LOAD_32 :{nb_bytes=4; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
196 case DCACHE_TYPE_LOAD_64 :{nb_bytes=8; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
197 case DCACHE_TYPE_LOCK :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
198 case DCACHE_TYPE_INVALIDATE :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
199 case DCACHE_TYPE_PREFETCH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
200 case DCACHE_TYPE_FLUSH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
201 case DCACHE_TYPE_SYNCHRONIZATION :{ must_read=false; must_write=false; must_ack=true ; must_ack_on_error=false; break;}
202 case DCACHE_TYPE_STORE_8 :{nb_bytes=1; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
203 case DCACHE_TYPE_STORE_16 :{nb_bytes=2; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
204 case DCACHE_TYPE_STORE_32 :{nb_bytes=4; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
205 case DCACHE_TYPE_STORE_64 :{nb_bytes=8; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
206 default :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
207 }
208
209 // search the entity
210 data::Entity entity = component_data->entity(static_cast<uint32_t>(address),nb_bytes);
211
212// std::cout << entity << std::endl;
213
214 // Test the type of the address
215 if (entity.present == true)
216 {
217 switch (entity.segment->getType())
218 {
219 //**************************************************************
220 //*****[ TTY ]**************************************************
221 //**************************************************************
222 case data::TYPE_TARGET_TTY :
223 {
224 // Can't read a tty, must write
225 if (must_write == false)
226 {
227 bus_error = true;
228 break;
229 }
230
231 uint32_t num_tty = (address - entity.segment->getBase())>>4;
232 uint32_t num_print = ((address>>2) & 0x3);
233 _cout(true," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print);
234
235 switch (num_print)
236 {
237 case 0 : // Write TTY
238 {
239 uint32_t num_component_tty = entity.segment->getIndex();
240 char char_write = static_cast<char>(wdata&0xff);
241 bus_error |= !component_tty [num_component_tty]->write(num_tty,char_write);
242 break;
243 }
244 case 1 : // STOP
245 {
246 _cout(true,"\n");
247 _cout(true,"***********************************************************************************************\n");
248 _cout(true,"***** [ STOP ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n"
249 ,static_cast<uint32_t>(sc_simulation_time())
250 ,static_cast<uint32_t>(address )
251 ,static_cast<uint32_t>((wdata>>24)&0xff)
252 ,static_cast<uint32_t>((wdata>>16)&0xff)
253 ,static_cast<uint32_t>((wdata>> 8)&0xff)
254 ,static_cast<uint32_t>((wdata>> 0)&0xff)
255 );
256 _cout(true,"***********************************************************************************************\n");
257 _cout(true,"\n");
258 _cout(true,"%s\n",(wdata == 0)?STR_OK:STR_KO);
259 _cout(true,"\n");
260
261 stop (context);
262
263 break;
264 }
265 case 2 : // PRINT
266 {
267 _cout(true,"\n");
268 _cout(true,"-----------------------------------------------------------------------------------------------\n");
269 _cout(true,"----- [ PRINT ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
270 ,static_cast<uint32_t>(sc_simulation_time())
271 ,static_cast<uint32_t>(address )
272 ,static_cast<uint32_t>((wdata>>24)&0xff)
273 ,static_cast<uint32_t>((wdata>>16)&0xff)
274 ,static_cast<uint32_t>((wdata>> 8)&0xff)
275 ,static_cast<uint32_t>((wdata>> 0)&0xff)
276 );
277 _cout(true,"-----------------------------------------------------------------------------------------------\n");
278 _cout(true,"\n");
279
280 break;
281 }
282 default :
283 {
284 _cout(true,"[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print);
285 bus_error = true;
286 }
287 }
288 break;
289 }
290
291 //**************************************************************
292 //*****[ MEMORY ]***********************************************
293 //**************************************************************
294 case data::TYPE_TARGET_MEMORY :
295 {
296 _cout(ENVIRONMENT," * TYPE_TARGET_MEMORY\n");
297 _cout(ENVIRONMENT," * access : %x\n",address);
298
299 if (must_read == true)
300 {
301 // Read
302 _cout(ENVIRONMENT," * Read (%d bytes)\n",size);
303 bus_error |= !component_data->read(address,nb_bytes,read_dram[0]); // always read a complete word
304
305 // Multiple copy
306 for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes)
307 memcpy(&(read_dram[0][it_size_data]),&(read_dram[0][0]),nb_bytes);
308
309 // Permutation if problem of endianness
310 if (endianness::isSameEndianness(context) == false)
311 read_dram[0] = endianness::swapBytes(read_dram[0] , size, nb_bytes);
312 }
313
314 if (must_write == true)
315 {
316 // Write
317 _cout(ENVIRONMENT," * Write (%d bytes)\n",size);
318 _cout(ENVIRONMENT," * Wdata : %x\n",wdata);
319 itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes);
320
321// for (unsigned int it_nb_bytes = 0; it_nb_bytes < size; it_nb_bytes ++)
322// write_dram [it_nb_bytes] = wdata.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes);
323 }
324
325 break;
326 }
327 //**************************************************************
328 //*****[ RAMLOCK ]**********************************************
329 //**************************************************************
330 case data::TYPE_TARGET_RAMLOCK :
331 {
332 _cout(ENVIRONMENT," * TYPE_TARGET_RAMLOCK\n");
333
334 // Access is on a byte, else error
335 if (nb_bytes != 1)
336 {
337 bus_error = true;
338 break;
339 }
340
341 uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access
342 uint32_t num_lock = num_ramlock % (param->daccess_size_data [i]/8);
343 uint32_t num_component_ramlock = entity.segment->getIndex();
344
345// _cout(ENVIRONMENT," * num_ramlock : %d\n",num_ramlock );
346// _cout(ENVIRONMENT," * num_lock : %d\n",num_lock );
347// _cout(ENVIRONMENT," * num_component_ramlock : %d\n",num_component_ramlock);
348 _cout(true," * num_ramlock : %d\n",num_ramlock );
349 _cout(true," * num_lock : %d\n",num_lock );
350 _cout(true," * num_component_ramlock : %d\n",num_component_ramlock);
351
352 // No test : because out of range
353
354// bus_error |= !component_ramlock [num_component_ramlock]->test(num_ramlock);
355
356// if (bus_error == true)
357// break;
358
359 memset (read_dram[0],0,size);
360
361 if (must_read == true)
362 read_dram [0][num_lock] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock));
363 if (must_write == true)
364 read_dram [0][num_lock] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock));
365
366 _cout(true," * lock : %d\n",(int)read_dram [0][num_lock]);
367// _cout(ENVIRONMENT," * lock : %d\n",(int)read_dram [0][num_lock]);
368
369 break;
370 }
371
372 //**************************************************************
373 //*****[ SIM2OS ]***********************************************
374 //**************************************************************
375 case data::TYPE_TARGET_SIM2OS :
376 {
377 _cout(ENVIRONMENT," * TYPE_TARGET_SIM2OS\n");
378
379 // Mapping :
380 // [0] number of service - Wonly - A write in this register lunch the execution of service
381 // [1] result - Ronly - Content the result of the service
382 // [2] error - Ronly - Content the code of errno
383 // [3+] argument - Wonly - it's all argument to execute the service
384
385 uint32_t num_reg = (address - entity.segment->getBase())>>2;
386
387 _cout(ENVIRONMENT," * num_reg : %d\n",num_reg);
388
389 switch (num_reg)
390 {
391 case 0 : // ---> number of service
392 {
393 if (must_write == false)
394 {
395 _cerr("<Environment::transition> SIM2OS[0] is not accessible in Read\n");
396 bus_error = true;
397 }
398 else
399 {
400 _cout(ENVIRONMENT," * service : %x\n",wdata);
401 component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata)));
402 }
403 break;
404 }
405 case 1 : // ---> result
406 {
407 if (must_read == false)
408 {
409 _cerr("<Environment::transition> SIM2OS[1] is not accessible in Write\n");
410 bus_error = true;
411 }
412 else
413 {
414 // Decomposition en groupe octect
415 Tdcache_data_t result = static_cast<Tdcache_data_t>(reinterpret_cast<uint64_t>(component_sim2os->result));
416 _cout(ENVIRONMENT," * result : %x\n",result);
417
418 itoa<Tdcache_data_t>(result,read_dram[0],size);
419 }
420 break;
421 }
422 case 2 : // ---> error
423 {
424 if (must_read == false)
425 {
426 _cerr("<Environment::transition> SIM2OS[2] is not accessible in Write\n");
427 bus_error = true;
428 }
429 else
430 {
431 // Decomposition en groupe octect
432 Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error;
433 _cout(ENVIRONMENT," * error : %x\n",error);
434
435 itoa<Tdcache_data_t>(error,read_dram[0],size);
436 }
437
438 break;
439 }
440 default : //---> argument
441 {
442 if (must_write == false)
443 {
444 _cerr("<Environment::transition> SIM2OS[%d] is not accessible in Read\n",num_reg);
445 bus_error = true;
446 }
447 else
448 {
449 _cout(ENVIRONMENT," * argument[%d] : %x\n",num_reg-1,wdata);
450 component_sim2os->parameter(num_reg-2,(void *)wdata);
451 }
452 break;
453 }
454 }
455
456 break;
457 }
458
459 default :
460 {
461 _cerr("<Environment::transition> Dcache_req : Unknow type\n");
462 exit(1);
463 break;
464 }
465 }
466 uncached |= entity.segment->getUncached();
467 }
468 else
469 {
470 // entity is not present, or is present but is not a memory : have a bus error
471 bus_error = true;
472 uncached = true;
473 }
474
475 if ((must_write == true) and (bus_error == false))
476 {
477 // Permutation if problem of endianness
478 if (endianness::isSameEndianness(context) == false)
479 write_dram = endianness::swapBytes(write_dram, size, nb_bytes);
480
481 bus_error |= !component_data->write(address, nb_bytes, write_dram); // take the good access
482 }
483
484 // Acces at the cache !!!
485 // Cache WRITE ALLOCATE (becauce compute latence always; )
486 Cache_Access cache_type = dreq_type2cache_type (type,uncached);
487 uint32_t latence = component_cache->latence(cache::DATA_CACHE,
488 i,
489 j,
490 address,
491 context,
492 cache_type.type,
493 cache_type.direction);
494
495 // If is a respons -> compute the latence and push in the write_buffer
496 if (must_ack or (must_ack_on_error and bus_error))
497 {
498 if (bus_error == true)
499 {
500 _cout(ENVIRONMENT," * Dcache : have a bus error\n");
501 _cout(ENVIRONMENT," * entity : %d\n",i);
502 _cout(ENVIRONMENT," * port : %d\n",j);
503 _cout(ENVIRONMENT," * req_addr : 0x%x\n",address);
504 _cout(ENVIRONMENT," * req_trdid : %d\n",context);
505 _cout(ENVIRONMENT," * req_pktid : %d\n",packet );
506
507 // Write in data [0] the bad address (32bit or 64bits )
508 itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8);
509 }
510
511 _cout(ENVIRONMENT," * Rdata : ");
512 for (uint32_t x=0; x<nb_bytes; x++)
513 __cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][x]));
514 _cout(ENVIRONMENT,".\n");
515
516 // Simplification : the size of a line is a multiple of size_iword (no test)
517 drsp_t * rsp = new drsp_t(j,
518 context,
519 packet,
520 1,
521 size,
522 read_dram,
523 (bus_error==true)?DCACHE_ERROR_BUS_ERROR:DCACHE_ERROR_NONE);
524 component_buffer_drsp [i]->push(latence,rsp);
525 }
526 }
527
528 //=============================================================================
529 //===== [ OTHERS ]=============================================================
530 //=============================================================================
531
532 // Transition for each component
533 component_cache -> transition();
534 for (uint32_t i=0; i<param->nb_entity; i++)
535 {
536 component_buffer_irsp [i]->transition();
537 component_buffer_drsp [i]->transition();
538 }
539 component_sim2os->transition();
540 }
541 }
542
543// // ******************
544// // ***** DCACHE *****
545// // ******************
546
547// for (uint32_t j = 0; j < nb_dport [i]; j ++)
548// {
549// // Test if transaction
550
551// if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false)
552// continue;
553
554// entity_t entity = component_data->entity((uint32_t)DCACHE [i][j].REQ_ADDR.read(), SIZE_DDATA/8);
555
556// bool uncached = DCACHE [i][j].REQ_UNC.read();
557// bool bus_error = false;
558
559// uint32_t addr = (uint32_t) DCACHE [i][j].REQ_ADDR.read();
560// sc_uint<SIZE_DDATA> wdata = DCACHE[i][j].REQ_WDATA .read();
561// sc_uint<3> type = DCACHE[i][j].REQ_TYPE .read();
562// uint32_t nb_bytes = access_nb_bytes(DCACHE[i][j].REQ_ACCESS.read());
563// // A lot of flag
564// bool must_read = ((type == DTYPE_READ ));
565// bool must_write = ((type == DTYPE_WRITE ) ||
566// (type == DTYPE_WRITE_ACK ) );
567// bool must_ack = ((type == DTYPE_READ ) ||
568// (type == DTYPE_WRITE_ACK ) );
569
570// // Test the type of the address
571// if (entity.present == true)
572// {
573// switch (entity.segment->getType())
574// {
575// // ACCESS AT A RAM
576// case data::TYPE_TARGET_MEMORY :
577// {
578// if (must_read == true)
579// {
580// // Read
581// bus_error |= !component_data->read(addr ,
582// SIZE_DDATA/8 , // always read a complete word
583// read_dram );
584
585// for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes)
586// memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes);
587
588// // Permutation if problem of endianness
589// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
590// read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes);
591// }
592
593// if (must_write == true)
594// {
595// // Write
596// for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
597// write_dram [it_nb_bytes] = wdata.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes);
598// }
599// break;
600// }
601// //ACCESS AT THE TTY
602// case TYPE_TTY :
603// {
604// if (must_write == false)
605// {
606// bus_error = true;
607// break;
608// }
609// uint32_t num_tty = (addr - entity.segment->getBase())>>4;
610// uint32_t num_print = ((addr>>2) & 0x3);
611
612// switch (num_print)
613// {
614// case 0 : // Write TTY
615// {
616// uint32_t num_component_tty = entity.segment->getIndex();
617// char char_write = (char)wdata.range( 7, 0);
618// bus_error |= !component_tty [num_component_tty]->write(num_tty,char_write);
619// break;
620// }
621// case 1 : // STOP
622// {
623// cout("\n\t***** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n"
624// ,(unsigned int)sc_simulation_time()
625// ,(unsigned int)addr
626// ,(unsigned int)wdata.range(31,24)
627// ,(unsigned int)wdata.range(23,16)
628// ,(unsigned int)wdata.range(15, 8)
629// ,(unsigned int)wdata.range( 7, 0)
630// );
631
632// uint32_t trdid = (uint32_t) DCACHE[i][j].REQ_TRDID.read();
633
634// if (context_stop [trdid] == false)
635// {
636// context_stop [trdid] = true;
637// nb_context_stop ++;
638
639// if (nb_context_stop >= nb_context)
640// sc_stop();
641// }
642
643// break;
644// }
645// case 2 : // PRINT
646// {
647// cout("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
648// ,(unsigned int)sc_simulation_time()
649// ,(unsigned int)addr
650// ,(unsigned int)wdata.range(31,24)
651// ,(unsigned int)wdata.range(23,16)
652// ,(unsigned int)wdata.range(15, 8)
653// ,(unsigned int)wdata.range( 7, 0)
654// );
655
656// break;
657// }
658// default :
659// {
660// cout("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);
661// exit(1);
662// }
663// }
664
665// break;
666// }
667// case TYPE_RAMLOCK :
668// {
669// // Access is on a byte, else error
670// if (nb_bytes != 1)
671// {
672// bus_error = true;
673// break;
674// }
675// uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access
676// uint32_t num_component_ramlock = entity.segment->getIndex();
677// bus_error |= !component_ramlock [num_component_ramlock]->test(num_ramlock);
678
679// if (bus_error == true)
680// break;
681
682// memset (read_dram,0,SIZE_DDATA/8);
683
684// if (must_read == true)
685// read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock);
686// if (must_write == true)
687// read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock);
688
689// /*
690// cout("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time());
691// cout(" * addr : %.8x\n" ,(uint32_t)addr);
692// cout(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read());
693// cout(" * r/w : %d/%d\n",must_read,must_write);
694// cout(" * val : %d\n" ,(uint32_t)read_dram[0]);
695// */
696// break;
697// }
698// case TYPE_SIM2OS :
699// {
700// // Mapping :
701// // [0] number of service - Wonly - A write in this register lunch the execution of service
702// // [1] result - Ronly - Content the result of the service
703// // [2] error - Ronly - Content the code of errno
704// // [3+] argument - Wonly - it's all argument to execute the service
705
706// uint32_t num_reg = (addr - entity.segment->getBase())>>2;
707
708// switch (num_reg)
709// {
710// case 0 : // ---> number of service
711// {
712// if (must_write == false)
713// {
714// cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl;
715// bus_error = true;
716// }
717// else
718// {
719// cout("<sim2os> service : %.8x\n",(uint32_t)wdata);
720// component_sim2os->execute(int2service((uint32_t)wdata));
721// }
722// break;
723// }
724// case 1 : // ---> result
725// {
726// if (must_read == false)
727// {
728// cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl;
729// bus_error = true;
730// }
731// else
732// {
733// // Decomposition en groupe octect
734// uint32_t result = (uint32_t) component_sim2os->result;
735// cout("<sim2os> result : %.8x (%d)\n",result,result);
736
737// read_dram = itoa(result,read_dram,SIZE_DDATA/8);
738// }
739// break;
740// }
741// case 2 : // ---> error
742// {
743// if (must_read == false)
744// {
745// cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl;
746// bus_error = true;
747// }
748// else
749// {
750// // Decomposition en groupe octect
751// uint32_t error = (uint32_t) component_sim2os->error;
752// cout("<sim2os> error : %.8x\n",error);
753// read_dram = itoa(error ,read_dram,SIZE_DDATA/8);
754// }
755// break;
756// }
757// default : // ---> argument
758// {
759// if (must_write == false)
760// {
761// cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl;
762// bus_error = true;
763// }
764// else
765// {
766// uint32_t data = (uint32_t)wdata;
767// cout("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);
768// component_sim2os->parameter(num_reg-2,(void *)data);
769// }
770// break;
771// }
772// }//end switch num_reg
773
774// break;
775// }
776// default :
777// {
778// // Have a bus error
779// bus_error = true;
780// break;
781// }
782// }// switch
783// uncached |= entity.segment->getUncached();
784// }
785// else
786// uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist
787
788
789// if ((must_write == true) && (bus_error == false))
790// {
791// // Permutation if problem of endianness
792// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
793// write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes);
794
795// bus_error |= !component_data->write(addr ,
796// nb_bytes, // take the good access
797// write_dram );
798// }
799
800
801// // Acces at the cache !!!
802// Cache_Access cache_type = dreq_type2cache_type (type, uncached);
803
804// uint32_t latence = component_cache->latence(DATA_CACHE ,
805// i ,
806// j ,
807// (uint32_t)DCACHE [i][j].REQ_ADDR .read() ,
808// (uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
809// cache_type.type ,
810// cache_type.direction );
811
812// // If is a respons -> compute the latence and push in the write_buffer
813// if ( must_ack == true)
814// {
815// if (bus_error == true)
816// cout("Dcache : have a bus error");
817// component_buffer_drsp [i]->push(latence,
818// Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
819// (uint32_t)DCACHE [i][j].REQ_PKTID.read() ,
820// 1 ,
821// SIZE_DDATA/8 ,
822// &read_dram ,
823// (bus_error==true)?ERR_BUS:ERR_NO )
824// );
825// }
826// }// dnb_port
827// }//i
828
829
830};
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