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source: trunk/IPs/systemC/Environment/src/Environment_transition.cpp @ 128

Last change on this file since 128 was 128, checked in by rosiere, 15 years ago
1) Correct bug in link two signal 2) Fix error detected with valgrind 3) modif distexe script
Property svn:keywords set to `Id`
File size: 32.5 KB

Line
1	#include "../include/Environment.h"
2
3	#define CYCLE_MAX 0
4	#include "../../processor/Morpheo/Common/include/Test.h"
5	#include "../../processor/Morpheo/Common/include/Systemc.h"
6
7	using namespace morpheo;
8
9	namespace environment {
10
11	void Environment::transition (void)
12	{
13	_cout(ENVIRONMENT, " [%d] <Environment::transition>\n",static_cast<uint32_t>(simulation_cycle()));
14
15	if (NRESET->read() == 0)
16	{
17	reset ();
18	}
19	else
20	{
21	//=============================================================================
22	//===== [ ICACHE - RESPONS ]===================================================
23	//=============================================================================
24	for (uint32_t i = 0; i < param->nb_entity; i++)
25	for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--)
26	{
27	_cout(ENVIRONMENT, " * ICACHE_RSP [%d][%d]\n",i,j);
28
29	if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read())
30	{
31	_cout(ENVIRONMENT, " * ICACHE_RSP [%d][%d] : Transaction accepted\n",i,j);
32
33	uint32_t num = icache_rsp_num [i][j];
34
35	delete component_buffer_irsp [i]->read(num)._data;
36	component_buffer_irsp [i]->pop(num);
37	}
38	}
39	//=============================================================================
40	//===== [ DCACHE - RESPONS ]===================================================
41	//=============================================================================
42	for (uint32_t i = 0; i < param->nb_entity; i++)
43	for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--)
44	{
45	_cout(ENVIRONMENT, " * DCACHE_RSP [%d][%d]\n",i,j);
46	if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read())
47	{
48	_cout(ENVIRONMENT, " * DCACHE_RSP [%d][%d] : Transaction accepted\n",i,j);
49
50	uint32_t num = dcache_rsp_num [i][j];
51
52	delete component_buffer_drsp [i]->read(num)._data;
53	component_buffer_drsp [i]->pop(num);
54	}
55	}
56
57	//=============================================================================
58	//===== [ ICACHE - RESPONS ]===================================================
59	//=============================================================================
60	for (uint32_t i=0; i<param->nb_entity; i++)
61	for (uint32_t j=0; j <param->icache_dedicated_nb_port [i]; j++)
62	if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j])
63	{
64	_cout(ENVIRONMENT, " * ICACHE_REQ [%d][%d] : Transaction accepted\n",i,j);
65
66	Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
67	Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
68	Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read()<<2;
69	Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read();
70	uint32_t size = (param->iaccess_size_address [i]+2)/8;
71
72	_cout(ENVIRONMENT," * information\n");
73	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
74	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
75	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
76	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
77	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
78
79	// search the entity
80	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
81
82	bool uncached ;
83	bool bus_error;
84	bool must_read = (type == ICACHE_TYPE_LOAD);
85	bool must_ack = (type == ICACHE_TYPE_LOAD);
86	bool must_ack_on_error = (type == ICACHE_TYPE_LOAD);
87
88	// Test the type of the address : if != MEMORY -> error
89	if ((entity.present == true) and
90	(entity.segment->getType() == data::TYPE_TARGET_MEMORY))
91	{
92	_cout(ENVIRONMENT," * OK !\n");
93	bus_error = false;
94	uncached = entity.segment->getUncached();
95
96	if (must_read == true) // Test if must read the ram
97	{
98	_cout(ENVIRONMENT," * must read\n");
99	// Read all instruction
100	for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++)
101	{
102	uint32_t addr = address+k*(size);
103	_cout(ENVIRONMENT," * addr : %.8x - ",addr);
104
105	bus_error \|= !component_data->read(addr,size,read_iram[k]);
106
107	// Swap if endienness is different
108	if (endianness::isSameEndianness(context) == false)
109	{
110	read_iram[k] = endianness::swapBytes(read_iram[k],size,size);
111	}
112
113	//_cout(ENVIRONMENT," * inst : ");
114	for (int32_t cpt=(param->iaccess_size_instruction[i]/8)-1; cpt>=0; --cpt)
115	__cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt]));
116	__cout(ENVIRONMENT, "\n");
117	}
118	}
119	}
120	else
121	{
122	_cout(ENVIRONMENT, " * KO !\n");
123	_cout(ENVIRONMENT, " * present : %d\n",entity.present);
124	if (entity.present)
125	_cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY);
126
127	// entity is not present, or is present but is not a memory : have a bus error
128	bus_error = true;
129	uncached = true;
130	}
131
132	Cache_Access cache_type = ireq_type2cache_type (type,uncached);
133	uint32_t latence = component_cache->latence(cache::INSTRUCTION_CACHE,
134	i,
135	j,
136	address,
137	context,
138	cache_type.type,
139	cache_type.direction);
140
141	_cout(ENVIRONMENT, " * latence : %d\n",latence);
142
143	// If is a respons -> compute the latence and push in the write_buffer
144	if (must_ack or (must_ack_on_error and bus_error))
145	{
146	_cout(ENVIRONMENT, " * must ack\n");
147
148	if (bus_error == true)
149	{
150	_cout(ENVIRONMENT," * Icache : have a bus error\n");
151	_cout(ENVIRONMENT," * entity : %d\n",i);
152	_cout(ENVIRONMENT," * port : %d\n",j);
153	_cout(ENVIRONMENT," * req_addr : %x\n",address);
154	_cout(ENVIRONMENT," * req_trdid : %d\n",context);
155	_cout(ENVIRONMENT," * req_pktid : %d\n",packet );
156
157	// Write in instruction [0] the bad address (only 32bit ....)
158	itoa<Ticache_address_t>(address,read_iram[0],param->iaccess_size_instruction[i]/8);
159	}
160
161	// Simplification : the size of a line is a multiple of size_iword (no test)
162	_cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i);
163
164	irsp_t * rsp = new irsp_t(j,
165	context,
166	packet,
167	param->iaccess_nb_instruction[i],
168	size,
169	read_iram,
170	(bus_error==true)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
171	component_buffer_irsp [i]->push(latence,rsp);
172	}
173
174	_cout(ENVIRONMENT, " * End request\n");
175	}
176
177	//=============================================================================
178	//===== [ DCACHE - REQUEST ]===================================================
179	//=============================================================================
180	for (uint32_t i=0; i<param->nb_entity; i++)
181	for (uint32_t j=0; j <param->dcache_dedicated_nb_port [i]; j++)
182	if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j])
183	{
184	_cout(ENVIRONMENT, " * DCACHE_REQ [%d][%d] : Transaction accepted\n",i,j);
185
186	Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
187	Tdcache_packet_t packet = DCACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
188	Tdcache_address_t address = DCACHE_REQ_ADDRESS [i][j]->read();
189	Tdcache_data_t wdata = DCACHE_REQ_WDATA [i][j]->read();
190	Tdcache_type_t type = DCACHE_REQ_TYPE [i][j]->read();
191	uint32_t size = param->daccess_size_data [i]/8;
192
193	_cout(ENVIRONMENT," * information\n");
194	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
195	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
196	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
197	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
198	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
199
200	bool uncached = false;
201	bool bus_error = false;
202
203	uint32_t nb_bytes = size;
204	bool must_read ;
205	bool must_write;
206	bool must_ack ;
207	bool must_ack_on_error;
208
209	switch (type)
210	{
211	case DCACHE_TYPE_LOAD_8 :{nb_bytes=1; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
212	case DCACHE_TYPE_LOAD_16 :{nb_bytes=2; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
213	case DCACHE_TYPE_LOAD_32 :{nb_bytes=4; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
214	case DCACHE_TYPE_LOAD_64 :{nb_bytes=8; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
215	case DCACHE_TYPE_LOCK :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
216	case DCACHE_TYPE_INVALIDATE :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
217	case DCACHE_TYPE_PREFETCH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
218	case DCACHE_TYPE_FLUSH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
219	case DCACHE_TYPE_SYNCHRONIZATION :{ must_read=false; must_write=false; must_ack=true ; must_ack_on_error=false; break;}
220	case DCACHE_TYPE_STORE_8 :{nb_bytes=1; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
221	case DCACHE_TYPE_STORE_16 :{nb_bytes=2; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
222	case DCACHE_TYPE_STORE_32 :{nb_bytes=4; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
223	case DCACHE_TYPE_STORE_64 :{nb_bytes=8; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
224	default :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
225	}
226
227	// search the entity
228	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),nb_bytes);
229
230	// std::cout << entity << std::endl;
231
232	// Test the type of the address
233	if (entity.present == true)
234	{
235	switch (entity.segment->getType())
236	{
237	//**************************************************************
238	//***[ TTY ]************************************************
239	//**************************************************************
240	case data::TYPE_TARGET_TTY :
241	{
242	// Can't read a tty, must write
243	if (must_write == false)
244	{
245	bus_error = true;
246	break;
247	}
248
249	uint32_t num_tty = (address - entity.segment->getBase())>>4;
250	uint32_t num_print = ((address>>2) & 0x3);
251	_cout(true," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print);
252
253	switch (num_print)
254	{
255	case 0 : // Write TTY
256	{
257	uint32_t num_component_tty = entity.segment->getIndex();
258	char char_write = static_cast<char>(wdata&0xff);
259	bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
260	break;
261	}
262	case 1 : // STOP
263	{
264	_cout(true,"\n");
265	_cout(true,"***********************************************************************************************\n");
266	_cout(true,"*** [ STOP ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
267	,static_cast<uint32_t>(sc_simulation_time())
268	,static_cast<uint32_t>(address )
269	,static_cast<uint32_t>((wdata>>24)&0xff)
270	,static_cast<uint32_t>((wdata>>16)&0xff)
271	,static_cast<uint32_t>((wdata>> 8)&0xff)
272	,static_cast<uint32_t>((wdata>> 0)&0xff)
273	);
274	_cout(true,"***********************************************************************************************\n");
275	_cout(true,"\n");
276	_cout(true,"%s\n",(wdata == 0)?STR_OK:STR_KO);
277	_cout(true,"\n");
278
279	stop (context);
280
281	break;
282	}
283	case 2 : // PRINT
284	{
285	_cout(true,"\n");
286	_cout(true,"-----------------------------------------------------------------------------------------------\n");
287	_cout(true,"----- [ PRINT ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
288	,static_cast<uint32_t>(sc_simulation_time())
289	,static_cast<uint32_t>(address )
290	,static_cast<uint32_t>((wdata>>24)&0xff)
291	,static_cast<uint32_t>((wdata>>16)&0xff)
292	,static_cast<uint32_t>((wdata>> 8)&0xff)
293	,static_cast<uint32_t>((wdata>> 0)&0xff)
294	);
295	_cout(true,"-----------------------------------------------------------------------------------------------\n");
296	_cout(true,"\n");
297
298	break;
299	}
300	default :
301	{
302	_cout(true,"[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print);
303	bus_error = true;
304	}
305	}
306	break;
307	}
308
309	//**************************************************************
310	//***[ MEMORY ]*********************************************
311	//**************************************************************
312	case data::TYPE_TARGET_MEMORY :
313	{
314	_cout(ENVIRONMENT," * TYPE_TARGET_MEMORY\n");
315	_cout(ENVIRONMENT," * access : %x\n",address);
316
317	if (must_read == true)
318	{
319	// Read
320	_cout(ENVIRONMENT," * Read (%d bytes)\n",size);
321	bus_error \|= !component_data->read(address,nb_bytes,read_dram[0]); // always read a complete word
322
323	// Multiple copy
324	for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes)
325	memcpy(&(read_dram[0][it_size_data]),&(read_dram[0][0]),nb_bytes);
326
327	// Permutation if problem of endianness
328	if (endianness::isSameEndianness(context) == false)
329	read_dram[0] = endianness::swapBytes(read_dram[0] , size, nb_bytes);
330	}
331
332	if (must_write == true)
333	{
334	// Write
335	_cout(ENVIRONMENT," * Write (%d bytes)\n",size);
336	_cout(ENVIRONMENT," * Wdata : %x\n",wdata);
337	itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes);
338
339	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < size; it_nb_bytes ++)
340	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
341	}
342
343	break;
344	}
345	//**************************************************************
346	//***[ RAMLOCK ]********************************************
347	//**************************************************************
348	case data::TYPE_TARGET_RAMLOCK :
349	{
350	_cout(ENVIRONMENT," * TYPE_TARGET_RAMLOCK\n");
351
352	// Access is on a byte, else error
353	if (nb_bytes != 1)
354	{
355	bus_error = true;
356	break;
357	}
358
359	uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access
360	uint32_t num_lock = num_ramlock % (param->daccess_size_data [i]/8);
361	uint32_t num_component_ramlock = entity.segment->getIndex();
362
363	_cout(ENVIRONMENT," * num_ramlock : %d\n",num_ramlock );
364	_cout(ENVIRONMENT," * num_lock : %d\n",num_lock );
365	_cout(ENVIRONMENT," * num_component_ramlock : %d\n",num_component_ramlock);
366	// _cout(true," * num_ramlock : %d\n",num_ramlock );
367	// _cout(true," * num_lock : %d\n",num_lock );
368	// _cout(true," * num_component_ramlock : %d\n",num_component_ramlock);
369
370	// No test : because out of range
371
372	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
373
374	// if (bus_error == true)
375	// break;
376
377	memset (read_dram[0],0,size);
378
379	if (must_read == true)
380	read_dram [0][num_lock] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock));
381	if (must_write == true)
382	read_dram [0][num_lock] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock));
383
384	// _cout(true," * lock : %d\n",(int)read_dram [0][num_lock]);
385	_cout(ENVIRONMENT," * lock : %d\n",(int)read_dram [0][num_lock]);
386
387	break;
388	}
389
390	//**************************************************************
391	//***[ SIM2OS ]*********************************************
392	//**************************************************************
393	case data::TYPE_TARGET_SIM2OS :
394	{
395	_cout(ENVIRONMENT," * TYPE_TARGET_SIM2OS\n");
396
397	// Mapping :
398	// [0] number of service - Wonly - A write in this register lunch the execution of service
399	// [1] result - Ronly - Content the result of the service
400	// [2] error - Ronly - Content the code of errno
401	// [3+] argument - Wonly - it's all argument to execute the service
402
403	uint32_t num_reg = (address - entity.segment->getBase())>>2;
404
405	_cout(ENVIRONMENT," * num_reg : %d\n",num_reg);
406
407	switch (num_reg)
408	{
409	case 0 : // ---> number of service
410	{
411	if (must_write == false)
412	{
413	_cerr("<Environment::transition> SIM2OS[0] is not accessible in Read\n");
414	bus_error = true;
415	}
416	else
417	{
418	_cout(ENVIRONMENT," * service : %x\n",wdata);
419	component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata)));
420	}
421	break;
422	}
423	case 1 : // ---> result
424	{
425	if (must_read == false)
426	{
427	_cerr("<Environment::transition> SIM2OS[1] is not accessible in Write\n");
428	bus_error = true;
429	}
430	else
431	{
432	// Decomposition en groupe octect
433	Tdcache_data_t result = static_cast<Tdcache_data_t>(reinterpret_cast<uint64_t>(component_sim2os->result));
434	_cout(ENVIRONMENT," * result : %x\n",result);
435
436	itoa<Tdcache_data_t>(result,read_dram[0],size);
437	}
438	break;
439	}
440	case 2 : // ---> error
441	{
442	if (must_read == false)
443	{
444	_cerr("<Environment::transition> SIM2OS[2] is not accessible in Write\n");
445	bus_error = true;
446	}
447	else
448	{
449	// Decomposition en groupe octect
450	Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error;
451	_cout(ENVIRONMENT," * error : %x\n",error);
452
453	itoa<Tdcache_data_t>(error,read_dram[0],size);
454	}
455
456	break;
457	}
458	default : //---> argument
459	{
460	if (must_write == false)
461	{
462	_cerr("<Environment::transition> SIM2OS[%d] is not accessible in Read\n",num_reg);
463	bus_error = true;
464	}
465	else
466	{
467	_cout(ENVIRONMENT," * argument[%d] : %x\n",num_reg-1,wdata);
468	component_sim2os->parameter(num_reg-2,(void *)wdata);
469	}
470	break;
471	}
472	}
473
474	break;
475	}
476
477	default :
478	{
479	_cerr("<Environment::transition> Dcache_req : Unknow type\n");
480	exit(1);
481	break;
482	}
483	}
484	uncached \|= entity.segment->getUncached();
485	}
486	else
487	{
488	// entity is not present, or is present but is not a memory : have a bus error
489	bus_error = true;
490	uncached = true;
491	}
492
493	if ((must_write == true) and (bus_error == false))
494	{
495	// Permutation if problem of endianness
496	if (endianness::isSameEndianness(context) == false)
497	write_dram = endianness::swapBytes(write_dram, size, nb_bytes);
498
499	bus_error \|= !component_data->write(address, nb_bytes, write_dram); // take the good access
500	}
501
502	// Acces at the cache !!!
503	// Cache WRITE ALLOCATE (becauce compute latence always; )
504	Cache_Access cache_type = dreq_type2cache_type (type,uncached);
505	uint32_t latence = component_cache->latence(cache::DATA_CACHE,
506	i,
507	j,
508	address,
509	context,
510	cache_type.type,
511	cache_type.direction);
512
513	// If is a respons -> compute the latence and push in the write_buffer
514	if (must_ack or (must_ack_on_error and bus_error))
515	{
516	if (bus_error == true)
517	{
518	_cout(ENVIRONMENT," * Dcache : have a bus error\n");
519	_cout(ENVIRONMENT," * entity : %d\n",i);
520	_cout(ENVIRONMENT," * port : %d\n",j);
521	_cout(ENVIRONMENT," * req_addr : 0x%x\n",address);
522	_cout(ENVIRONMENT," * req_trdid : %d\n",context);
523	_cout(ENVIRONMENT," * req_pktid : %d\n",packet );
524
525	// Write in data [0] the bad address (32bit or 64bits )
526	itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8);
527	}
528
529	_cout(ENVIRONMENT," * Rdata : ");
530	for (uint32_t x=0; x<nb_bytes; x++)
531	__cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][x]));
532	_cout(ENVIRONMENT,".\n");
533
534	// Simplification : the size of a line is a multiple of size_iword (no test)
535	drsp_t * rsp = new drsp_t(j,
536	context,
537	packet,
538	1,
539	size,
540	read_dram,
541	(bus_error==true)?DCACHE_ERROR_BUS_ERROR:DCACHE_ERROR_NONE);
542	component_buffer_drsp [i]->push(latence,rsp);
543	}
544	}
545
546	//=============================================================================
547	//===== [ OTHERS ]=============================================================
548	//=============================================================================
549
550	// Transition for each component
551	component_cache -> transition();
552	for (uint32_t i=0; i<param->nb_entity; i++)
553	{
554	component_buffer_irsp [i]->transition();
555	component_buffer_drsp [i]->transition();
556	}
557	component_sim2os->transition();
558	}
559	}
560
561	// // ******************
562	// // *** DCACHE ***
563	// // ******************
564
565	// for (uint32_t j = 0; j < nb_dport [i]; j ++)
566	// {
567	// // Test if transaction
568
569	// if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false)
570	// continue;
571
572	// entity_t entity = component_data->entity((uint32_t)DCACHE [i][j].REQ_ADDR.read(), SIZE_DDATA/8);
573
574	// bool uncached = DCACHE [i][j].REQ_UNC.read();
575	// bool bus_error = false;
576
577	// uint32_t addr = (uint32_t) DCACHE [i][j].REQ_ADDR.read();
578	// sc_uint<SIZE_DDATA> wdata = DCACHE[i][j].REQ_WDATA .read();
579	// sc_uint<3> type = DCACHE[i][j].REQ_TYPE .read();
580	// uint32_t nb_bytes = access_nb_bytes(DCACHE[i][j].REQ_ACCESS.read());
581	// // A lot of flag
582	// bool must_read = ((type == DTYPE_READ ));
583	// bool must_write = ((type == DTYPE_WRITE ) \|\|
584	// (type == DTYPE_WRITE_ACK ) );
585	// bool must_ack = ((type == DTYPE_READ ) \|\|
586	// (type == DTYPE_WRITE_ACK ) );
587
588	// // Test the type of the address
589	// if (entity.present == true)
590	// {
591	// switch (entity.segment->getType())
592	// {
593	// // ACCESS AT A RAM
594	// case data::TYPE_TARGET_MEMORY :
595	// {
596	// if (must_read == true)
597	// {
598	// // Read
599	// bus_error \|= !component_data->read(addr ,
600	// SIZE_DDATA/8 , // always read a complete word
601	// read_dram );
602
603	// for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes)
604	// memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes);
605
606	// // Permutation if problem of endianness
607	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
608	// read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes);
609	// }
610
611	// if (must_write == true)
612	// {
613	// // Write
614	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
615	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
616	// }
617	// break;
618	// }
619	// //ACCESS AT THE TTY
620	// case TYPE_TTY :
621	// {
622	// if (must_write == false)
623	// {
624	// bus_error = true;
625	// break;
626	// }
627	// uint32_t num_tty = (addr - entity.segment->getBase())>>4;
628	// uint32_t num_print = ((addr>>2) & 0x3);
629
630	// switch (num_print)
631	// {
632	// case 0 : // Write TTY
633	// {
634	// uint32_t num_component_tty = entity.segment->getIndex();
635	// char char_write = (char)wdata.range( 7, 0);
636	// bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
637	// break;
638	// }
639	// case 1 : // STOP
640	// {
641	// cout("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
642	// ,(unsigned int)sc_simulation_time()
643	// ,(unsigned int)addr
644	// ,(unsigned int)wdata.range(31,24)
645	// ,(unsigned int)wdata.range(23,16)
646	// ,(unsigned int)wdata.range(15, 8)
647	// ,(unsigned int)wdata.range( 7, 0)
648	// );
649
650	// uint32_t trdid = (uint32_t) DCACHE[i][j].REQ_TRDID.read();
651
652	// if (context_stop [trdid] == false)
653	// {
654	// context_stop [trdid] = true;
655	// nb_context_stop ++;
656
657	// if (nb_context_stop >= nb_context)
658	// sc_stop();
659	// }
660
661	// break;
662	// }
663	// case 2 : // PRINT
664	// {
665	// cout("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
666	// ,(unsigned int)sc_simulation_time()
667	// ,(unsigned int)addr
668	// ,(unsigned int)wdata.range(31,24)
669	// ,(unsigned int)wdata.range(23,16)
670	// ,(unsigned int)wdata.range(15, 8)
671	// ,(unsigned int)wdata.range( 7, 0)
672	// );
673
674	// break;
675	// }
676	// default :
677	// {
678	// cout("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);
679	// exit(1);
680	// }
681	// }
682
683	// break;
684	// }
685	// case TYPE_RAMLOCK :
686	// {
687	// // Access is on a byte, else error
688	// if (nb_bytes != 1)
689	// {
690	// bus_error = true;
691	// break;
692	// }
693	// uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access
694	// uint32_t num_component_ramlock = entity.segment->getIndex();
695	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
696
697	// if (bus_error == true)
698	// break;
699
700	// memset (read_dram,0,SIZE_DDATA/8);
701
702	// if (must_read == true)
703	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock);
704	// if (must_write == true)
705	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock);
706
707	// /*
708	// cout("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time());
709	// cout(" * addr : %.8x\n" ,(uint32_t)addr);
710	// cout(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read());
711	// cout(" * r/w : %d/%d\n",must_read,must_write);
712	// cout(" * val : %d\n" ,(uint32_t)read_dram[0]);
713	// */
714	// break;
715	// }
716	// case TYPE_SIM2OS :
717	// {
718	// // Mapping :
719	// // [0] number of service - Wonly - A write in this register lunch the execution of service
720	// // [1] result - Ronly - Content the result of the service
721	// // [2] error - Ronly - Content the code of errno
722	// // [3+] argument - Wonly - it's all argument to execute the service
723
724	// uint32_t num_reg = (addr - entity.segment->getBase())>>2;
725
726	// switch (num_reg)
727	// {
728	// case 0 : // ---> number of service
729	// {
730	// if (must_write == false)
731	// {
732	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl;
733	// bus_error = true;
734	// }
735	// else
736	// {
737	// cout("<sim2os> service : %.8x\n",(uint32_t)wdata);
738	// component_sim2os->execute(int2service((uint32_t)wdata));
739	// }
740	// break;
741	// }
742	// case 1 : // ---> result
743	// {
744	// if (must_read == false)
745	// {
746	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl;
747	// bus_error = true;
748	// }
749	// else
750	// {
751	// // Decomposition en groupe octect
752	// uint32_t result = (uint32_t) component_sim2os->result;
753	// cout("<sim2os> result : %.8x (%d)\n",result,result);
754
755	// read_dram = itoa(result,read_dram,SIZE_DDATA/8);
756	// }
757	// break;
758	// }
759	// case 2 : // ---> error
760	// {
761	// if (must_read == false)
762	// {
763	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl;
764	// bus_error = true;
765	// }
766	// else
767	// {
768	// // Decomposition en groupe octect
769	// uint32_t error = (uint32_t) component_sim2os->error;
770	// cout("<sim2os> error : %.8x\n",error);
771	// read_dram = itoa(error ,read_dram,SIZE_DDATA/8);
772	// }
773	// break;
774	// }
775	// default : // ---> argument
776	// {
777	// if (must_write == false)
778	// {
779	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl;
780	// bus_error = true;
781	// }
782	// else
783	// {
784	// uint32_t data = (uint32_t)wdata;
785	// cout("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);
786	// component_sim2os->parameter(num_reg-2,(void *)data);
787	// }
788	// break;
789	// }
790	// }//end switch num_reg
791
792	// break;
793	// }
794	// default :
795	// {
796	// // Have a bus error
797	// bus_error = true;
798	// break;
799	// }
800	// }// switch
801	// uncached \|= entity.segment->getUncached();
802	// }
803	// else
804	// uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist
805
806
807	// if ((must_write == true) && (bus_error == false))
808	// {
809	// // Permutation if problem of endianness
810	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
811	// write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes);
812
813	// bus_error \|= !component_data->write(addr ,
814	// nb_bytes, // take the good access
815	// write_dram );
816	// }
817
818
819	// // Acces at the cache !!!
820	// Cache_Access cache_type = dreq_type2cache_type (type, uncached);
821
822	// uint32_t latence = component_cache->latence(DATA_CACHE ,
823	// i ,
824	// j ,
825	// (uint32_t)DCACHE [i][j].REQ_ADDR .read() ,
826	// (uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
827	// cache_type.type ,
828	// cache_type.direction );
829
830	// // If is a respons -> compute the latence and push in the write_buffer
831	// if ( must_ack == true)
832	// {
833	// if (bus_error == true)
834	// cout("Dcache : have a bus error");
835	// component_buffer_drsp [i]->push(latence,
836	// Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
837	// (uint32_t)DCACHE [i][j].REQ_PKTID.read() ,
838	// 1 ,
839	// SIZE_DDATA/8 ,
840	// &read_dram ,
841	// (bus_error==true)?ERR_BUS:ERR_NO )
842	// );
843	// }
844	// }// dnb_port
845	// }//i
846
847
848	};

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