Context Navigation

test1.cpp @ 113

Last change on this file since 113 was 113, checked in by rosiere, 15 years ago
1) Add modelsim simulation systemC 2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit) 3) Add multi architecture 5) Add template for comparator, multiplier and divider 6) Change Message Warning) Various test macro have change, many selftest can't compile
Property svn:keywords set to `Id`
File size: 33.3 KB

Line
1	/*
2	* $Id: test1.cpp 113 2009-04-14 18:39:12Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	/*
10
11	#include <queue>
12	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
13
14
15	//===================================================================={test}
16	void test1 (string name,
17	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
18	{
19	cout << "<" << name << "> : Simulation SystemC" << endl;
20
21	#ifdef STATISTICS
22	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
23	#endif
24
25	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
26	#ifdef STATISTICS
27	_parameters_statistics,
28	#endif
29	_param);
30
31	#ifdef SYSTEMC
32
33	string rename = "";
34
35	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
36	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
37
38	sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str());
39	sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str());
40	sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str());
41	sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str());
42	sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str());
43	sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str());
44	sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str());
45	sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str());
46	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
47	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
48	sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());
49	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str());
50	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str());
51	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str());
52	sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());
53	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());
54	sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str());
55	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());
56	sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());
57
58	sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
59	sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
60	sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
61	sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str());
62	sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str());
63	sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
64	// sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str());
65	sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str());
66	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());
67	sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
68	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());
69	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());
70	sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
71	sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());
72	sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());
73	sc_signal<Tcontrol_t > * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal<Tcontrol_t >(rename.c_str());
74	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_ADDRESS = new sc_signal<Tgeneral_data_t >(rename.c_str());
75
76	sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
77	sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
78	sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
79	sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
80	sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str());
81	sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str());
82	sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
83
84	sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
85	sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
86	sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
87	sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
88	sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
89	sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str());
90
91	sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory];
92	sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory];
93	sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory];
94	sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory];
95
96	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
97	{
98	out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str());
99	out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str());
100	out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
101	out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str());
102	}
103
104	// Instanciation
105
106	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
107
108	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
109	((_Load_store_unit->in_NRESET)) ((in_NRESET));
110
111	((_Load_store_unit-> in_MEMORY_IN_VAL ))(( in_MEMORY_IN_VAL ));
112	((_Load_store_unit->out_MEMORY_IN_ACK ))((out_MEMORY_IN_ACK ));
113	if (_param->_have_port_context_id)
114	((_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(( in_MEMORY_IN_CONTEXT_ID ));
115	if (_param->_have_port_front_end_id)
116	((_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(( in_MEMORY_IN_FRONT_END_ID ));
117	if (_param->_have_port_ooo_engine_id)
118	((_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(( in_MEMORY_IN_OOO_ENGINE_ID ));
119	if (_param->_have_port_packet_id)
120	((_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(( in_MEMORY_IN_PACKET_ID ));
121	((_Load_store_unit-> in_MEMORY_IN_OPERATION ))(( in_MEMORY_IN_OPERATION ));
122	((_Load_store_unit-> in_MEMORY_IN_TYPE ))(( in_MEMORY_IN_TYPE ));
123	((_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
124	if (_param->_have_port_load_queue_ptr)
125	((_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
126	((_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(( in_MEMORY_IN_HAS_IMMEDIAT ));
127	((_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(( in_MEMORY_IN_IMMEDIAT ));
128	((_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(( in_MEMORY_IN_DATA_RA ));
129	((_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(( in_MEMORY_IN_DATA_RB ));
130	((_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(( in_MEMORY_IN_DATA_RC ));
131	((_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(( in_MEMORY_IN_WRITE_RD ));
132	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(( in_MEMORY_IN_NUM_REG_RD ));
133	((_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(( in_MEMORY_IN_WRITE_RE ));
134	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(( in_MEMORY_IN_NUM_REG_RE ));
135
136	((_Load_store_unit->out_MEMORY_OUT_VAL ))((out_MEMORY_OUT_VAL ));
137	((_Load_store_unit-> in_MEMORY_OUT_ACK ))(( in_MEMORY_OUT_ACK ));
138	if (_param->_have_port_context_id)
139	((_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))((out_MEMORY_OUT_CONTEXT_ID ));
140	if (_param->_have_port_front_end_id)
141	((_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))((out_MEMORY_OUT_FRONT_END_ID ));
142	if (_param->_have_port_ooo_engine_id)
143	((_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))((out_MEMORY_OUT_OOO_ENGINE_ID ));
144	if (_param->_have_port_packet_id)
145	((_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))((out_MEMORY_OUT_PACKET_ID ));
146	// ((_Load_store_unit->out_MEMORY_OUT_OPERATION ))((out_MEMORY_OUT_OPERATION ));
147	((_Load_store_unit->out_MEMORY_OUT_TYPE ))((out_MEMORY_OUT_TYPE ));
148	((_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))((out_MEMORY_OUT_WRITE_RD ));
149	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))((out_MEMORY_OUT_NUM_REG_RD ));
150	((_Load_store_unit->out_MEMORY_OUT_DATA_RD ))((out_MEMORY_OUT_DATA_RD ));
151	((_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))((out_MEMORY_OUT_WRITE_RE ));
152	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))((out_MEMORY_OUT_NUM_REG_RE ));
153	((_Load_store_unit->out_MEMORY_OUT_DATA_RE ))((out_MEMORY_OUT_DATA_RE ));
154	((_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))((out_MEMORY_OUT_EXCEPTION ));
155	((_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))((out_MEMORY_OUT_NO_SEQUENCE ));
156	((_Load_store_unit->out_MEMORY_OUT_ADDRESS ))((out_MEMORY_OUT_ADDRESS ));
157
158	((_Load_store_unit->out_DCACHE_REQ_VAL ))((out_DCACHE_REQ_VAL ));
159	((_Load_store_unit-> in_DCACHE_REQ_ACK ))(( in_DCACHE_REQ_ACK ));
160	if (_param->_have_port_dcache_context_id)
161	((_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))((out_DCACHE_REQ_CONTEXT_ID));
162	((_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))((out_DCACHE_REQ_PACKET_ID ));
163	((_Load_store_unit->out_DCACHE_REQ_ADDRESS ))((out_DCACHE_REQ_ADDRESS ));
164	((_Load_store_unit->out_DCACHE_REQ_TYPE ))((out_DCACHE_REQ_TYPE ));
165	((_Load_store_unit->out_DCACHE_REQ_WDATA ))((out_DCACHE_REQ_WDATA ));
166
167	((_Load_store_unit-> in_DCACHE_RSP_VAL ))(( in_DCACHE_RSP_VAL ));
168	((_Load_store_unit->out_DCACHE_RSP_ACK ))((out_DCACHE_RSP_ACK ));
169	if (_param->_have_port_dcache_context_id)
170	((_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(( in_DCACHE_RSP_CONTEXT_ID));
171	((_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(( in_DCACHE_RSP_PACKET_ID ));
172	((_Load_store_unit-> in_DCACHE_RSP_RDATA ))(( in_DCACHE_RSP_RDATA ));
173	((_Load_store_unit-> in_DCACHE_RSP_ERROR ))(( in_DCACHE_RSP_ERROR ));
174
175	{
176	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
177	{
178	((_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))((out_BYPASS_MEMORY_VAL [i]));
179	if (_param->_have_port_ooo_engine_id)
180	((_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))((out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
181	((_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))((out_BYPASS_MEMORY_NUM_REG [i]));
182	((_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))((out_BYPASS_MEMORY_DATA [i]));
183	}
184	}
185	cout << "<" << name << "> Start Simulation ............" << endl;
186	Time * _time = new Time();
187
188	// Simulation - Begin
189
190	// Initialisation
191
192	const uint32_t seed = 0;
193	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
194
195	srand(seed);
196
197	const uint32_t nb_request = _param->_nb_packet;
198	const uint32_t nb_word = nb_request;
199
200	//const int32_t percent_transaction_memory_in = 100;
201	const int32_t percent_transaction_memory_out = 75;
202	const int32_t percent_transaction_dcache = 75;
203
204	const int32_t percent_exception = 0;
205	const int32_t percent_type_load = 0;
206	const int32_t percent_type_store = 50;
207	const int32_t percent_miss_spec = 20;
208
209	const uint32_t miss_rate = 10;
210	const uint32_t miss_penality = 5;
211
212	if ((percent_type_load +
213	percent_type_store ) > 100)
214	TEST_KO("sum of percent_type > 100");
215
216	const int32_t seuil_type_load = percent_type_load;
217	const int32_t seuil_type_store = percent_type_store+percent_type_load;
218
219	uint32_t nb_request_memory_in ;
220	uint32_t nb_request_memory_out;
221	uint32_t nb_request_dcache ;
222
223	MemoryRequest_t tab_request [nb_request];
224	priority_queue<MemoryRequest_t> fifo_request;
225
226	// emulation of memory
227	Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, nb_word, _param->_size_general_data);
228	Cache_t * _cache = new Cache_t (miss_rate, miss_penality);
229
230
231	SC_START(0);
232
233	LABEL("Initialisation");
234
235	in_MEMORY_IN_VAL ->write(0);
236	in_MEMORY_OUT_ACK->write(0);
237	in_DCACHE_REQ_ACK->write(0);
238	in_DCACHE_RSP_VAL->write(0);
239
240	in_NRESET ->write(0);
241	SC_START(5);
242	in_NRESET ->write(5);
243
244	LABEL("Loop of Test");
245
246	try
247	{
248	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
249	{
250	LABEL("Iteration "+toString(iteration));
251
252	LABEL("Structure's initialisation");
253
254	nb_request_memory_in = 0;
255	nb_request_memory_out = 0;
256	nb_request_dcache = 0;
257
258	// Fill the request_queue
259
260	Tlsq_ptr_t store_queue_ptr_write = 0;
261	Tlsq_ptr_t load_queue_ptr_write = 0;
262
263	bool store_queue_use [_param->_size_store_queue];
264	uint32_t nb_store_slot_use = 0;
265	bool load_queue_use [_param->_size_load_queue ];
266
267	for (uint32_t i=0; i<_param->_size_store_queue; i++)
268	store_queue_use [i] = false;
269	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
270	load_queue_use [i] = false;
271
272	double current_cycle = simulation_cycle();
273	double cycle_min = current_cycle;
274
275	Toperation_t operation_store [4] = {OPERATION_MEMORY_STORE_8,
276	OPERATION_MEMORY_STORE_16,
277	OPERATION_MEMORY_STORE_32,
278	OPERATION_MEMORY_STORE_64};
279
280	Toperation_t operation_load [8] = {OPERATION_MEMORY_LOAD_8_Z,
281	OPERATION_MEMORY_LOAD_8_S,
282	OPERATION_MEMORY_LOAD_16_Z,
283	OPERATION_MEMORY_LOAD_16_S,
284	OPERATION_MEMORY_LOAD_32_Z,
285	OPERATION_MEMORY_LOAD_32_S,
286	OPERATION_MEMORY_LOAD_64_Z,
287	OPERATION_MEMORY_LOAD_64_S};
288
289	Toperation_t operation_other [5] = {OPERATION_MEMORY_LOCK ,
290	OPERATION_MEMORY_INVALIDATE ,
291	OPERATION_MEMORY_PREFETCH ,
292	OPERATION_MEMORY_FLUSH ,
293	OPERATION_MEMORY_SYNCHRONIZATION};
294
295
296	const uint32_t nb_operation_store = (log2(_param->_size_general_data/8)+1);
297	const uint32_t nb_operation_load = 2*(log2(_param->_size_general_data/8)+1);
298	const uint32_t nb_operation_other = 5;
299
300	LABEL("Fifo request initialisation");
301	// Init fifo_request
302	for (uint32_t i=0; i<nb_request; i++)
303	{
304	double cycle;
305	Tcontext_t context_id = 0;
306	Tcontext_t front_end_id = 0;
307	Tcontext_t ooo_engine_id = rand () % _param->_nb_ooo_engine;
308	Tpacket_t packet_id = i;
309	Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
310	Tlsq_ptr_t load_queue_ptr_write_old = load_queue_ptr_write ;
311	Toperation_t operation;
312
313	int32_t percent = rand()%100;
314
315	uint32_t size_queue;
316
317	if (percent < seuil_type_load)
318	{
319	LABEL(" * LOAD");
320	operation = operation_load[(rand()%nb_operation_load)];
321	size_queue = _param->_size_load_queue;
322	load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
323	}
324	else
325	{
326	if (percent < seuil_type_store)
327	{
328	LABEL(" * STORE");
329
330
331	operation = operation_store[(rand()%nb_operation_store)];
332	size_queue = _param->_size_store_queue;
333	store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
334	}
335	else
336	{
337	LABEL(" * OTHERS");
338	operation = operation_other[(rand()%nb_operation_other)];
339	// operation = operation_other[4];
340	size_queue = _param->_size_load_queue;
341	load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
342	}
343	}
344
345	cycle = cycle_min;
346	cycle_min ++;
347
348	Ttype_t type = TYPE_MEMORY;
349	Tgeneral_data_t address = rand()%(nb_word);
350	Tgeneral_data_t offset = rand()%(nb_word);
351
352	// LABEL ("Address step 1 : "+toString(address)+" - "+toString(offset));
353
354	percent = rand()%100;
355	if (percent > percent_exception)
356	address = address & (~ mask_memory_access(operation));
357
358	// LABEL ("Address step 2 : "+toString(address)+" - mask : "+toString((~ mask_memory_access(operation))));
359
360	if (offset > address) // max
361	offset = address;
362
363	Tgeneral_data_t immediat = offset;
364	Tgeneral_data_t data_ra = address - offset;
365
366	// LABEL ("Address step 3 : "+toString(address)+", "+toString(data_ra)+" - "+toString(immediat));
367
368	Tgeneral_data_t data_rb = static_cast<Tgeneral_data_t>(rand());
369	Tcontrol_t write_rd = 0;
370	Tgeneral_address_t num_reg_rd = 0;
371	bool write_spec_ko = is_operation_memory_store(operation) and ((rand()%100)<percent_miss_spec);
372
373	tab_request [i].modif(cycle ,
374	context_id ,
375	front_end_id ,
376	ooo_engine_id ,
377	packet_id ,
378	operation ,
379	type ,
380	store_queue_ptr_write_old,
381	load_queue_ptr_write_old ,
382	immediat ,
383	data_ra ,
384	data_rb ,
385	write_rd ,
386	num_reg_rd ,
387	write_spec_ko);
388
389	cout << tab_request [i] << endl;
390
391	fifo_request.push(tab_request [i]);
392
393	double cycle_head = 0;
394
395	if (is_operation_memory_store(operation))
396	{
397	cycle_head = cycle_min;
398	cycle_min ++;
399
400	cout << " * Write head : " << toString(cycle_head)
401	<< endl
402	<< endl;
403
404	fifo_request.push(MemoryRequest_t(cycle_head,
405	context_id,
406	front_end_id,
407	ooo_engine_id,
408	packet_id,
409	(write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
410	type,
411	store_queue_ptr_write_old,
412	0,
413	0,
414	0,
415	0,
416	0,
417	0,
418	write_spec_ko));
419	}
420	}
421
422	LABEL("Simulation of this iteration ...");
423
424	while (nb_request_memory_out < nb_request)
425	{
426	cout << "*********************************************" << endl;
427	cout << "Dump STORE_QUEUE_USE : " << endl;
428	cout << " use " << nb_store_slot_use << endl;
429	for (uint32_t i=0; i<_param->_size_store_queue; i++)
430	cout << " [" << i << "] " << store_queue_use [i] << endl;
431	cout << "Dump LOAD_QUEUE_USE : " << endl;
432	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
433	cout << " [" << i << "] " << load_queue_use [i] << endl;
434	cout << "*********************************************" << endl;
435
436
437	// *** MEMORY_IN ***
438
439	// memory_in_val depends of three factors :
440	// 1) request's fifo is not empty ?
441	// 2) the slot destination is free ?
442	// 3) The head of request's fifo can be issue : the number of cycle is more than current cycle
443
444	bool can_execute = false;
445
446	if (is_operation_memory_store(fifo_request.top()._operation))
447	can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
448	else
449	can_execute = not load_queue_use [fifo_request.top()._load_queue_ptr_write];
450
451	in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and
452	can_execute and
453	(simulation_cycle() >= fifo_request.top()._cycle));
454
455	if (_param->_have_port_context_id)
456	in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );
457	if (_param->_have_port_front_end_id)
458	in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id );
459	if (_param->_have_port_ooo_engine_id)
460	in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id );
461	if (_param->_have_port_packet_id)
462	in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );
463	in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );
464	in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );
465	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
466	if (_param->_have_port_load_queue_ptr)
467	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
468	in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );
469	in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );
470	in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );
471	// in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );
472	in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );
473
474	in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
475
476	// *** DCACHE_REQ ***
477	in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
478
479	// *** DCACHE_RSP ***
480	bool have_rsp = _cache->have_rsp ();
481	in_DCACHE_RSP_VAL->write(have_rsp);
482
483	if (have_rsp)
484	{
485	in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
486	in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
487	in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata );
488	in_DCACHE_RSP_ERROR ->write(_cache->front()._error );
489	}
490
491	SC_START(0);
492
493	LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
494	LABEL(" * fifo_request.empty : "+toString(fifo_request.empty()));
495	LABEL(" * fifo_request.top.cycle : "+toString(fifo_request.top()._cycle));
496	LABEL(" * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
497	LABEL(" * fifo_request.top.load_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
498	LABEL(" * fifo_request.top.operation : "+toString(static_cast<uint32_t>(fifo_request.top()._operation )));
499	LABEL(" * can_execute : "+toString(can_execute));
500
501	if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
502	{
503	LABEL(" * Accepted MEMORY_IN : " + toString(nb_request_memory_in));
504	cout << fifo_request.top();
505
506	if (is_operation_memory_store(fifo_request.top()._operation))
507	{
508	if (not is_operation_memory_store_head(fifo_request.top()._operation))
509	{
510	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
511	nb_store_slot_use ++;
512	}
513	}
514	else
515	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
516
517	fifo_request.pop();
518
519	nb_request_memory_in ++;
520	}
521
522	LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
523	if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())
524	{
525	Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read();
526
527	LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id));
528
529	if (is_operation_memory_store(tab_request[packet_id]._operation))
530	{
531	store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
532	nb_store_slot_use --;
533	}
534	else
535	load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false;
536
537	nb_request_memory_out ++;
538
539	// a lot of test
540	TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id );
541	TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
542	TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
543	TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id );
544	// TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation );
545	TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY );
546	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), tab_request[packet_id]._write_rd );
547	TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd );
548
549	Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
550	if (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))))
551	TEST(Texception_t , out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_ALIGNMENT);
552	else
553	{
554	if (tab_request[packet_id]._write_spec_ko)
555	TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_MISS_SPECULATION);
556	else
557	{
558	TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_NONE);
559
560	if (is_operation_memory_load(tab_request[packet_id]._operation))
561	{
562	Tgeneral_data_t read_lsq = _memory->read_lsq (((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) \|
563	(tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) \|
564	(tab_request[packet_id]._context_id)),
565	(tab_request[packet_id]._immediat +
566	tab_request[packet_id]._data_ra),
567	tab_request[packet_id]._operation);
568	cout << "MEMORY_OUT is a LOAD" << endl
569	<< " * operation : " << tab_request[packet_id]._operation << endl
570	<< std::hex
571	<< " * address : " << (tab_request[packet_id]._immediat +
572	tab_request[packet_id]._data_ra) << endl
573	<< " * read_lsq : " << read_lsq << endl
574	<< " * memory_out_data : " << out_MEMORY_OUT_DATA_RD->read() << endl
575	<< std::dec;
576
577	// TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), read_lsq);
578	}
579	}
580	}
581	}
582
583	LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
584	if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read())
585	{
586	Tcontext_t context_id;
587	Tpacket_t packet_id ;
588	if (_param->_have_port_dcache_context_id)
589	context_id = out_DCACHE_REQ_CONTEXT_ID->read();
590	else
591	context_id = 0;
592
593	packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
594
595	LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id));
596
597	// TEST(Tcontext_t ,out_DCACHE_REQ_CONTEXT_ID->read(),((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) \|
598	// (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) \|
599	// (tab_request[packet_id]._context_id)));
600	// TEST(Tdcache_address_t,out_DCACHE_REQ_ADDRESS ->read(),(tab_request[packet_id]._immediat +
601	// tab_request[packet_id]._data_ra) );
602	// TEST(Tdcache_type_t ,out_DCACHE_REQ_TYPE ->read(), operation_to_dcache_type(operation));
603
604	// if (is_operation_memory_store(operation))
605	// TEST(Tdcache_data_t ,out_DCACHE_REQ_WDATA ->read(),tab_request[packet_id]._data_rb);
606
607	Tdcache_data_t rdata = _memory->access (context_id, out_DCACHE_REQ_ADDRESS->read(), out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
608
609	// test type : send or not a respons !
610	LABEL(" * rdata : " + toString(rdata));
611
612	if ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_SYNCHRONIZATION) or
613	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_8 ) or
614	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_16) or
615	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_32) or
616	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_64))
617	{
618	LABEL(" * have_dcache_rsp");
619
620	_cache->push (context_id,
621	out_DCACHE_REQ_PACKET_ID ->read(),
622	rdata ,
623	0);
624	}
625	}
626
627	LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read()));
628	if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
629	{
630	_cache->pop();
631	}
632
633	_cache->end_cycle();
634
635	SC_START(1);
636	}
637	}
638	}
639	catch (morpheo::ErrorMorpheo & error)
640	{
641	_memory->trace();
642	throw (error);
643	}
644
645	_memory->trace();
646
647
648	// Simulation - End
649
650	TEST_OK ("End of Simulation");
651	delete _time;
652	cout << "<" << name << "> ............ Stop Simulation" << endl;
653
654	delete in_CLOCK;
655	delete in_NRESET;
656
657	delete in_MEMORY_IN_VAL ;
658	delete out_MEMORY_IN_ACK ;
659	delete in_MEMORY_IN_CONTEXT_ID ;
660	delete in_MEMORY_IN_FRONT_END_ID ;
661	delete in_MEMORY_IN_OOO_ENGINE_ID ;
662	delete in_MEMORY_IN_PACKET_ID ;
663	delete in_MEMORY_IN_OPERATION ;
664	delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
665	delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
666	delete in_MEMORY_IN_HAS_IMMEDIAT;
667	delete in_MEMORY_IN_IMMEDIAT ;
668	delete in_MEMORY_IN_DATA_RA ;
669	delete in_MEMORY_IN_DATA_RB ;
670	delete in_MEMORY_IN_DATA_RC ;
671	delete in_MEMORY_IN_WRITE_RD ;
672	delete in_MEMORY_IN_NUM_REG_RD ;
673	delete in_MEMORY_IN_WRITE_RE ;
674	delete in_MEMORY_IN_NUM_REG_RE ;
675
676	delete out_MEMORY_OUT_VAL ;
677	delete in_MEMORY_OUT_ACK ;
678	delete out_MEMORY_OUT_CONTEXT_ID;
679	delete out_MEMORY_OUT_FRONT_END_ID;
680	delete out_MEMORY_OUT_OOO_ENGINE_ID;
681	delete out_MEMORY_OUT_PACKET_ID ;
682	// delete out_MEMORY_OUT_OPERATION ;
683	delete out_MEMORY_OUT_TYPE ;
684	delete out_MEMORY_OUT_WRITE_RD ;
685	delete out_MEMORY_OUT_NUM_REG_RD;
686	delete out_MEMORY_OUT_DATA_RD ;
687	delete out_MEMORY_OUT_WRITE_RE ;
688	delete out_MEMORY_OUT_NUM_REG_RE;
689	delete out_MEMORY_OUT_DATA_RE ;
690	delete out_MEMORY_OUT_EXCEPTION ;
691	delete out_MEMORY_OUT_NO_SEQUENCE;
692	delete out_MEMORY_OUT_ADDRESS ;
693
694	delete out_DCACHE_REQ_VAL ;
695	delete in_DCACHE_REQ_ACK ;
696	delete out_DCACHE_REQ_CONTEXT_ID;
697	delete out_DCACHE_REQ_PACKET_ID ;
698	delete out_DCACHE_REQ_ADDRESS ;
699	delete out_DCACHE_REQ_TYPE ;
700	delete out_DCACHE_REQ_WDATA ;
701
702	delete in_DCACHE_RSP_VAL ;
703	delete out_DCACHE_RSP_ACK ;
704	delete in_DCACHE_RSP_CONTEXT_ID;
705	delete in_DCACHE_RSP_PACKET_ID ;
706	delete in_DCACHE_RSP_RDATA ;
707	delete in_DCACHE_RSP_ERROR ;
708
709	{
710	delete [] out_BYPASS_MEMORY_VAL ;
711	delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
712	delete [] out_BYPASS_MEMORY_NUM_REG ;
713	delete [] out_BYPASS_MEMORY_DATA ;
714	}
715	#endif
716
717	delete _Load_store_unit;
718	delete _memory;
719	delete _cache;
720	#ifdef STATISTICS
721	delete _parameters_statistics;
722	#endif
723	}
724	*/

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp @ 113

Download in other formats: