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test1.cpp @ 78

Last change on this file since 78 was 78, checked in by rosiere, 16 years ago

Add :

Execute_loop (must be test systemC)
Prediction
- Direction : predifined scheme
- Branch Target Buffer
iFetch_unit
- ifetch_queue
- pc management
Decod_unit
- coming soon : support for custom operation
Rename_unit
- RAT
- Free_list
- Dependence RAW check
- Load store unit pointer
New Environnement (hierarchy_memory will remove in a next version)

Modif :

Manage Custom Operation
All component in execute_loop to use the new statistics management

Not Finish :

Return Address Stack
Environnement

File size: 34.4 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include <queue>
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
11
12	#define NB_ITERATION 1
13	#define CYCLE_MAX (1024*NB_ITERATION)
14
15	#define LABEL(str) \
16	{ \
17	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
18	} while(0)
19
20	#define SC_START(cycle_offset) \
21	do \
22	{ \
23	/cout << "SC_START (begin)" << endl;/ \
24	\
25	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
26	if (cycle_offset != 0) \
27	{ \
28	cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
29	} \
30	\
31	if (cycle_current > CYCLE_MAX) \
32	{ \
33	TEST_KO("Maximal cycles Reached"); \
34	} \
35	sc_start(cycle_offset); \
36	/cout << "SC_START (end )" << endl;/ \
37	} while(0)
38
39
40	//===================================================================={test}
41	void test1 (string name,
42	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
43	{
44	cout << "<" << name << "> : Simulation SystemC" << endl;
45
46	#ifdef STATISTICS
47	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
48	#endif
49
50	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
51	#ifdef STATISTICS
52	_parameters_statistics,
53	#endif
54	_param);
55
56	#ifdef SYSTEMC
57	/*********************************************************************
58	* Déclarations des signaux
59	*********************************************************************/
60	string rename = "";
61
62	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
63	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
64
65	sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str());
66	sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str());
67	sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str());
68	sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str());
69	sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str());
70	sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str());
71	sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str());
72	sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str());
73	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
74	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
75	sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());
76	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str());
77	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str());
78	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str());
79	sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());
80	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());
81	sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str());
82	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());
83	sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());
84
85	sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
86	sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
87	sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
88	sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str());
89	sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str());
90	sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
91	// sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str());
92	sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str());
93	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());
94	sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
95	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());
96	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());
97	sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
98	sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());
99	sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());
100	sc_signal<Tcontrol_t > * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal<Tcontrol_t >(rename.c_str());
101	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_ADDRESS = new sc_signal<Tgeneral_data_t >(rename.c_str());
102
103	sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
104	sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
105	sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
106	sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
107	sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str());
108	sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str());
109	sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
110
111	sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
112	sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
113	sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
114	sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
115	sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
116	sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str());
117
118	sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory];
119	sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory];
120	sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory];
121	sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory];
122
123	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
124	{
125	out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str());
126	out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str());
127	out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
128	out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str());
129	}
130
131	/********************************************************
132	* Instanciation
133	********************************************************/
134
135	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
136
137	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
138	((_Load_store_unit->in_NRESET)) ((in_NRESET));
139
140	((_Load_store_unit-> in_MEMORY_IN_VAL ))(( in_MEMORY_IN_VAL ));
141	((_Load_store_unit->out_MEMORY_IN_ACK ))((out_MEMORY_IN_ACK ));
142	if (_param->_have_port_context_id)
143	((_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(( in_MEMORY_IN_CONTEXT_ID ));
144	if (_param->_have_port_front_end_id)
145	((_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(( in_MEMORY_IN_FRONT_END_ID ));
146	if (_param->_have_port_ooo_engine_id)
147	((_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(( in_MEMORY_IN_OOO_ENGINE_ID ));
148	if (_param->_have_port_packet_id)
149	((_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(( in_MEMORY_IN_PACKET_ID ));
150	((_Load_store_unit-> in_MEMORY_IN_OPERATION ))(( in_MEMORY_IN_OPERATION ));
151	((_Load_store_unit-> in_MEMORY_IN_TYPE ))(( in_MEMORY_IN_TYPE ));
152	((_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
153	if (_param->_have_port_load_queue_ptr)
154	((_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
155	((_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(( in_MEMORY_IN_HAS_IMMEDIAT ));
156	((_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(( in_MEMORY_IN_IMMEDIAT ));
157	((_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(( in_MEMORY_IN_DATA_RA ));
158	((_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(( in_MEMORY_IN_DATA_RB ));
159	((_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(( in_MEMORY_IN_DATA_RC ));
160	((_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(( in_MEMORY_IN_WRITE_RD ));
161	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(( in_MEMORY_IN_NUM_REG_RD ));
162	((_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(( in_MEMORY_IN_WRITE_RE ));
163	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(( in_MEMORY_IN_NUM_REG_RE ));
164
165	((_Load_store_unit->out_MEMORY_OUT_VAL ))((out_MEMORY_OUT_VAL ));
166	((_Load_store_unit-> in_MEMORY_OUT_ACK ))(( in_MEMORY_OUT_ACK ));
167	if (_param->_have_port_context_id)
168	((_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))((out_MEMORY_OUT_CONTEXT_ID ));
169	if (_param->_have_port_front_end_id)
170	((_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))((out_MEMORY_OUT_FRONT_END_ID ));
171	if (_param->_have_port_ooo_engine_id)
172	((_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))((out_MEMORY_OUT_OOO_ENGINE_ID ));
173	if (_param->_have_port_packet_id)
174	((_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))((out_MEMORY_OUT_PACKET_ID ));
175	// ((_Load_store_unit->out_MEMORY_OUT_OPERATION ))((out_MEMORY_OUT_OPERATION ));
176	((_Load_store_unit->out_MEMORY_OUT_TYPE ))((out_MEMORY_OUT_TYPE ));
177	((_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))((out_MEMORY_OUT_WRITE_RD ));
178	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))((out_MEMORY_OUT_NUM_REG_RD ));
179	((_Load_store_unit->out_MEMORY_OUT_DATA_RD ))((out_MEMORY_OUT_DATA_RD ));
180	((_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))((out_MEMORY_OUT_WRITE_RE ));
181	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))((out_MEMORY_OUT_NUM_REG_RE ));
182	((_Load_store_unit->out_MEMORY_OUT_DATA_RE ))((out_MEMORY_OUT_DATA_RE ));
183	((_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))((out_MEMORY_OUT_EXCEPTION ));
184	((_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))((out_MEMORY_OUT_NO_SEQUENCE ));
185	((_Load_store_unit->out_MEMORY_OUT_ADDRESS ))((out_MEMORY_OUT_ADDRESS ));
186
187	((_Load_store_unit->out_DCACHE_REQ_VAL ))((out_DCACHE_REQ_VAL ));
188	((_Load_store_unit-> in_DCACHE_REQ_ACK ))(( in_DCACHE_REQ_ACK ));
189	if (_param->_have_port_dcache_context_id)
190	((_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))((out_DCACHE_REQ_CONTEXT_ID));
191	((_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))((out_DCACHE_REQ_PACKET_ID ));
192	((_Load_store_unit->out_DCACHE_REQ_ADDRESS ))((out_DCACHE_REQ_ADDRESS ));
193	((_Load_store_unit->out_DCACHE_REQ_TYPE ))((out_DCACHE_REQ_TYPE ));
194	((_Load_store_unit->out_DCACHE_REQ_WDATA ))((out_DCACHE_REQ_WDATA ));
195
196	((_Load_store_unit-> in_DCACHE_RSP_VAL ))(( in_DCACHE_RSP_VAL ));
197	((_Load_store_unit->out_DCACHE_RSP_ACK ))((out_DCACHE_RSP_ACK ));
198	if (_param->_have_port_dcache_context_id)
199	((_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(( in_DCACHE_RSP_CONTEXT_ID));
200	((_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(( in_DCACHE_RSP_PACKET_ID ));
201	((_Load_store_unit-> in_DCACHE_RSP_RDATA ))(( in_DCACHE_RSP_RDATA ));
202	((_Load_store_unit-> in_DCACHE_RSP_ERROR ))(( in_DCACHE_RSP_ERROR ));
203
204	{
205	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
206	{
207	((_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))((out_BYPASS_MEMORY_VAL [i]));
208	if (_param->_have_port_ooo_engine_id)
209	((_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))((out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
210	((_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))((out_BYPASS_MEMORY_NUM_REG [i]));
211	((_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))((out_BYPASS_MEMORY_DATA [i]));
212	}
213	}
214	cout << "<" << name << "> Start Simulation ............" << endl;
215	Time * _time = new Time();
216
217	/********************************************************
218	* Simulation - Begin
219	********************************************************/
220
221	// Initialisation
222
223	const uint32_t seed = 0;
224	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
225
226	srand(seed);
227
228	const uint32_t nb_request = _param->_nb_packet;
229	const uint32_t nb_word = nb_request;
230
231	//const int32_t percent_transaction_memory_in = 100;
232	const int32_t percent_transaction_memory_out = 75;
233	const int32_t percent_transaction_dcache = 75;
234
235	const int32_t percent_exception = 0;
236	const int32_t percent_type_load = 0;
237	const int32_t percent_type_store = 50;
238	const int32_t percent_miss_spec = 20;
239
240	const uint32_t miss_rate = 10;
241	const uint32_t miss_penality = 5;
242
243	if ((percent_type_load +
244	percent_type_store ) > 100)
245	TEST_KO("sum of percent_type > 100");
246
247	const int32_t seuil_type_load = percent_type_load;
248	const int32_t seuil_type_store = percent_type_store+percent_type_load;
249
250	uint32_t nb_request_memory_in ;
251	uint32_t nb_request_memory_out;
252	uint32_t nb_request_dcache ;
253
254	MemoryRequest_t tab_request [nb_request];
255	priority_queue<MemoryRequest_t> fifo_request;
256
257	// emulation of memory
258	Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, nb_word, _param->_size_general_data);
259	Cache_t * _cache = new Cache_t (miss_rate, miss_penality);
260
261
262	SC_START(0);
263
264	LABEL("Initialisation");
265
266	in_MEMORY_IN_VAL ->write(0);
267	in_MEMORY_OUT_ACK->write(0);
268	in_DCACHE_REQ_ACK->write(0);
269	in_DCACHE_RSP_VAL->write(0);
270
271	in_NRESET ->write(0);
272	SC_START(5);
273	in_NRESET ->write(5);
274
275	LABEL("Loop of Test");
276
277	try
278	{
279	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
280	{
281	LABEL("Iteration "+toString(iteration));
282
283	LABEL("Structure's initialisation");
284
285	nb_request_memory_in = 0;
286	nb_request_memory_out = 0;
287	nb_request_dcache = 0;
288
289	// Fill the request_queue
290
291	Tlsq_ptr_t store_queue_ptr_write = 0;
292	Tlsq_ptr_t load_queue_ptr_write = 0;
293
294	bool store_queue_use [_param->_size_store_queue];
295	uint32_t nb_store_slot_use = 0;
296	bool load_queue_use [_param->_size_load_queue ];
297
298	for (uint32_t i=0; i<_param->_size_store_queue; i++)
299	store_queue_use [i] = false;
300	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
301	load_queue_use [i] = false;
302
303	double current_cycle = sc_simulation_time();
304	double cycle_min = current_cycle;
305
306	Toperation_t operation_store [4] = {OPERATION_MEMORY_STORE_8,
307	OPERATION_MEMORY_STORE_16,
308	OPERATION_MEMORY_STORE_32,
309	OPERATION_MEMORY_STORE_64};
310
311	Toperation_t operation_load [8] = {OPERATION_MEMORY_LOAD_8_Z,
312	OPERATION_MEMORY_LOAD_8_S,
313	OPERATION_MEMORY_LOAD_16_Z,
314	OPERATION_MEMORY_LOAD_16_S,
315	OPERATION_MEMORY_LOAD_32_Z,
316	OPERATION_MEMORY_LOAD_32_S,
317	OPERATION_MEMORY_LOAD_64_Z,
318	OPERATION_MEMORY_LOAD_64_S};
319
320	Toperation_t operation_other [5] = {OPERATION_MEMORY_LOCK ,
321	OPERATION_MEMORY_INVALIDATE ,
322	OPERATION_MEMORY_PREFETCH ,
323	OPERATION_MEMORY_FLUSH ,
324	OPERATION_MEMORY_SYNCHRONIZATION};
325
326
327	const uint32_t nb_operation_store = (log2(_param->_size_general_data/8)+1);
328	const uint32_t nb_operation_load = 2*(log2(_param->_size_general_data/8)+1);
329	const uint32_t nb_operation_other = 5;
330
331	LABEL("Fifo request initialisation");
332	// Init fifo_request
333	for (uint32_t i=0; i<nb_request; i++)
334	{
335	double cycle;
336	Tcontext_t context_id = 0;
337	Tcontext_t front_end_id = 0;
338	Tcontext_t ooo_engine_id = rand () % _param->_nb_ooo_engine;
339	Tpacket_t packet_id = i;
340	Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
341	Tlsq_ptr_t load_queue_ptr_write_old = load_queue_ptr_write ;
342	Toperation_t operation;
343
344	int32_t percent = rand()%100;
345
346	uint32_t size_queue;
347
348	if (percent < seuil_type_load)
349	{
350	LABEL(" * LOAD");
351	operation = operation_load[(rand()%nb_operation_load)];
352	size_queue = _param->_size_load_queue;
353	load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
354	}
355	else
356	{
357	if (percent < seuil_type_store)
358	{
359	LABEL(" * STORE");
360
361
362	operation = operation_store[(rand()%nb_operation_store)];
363	size_queue = _param->_size_store_queue;
364	store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
365	}
366	else
367	{
368	LABEL(" * OTHERS");
369	operation = operation_other[(rand()%nb_operation_other)];
370	// operation = operation_other[4];
371	size_queue = _param->_size_load_queue;
372	load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
373	}
374	}
375
376	cycle = cycle_min;
377	cycle_min ++;
378
379	Ttype_t type = TYPE_MEMORY;
380	Tgeneral_data_t address = rand()%(nb_word);
381	Tgeneral_data_t offset = rand()%(nb_word);
382
383	// LABEL ("Address step 1 : "+toString(address)+" - "+toString(offset));
384
385	percent = rand()%100;
386	if (percent > percent_exception)
387	address = address & (~ mask_memory_access(operation));
388
389	// LABEL ("Address step 2 : "+toString(address)+" - mask : "+toString((~ mask_memory_access(operation))));
390
391	if (offset > address) // max
392	offset = address;
393
394	Tgeneral_data_t immediat = offset;
395	Tgeneral_data_t data_ra = address - offset;
396
397	// LABEL ("Address step 3 : "+toString(address)+", "+toString(data_ra)+" - "+toString(immediat));
398
399	Tgeneral_data_t data_rb = static_cast<Tgeneral_data_t>(rand());
400	Tcontrol_t write_rd = 0;
401	Tgeneral_address_t num_reg_rd = 0;
402	bool write_spec_ko = is_operation_memory_store(operation) and ((rand()%100)<percent_miss_spec);
403
404	tab_request [i].modif(cycle ,
405	context_id ,
406	front_end_id ,
407	ooo_engine_id ,
408	packet_id ,
409	operation ,
410	type ,
411	store_queue_ptr_write_old,
412	load_queue_ptr_write_old ,
413	immediat ,
414	data_ra ,
415	data_rb ,
416	write_rd ,
417	num_reg_rd ,
418	write_spec_ko);
419
420	cout << tab_request [i] << endl;
421
422	fifo_request.push(tab_request [i]);
423
424	double cycle_head = 0;
425
426	if (is_operation_memory_store(operation))
427	{
428	cycle_head = cycle_min;
429	cycle_min ++;
430
431	cout << " * Write head : " << toString(cycle_head)
432	<< endl
433	<< endl;
434
435	fifo_request.push(MemoryRequest_t(cycle_head,
436	context_id,
437	front_end_id,
438	ooo_engine_id,
439	packet_id,
440	(write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
441	type,
442	store_queue_ptr_write_old,
443	0,
444	0,
445	0,
446	0,
447	0,
448	0,
449	write_spec_ko));
450	}
451	}
452
453	LABEL("Simulation of this iteration ...");
454
455	while (nb_request_memory_out < nb_request)
456	{
457	cout << "*********************************************" << endl;
458	cout << "Dump STORE_QUEUE_USE : " << endl;
459	cout << " use " << nb_store_slot_use << endl;
460	for (uint32_t i=0; i<_param->_size_store_queue; i++)
461	cout << " [" << i << "] " << store_queue_use [i] << endl;
462	cout << "Dump LOAD_QUEUE_USE : " << endl;
463	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
464	cout << " [" << i << "] " << load_queue_use [i] << endl;
465	cout << "*********************************************" << endl;
466
467
468	// *** MEMORY_IN ***
469
470	// memory_in_val depends of three factors :
471	// 1) request's fifo is not empty ?
472	// 2) the slot destination is free ?
473	// 3) The head of request's fifo can be issue : the number of cycle is more than current cycle
474
475	bool can_execute = false;
476
477	if (is_operation_memory_store(fifo_request.top()._operation))
478	can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
479	else
480	can_execute = not load_queue_use [fifo_request.top()._load_queue_ptr_write];
481
482	in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and
483	can_execute and
484	(sc_simulation_time() >= fifo_request.top()._cycle));
485
486	if (_param->_have_port_context_id)
487	in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );
488	if (_param->_have_port_front_end_id)
489	in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id );
490	if (_param->_have_port_ooo_engine_id)
491	in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id );
492	if (_param->_have_port_packet_id)
493	in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );
494	in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );
495	in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );
496	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
497	if (_param->_have_port_load_queue_ptr)
498	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
499	in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );
500	in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );
501	in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );
502	// in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );
503	in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );
504
505	in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
506
507	// *** DCACHE_REQ ***
508	in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
509
510	// *** DCACHE_RSP ***
511	bool have_rsp = _cache->have_rsp ();
512	in_DCACHE_RSP_VAL->write(have_rsp);
513
514	if (have_rsp)
515	{
516	in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
517	in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
518	in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata );
519	in_DCACHE_RSP_ERROR ->write(_cache->front()._error );
520	}
521
522	SC_START(0);
523
524	LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
525	LABEL(" * fifo_request.empty : "+toString(fifo_request.empty()));
526	LABEL(" * fifo_request.top.cycle : "+toString(fifo_request.top()._cycle));
527	LABEL(" * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
528	LABEL(" * fifo_request.top.load_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
529	LABEL(" * fifo_request.top.operation : "+toString(static_cast<uint32_t>(fifo_request.top()._operation )));
530	LABEL(" * can_execute : "+toString(can_execute));
531
532	if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
533	{
534	LABEL(" * Accepted MEMORY_IN : " + toString(nb_request_memory_in));
535	cout << fifo_request.top();
536
537	if (is_operation_memory_store(fifo_request.top()._operation))
538	{
539	if (not is_operation_memory_store_head(fifo_request.top()._operation))
540	{
541	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
542	nb_store_slot_use ++;
543	}
544	}
545	else
546	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
547
548	fifo_request.pop();
549
550	nb_request_memory_in ++;
551	}
552
553	LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
554	if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())
555	{
556	Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read();
557
558	LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id));
559
560	if (is_operation_memory_store(tab_request[packet_id]._operation))
561	{
562	store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
563	nb_store_slot_use --;
564	}
565	else
566	load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false;
567
568	nb_request_memory_out ++;
569
570	// a lot of test
571	TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id );
572	TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
573	TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
574	TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id );
575	// TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation );
576	TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY );
577	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), tab_request[packet_id]._write_rd );
578	TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd );
579
580	Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
581	if (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))))
582	TEST(Texception_t , out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_ALIGNMENT);
583	else
584	{
585	if (tab_request[packet_id]._write_spec_ko)
586	TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_MISS_SPECULATION);
587	else
588	{
589	TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_NONE);
590
591	if (is_operation_memory_load(tab_request[packet_id]._operation))
592	{
593	Tgeneral_data_t read_lsq = _memory->read_lsq (((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) \|
594	(tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) \|
595	(tab_request[packet_id]._context_id)),
596	(tab_request[packet_id]._immediat +
597	tab_request[packet_id]._data_ra),
598	tab_request[packet_id]._operation);
599	cout << "MEMORY_OUT is a LOAD" << endl
600	<< " * operation : " << tab_request[packet_id]._operation << endl
601	<< std::hex
602	<< " * address : " << (tab_request[packet_id]._immediat +
603	tab_request[packet_id]._data_ra) << endl
604	<< " * read_lsq : " << read_lsq << endl
605	<< " * memory_out_data : " << out_MEMORY_OUT_DATA_RD->read() << endl
606	<< std::dec;
607
608	// TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), read_lsq);
609	}
610	}
611	}
612	}
613
614	LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
615	if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read())
616	{
617	Tcontext_t context_id;
618	Tpacket_t packet_id ;
619	if (_param->_have_port_dcache_context_id)
620	context_id = out_DCACHE_REQ_CONTEXT_ID->read();
621	else
622	context_id = 0;
623
624	packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
625
626	LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id));
627
628	// TEST(Tcontext_t ,out_DCACHE_REQ_CONTEXT_ID->read(),((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) \|
629	// (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) \|
630	// (tab_request[packet_id]._context_id)));
631	// TEST(Tdcache_address_t,out_DCACHE_REQ_ADDRESS ->read(),(tab_request[packet_id]._immediat +
632	// tab_request[packet_id]._data_ra) );
633	// TEST(Tdcache_type_t ,out_DCACHE_REQ_TYPE ->read(), operation_to_dcache_type(operation));
634
635	// if (is_operation_memory_store(operation))
636	// TEST(Tdcache_data_t ,out_DCACHE_REQ_WDATA ->read(),tab_request[packet_id]._data_rb);
637
638	Tdcache_data_t rdata = _memory->access (context_id, out_DCACHE_REQ_ADDRESS->read(), out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
639
640	// test type : send or not a respons !
641	LABEL(" * rdata : " + toString(rdata));
642
643	if ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_SYNCHRONIZATION) or
644	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD))
645	{
646	LABEL(" * have_dcache_rsp");
647
648	_cache->push (context_id,
649	out_DCACHE_REQ_PACKET_ID ->read(),
650	rdata ,
651	0);
652	}
653	}
654
655	LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read()));
656	if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
657	{
658	_cache->pop();
659	}
660
661	_cache->end_cycle();
662
663	SC_START(1);
664	}
665	}
666	}
667	catch (morpheo::ErrorMorpheo & error)
668	{
669	_memory->trace();
670	throw (error);
671	}
672
673	_memory->trace();
674
675
676	/********************************************************
677	* Simulation - End
678	********************************************************/
679
680	TEST_OK ("End of Simulation");
681	delete _time;
682	cout << "<" << name << "> ............ Stop Simulation" << endl;
683
684	delete in_CLOCK;
685	delete in_NRESET;
686
687	delete in_MEMORY_IN_VAL ;
688	delete out_MEMORY_IN_ACK ;
689	delete in_MEMORY_IN_CONTEXT_ID ;
690	delete in_MEMORY_IN_FRONT_END_ID ;
691	delete in_MEMORY_IN_OOO_ENGINE_ID ;
692	delete in_MEMORY_IN_PACKET_ID ;
693	delete in_MEMORY_IN_OPERATION ;
694	delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
695	delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
696	delete in_MEMORY_IN_HAS_IMMEDIAT;
697	delete in_MEMORY_IN_IMMEDIAT ;
698	delete in_MEMORY_IN_DATA_RA ;
699	delete in_MEMORY_IN_DATA_RB ;
700	delete in_MEMORY_IN_DATA_RC ;
701	delete in_MEMORY_IN_WRITE_RD ;
702	delete in_MEMORY_IN_NUM_REG_RD ;
703	delete in_MEMORY_IN_WRITE_RE ;
704	delete in_MEMORY_IN_NUM_REG_RE ;
705
706	delete out_MEMORY_OUT_VAL ;
707	delete in_MEMORY_OUT_ACK ;
708	delete out_MEMORY_OUT_CONTEXT_ID;
709	delete out_MEMORY_OUT_FRONT_END_ID;
710	delete out_MEMORY_OUT_OOO_ENGINE_ID;
711	delete out_MEMORY_OUT_PACKET_ID ;
712	// delete out_MEMORY_OUT_OPERATION ;
713	delete out_MEMORY_OUT_TYPE ;
714	delete out_MEMORY_OUT_WRITE_RD ;
715	delete out_MEMORY_OUT_NUM_REG_RD;
716	delete out_MEMORY_OUT_DATA_RD ;
717	delete out_MEMORY_OUT_WRITE_RE ;
718	delete out_MEMORY_OUT_NUM_REG_RE;
719	delete out_MEMORY_OUT_DATA_RE ;
720	delete out_MEMORY_OUT_EXCEPTION ;
721	delete out_MEMORY_OUT_NO_SEQUENCE;
722	delete out_MEMORY_OUT_ADDRESS ;
723
724	delete out_DCACHE_REQ_VAL ;
725	delete in_DCACHE_REQ_ACK ;
726	delete out_DCACHE_REQ_CONTEXT_ID;
727	delete out_DCACHE_REQ_PACKET_ID ;
728	delete out_DCACHE_REQ_ADDRESS ;
729	delete out_DCACHE_REQ_TYPE ;
730	delete out_DCACHE_REQ_WDATA ;
731
732	delete in_DCACHE_RSP_VAL ;
733	delete out_DCACHE_RSP_ACK ;
734	delete in_DCACHE_RSP_CONTEXT_ID;
735	delete in_DCACHE_RSP_PACKET_ID ;
736	delete in_DCACHE_RSP_RDATA ;
737	delete in_DCACHE_RSP_ERROR ;
738
739	{
740	delete [] out_BYPASS_MEMORY_VAL ;
741	delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
742	delete [] out_BYPASS_MEMORY_NUM_REG ;
743	delete [] out_BYPASS_MEMORY_DATA ;
744	}
745	#endif
746
747	delete _Load_store_unit;
748	delete _memory;
749	delete _cache;
750	#ifdef STATISTICS
751	delete _parameters_statistics;
752	#endif
753	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp @ 78

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