1 | /* |
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2 | * $Id: test2.cpp 117 2009-05-16 14:42:39Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #include <queue> |
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10 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h" |
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11 | #include "Behavioural/include/Allocation.h" |
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12 | |
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13 | //===================================================================={test} |
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14 | void test2 (void) |
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15 | { |
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16 | std::string name = "Test_Load_store_queue_manual"; |
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17 | |
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18 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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19 | |
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20 | |
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21 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters |
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22 | ( |
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23 | 4, //_size_store_queue |
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24 | 4, //_size_load_queue |
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25 | 2, //_size_speculative_access_queue |
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26 | 2, //_nb_port_check |
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27 | SPECULATIVE_LOAD_COMMIT, //_speculative_load |
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28 | 0, //_nb_bypass_memory |
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29 | 1, //_nb_cache_port |
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30 | 1, //_nb_inst_memory |
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31 | 1, //_nb_context |
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32 | 1, //_nb_front_end |
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33 | 2, //_nb_ooo_engine |
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34 | 128,//_nb_packet |
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35 | 32, //_size_general_data |
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36 | 2 , //_size_special_data |
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37 | 64, //_nb_general_register |
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38 | 16, //_nb_special_register |
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39 | true //is_toplevel |
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40 | ); |
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41 | |
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42 | #ifdef STATISTICS |
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43 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); |
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44 | #endif |
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45 | |
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46 | Tusage_t _usage = USE_ALL; |
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47 | |
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48 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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49 | // _usage = usage_unset(_usage,USE_VHDL ); |
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50 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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51 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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52 | // _usage = usage_unset(_usage,USE_POSITION ); |
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53 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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54 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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55 | |
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56 | Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(), |
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57 | #ifdef STATISTICS |
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58 | _parameters_statistics, |
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59 | #endif |
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60 | _param, |
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61 | _usage); |
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62 | |
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63 | #ifdef SYSTEMC |
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64 | /********************************************************************* |
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65 | * Déclarations des signaux |
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66 | *********************************************************************/ |
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67 | string rename = ""; |
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68 | |
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69 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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70 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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71 | |
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72 | sc_signal<Tcontrol_t > ** in_MEMORY_IN_VAL ; |
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73 | sc_signal<Tcontrol_t > ** out_MEMORY_IN_ACK ; |
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74 | sc_signal<Tcontext_t > ** in_MEMORY_IN_CONTEXT_ID ; |
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75 | sc_signal<Tcontext_t > ** in_MEMORY_IN_FRONT_END_ID ; |
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76 | sc_signal<Tcontext_t > ** in_MEMORY_IN_OOO_ENGINE_ID ; |
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77 | sc_signal<Tpacket_t > ** in_MEMORY_IN_PACKET_ID ; |
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78 | sc_signal<Toperation_t > ** in_MEMORY_IN_OPERATION ; |
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79 | sc_signal<Ttype_t > ** in_MEMORY_IN_TYPE ; |
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80 | sc_signal<Tlsq_ptr_t > ** in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; |
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81 | sc_signal<Tlsq_ptr_t > ** in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; |
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82 | sc_signal<Tcontrol_t > ** in_MEMORY_IN_HAS_IMMEDIAT ; |
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83 | sc_signal<Tgeneral_data_t > ** in_MEMORY_IN_IMMEDIAT ; |
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84 | sc_signal<Tgeneral_data_t > ** in_MEMORY_IN_DATA_RA ; |
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85 | sc_signal<Tgeneral_data_t > ** in_MEMORY_IN_DATA_RB ; |
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86 | sc_signal<Tspecial_data_t > ** in_MEMORY_IN_DATA_RC ; |
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87 | sc_signal<Tcontrol_t > ** in_MEMORY_IN_WRITE_RD ; |
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88 | sc_signal<Tgeneral_address_t> ** in_MEMORY_IN_NUM_REG_RD ; |
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89 | sc_signal<Tcontrol_t > ** in_MEMORY_IN_WRITE_RE ; |
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90 | sc_signal<Tspecial_address_t> ** in_MEMORY_IN_NUM_REG_RE ; |
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91 | sc_signal<Tcontrol_t > ** out_MEMORY_OUT_VAL ; |
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92 | sc_signal<Tcontrol_t > ** in_MEMORY_OUT_ACK ; |
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93 | sc_signal<Tcontext_t > ** out_MEMORY_OUT_CONTEXT_ID ; |
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94 | sc_signal<Tcontext_t > ** out_MEMORY_OUT_FRONT_END_ID ; |
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95 | sc_signal<Tcontext_t > ** out_MEMORY_OUT_OOO_ENGINE_ID ; |
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96 | sc_signal<Tpacket_t > ** out_MEMORY_OUT_PACKET_ID ; |
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97 | //sc_signal<Toperation_t > ** out_MEMORY_OUT_OPERATION ; |
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98 | //sc_signal<Ttype_t > ** out_MEMORY_OUT_TYPE ; |
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99 | sc_signal<Tcontrol_t > ** out_MEMORY_OUT_WRITE_RD ; |
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100 | sc_signal<Tgeneral_address_t> ** out_MEMORY_OUT_NUM_REG_RD ; |
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101 | sc_signal<Tgeneral_data_t > ** out_MEMORY_OUT_DATA_RD ; |
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102 | sc_signal<Tcontrol_t > ** out_MEMORY_OUT_WRITE_RE ; |
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103 | sc_signal<Tspecial_address_t> ** out_MEMORY_OUT_NUM_REG_RE ; |
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104 | sc_signal<Tspecial_data_t > ** out_MEMORY_OUT_DATA_RE ; |
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105 | sc_signal<Texception_t > ** out_MEMORY_OUT_EXCEPTION ; |
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106 | sc_signal<Tcontrol_t > ** out_MEMORY_OUT_NO_SEQUENCE ; |
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107 | sc_signal<Taddress_t > ** out_MEMORY_OUT_ADDRESS ; |
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108 | sc_signal<Tcontrol_t > ** out_DCACHE_REQ_VAL ; |
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109 | sc_signal<Tcontrol_t > ** in_DCACHE_REQ_ACK ; |
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110 | sc_signal<Tcontext_t > ** out_DCACHE_REQ_CONTEXT_ID ; |
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111 | sc_signal<Tpacket_t > ** out_DCACHE_REQ_PACKET_ID ; |
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112 | sc_signal<Tdcache_address_t > ** out_DCACHE_REQ_ADDRESS ; |
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113 | sc_signal<Tdcache_type_t > ** out_DCACHE_REQ_TYPE ; |
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114 | sc_signal<Tdcache_data_t > ** out_DCACHE_REQ_WDATA ; |
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115 | sc_signal<Tcontrol_t > ** in_DCACHE_RSP_VAL ; |
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116 | sc_signal<Tcontrol_t > ** out_DCACHE_RSP_ACK ; |
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117 | sc_signal<Tcontext_t > ** in_DCACHE_RSP_CONTEXT_ID ; |
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118 | sc_signal<Tpacket_t > ** in_DCACHE_RSP_PACKET_ID ; |
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119 | sc_signal<Tdcache_data_t > ** in_DCACHE_RSP_RDATA ; |
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120 | sc_signal<Tdcache_error_t > ** in_DCACHE_RSP_ERROR ; |
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121 | sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL ; |
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122 | sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID ; |
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123 | sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG ; |
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124 | sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA ; |
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125 | |
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126 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_VAL ," in_MEMORY_IN_VAL ",Tcontrol_t ,_param->_nb_inst_memory); |
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127 | ALLOC1_SC_SIGNAL(out_MEMORY_IN_ACK ,"out_MEMORY_IN_ACK ",Tcontrol_t ,_param->_nb_inst_memory); |
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128 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID ," in_MEMORY_IN_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_memory); |
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129 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID ," in_MEMORY_IN_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_memory); |
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130 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ," in_MEMORY_IN_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_memory); |
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131 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID ," in_MEMORY_IN_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory); |
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132 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_OPERATION ," in_MEMORY_IN_OPERATION ",Toperation_t ,_param->_nb_inst_memory); |
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133 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_TYPE ," in_MEMORY_IN_TYPE ",Ttype_t ,_param->_nb_inst_memory); |
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134 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE," in_MEMORY_IN_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_memory); |
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135 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ," in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_memory); |
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136 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ," in_MEMORY_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_memory); |
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137 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT ," in_MEMORY_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_memory); // memory address |
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138 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RA ," in_MEMORY_IN_DATA_RA ",Tgeneral_data_t ,_param->_nb_inst_memory); // memory address |
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139 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RB ," in_MEMORY_IN_DATA_RB ",Tgeneral_data_t ,_param->_nb_inst_memory); // data (store) |
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140 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RC ," in_MEMORY_IN_DATA_RC ",Tspecial_data_t ,_param->_nb_inst_memory); |
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141 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD ," in_MEMORY_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load) |
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142 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD ," in_MEMORY_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load) |
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143 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE ," in_MEMORY_IN_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_memory); |
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144 | ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE ," in_MEMORY_IN_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_memory); |
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145 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_VAL ,"out_MEMORY_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_memory); |
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146 | ALLOC1_SC_SIGNAL( in_MEMORY_OUT_ACK ," in_MEMORY_OUT_ACK ",Tcontrol_t ,_param->_nb_inst_memory); |
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147 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,"out_MEMORY_OUT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_memory); |
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148 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,"out_MEMORY_OUT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_memory); |
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149 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID ,"out_MEMORY_OUT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_memory); |
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150 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,"out_MEMORY_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory); |
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151 | //ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,"out_MEMORY_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_memory); |
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152 | //ALLOC1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,"out_MEMORY_OUT_TYPE ",Ttype_t ,_param->_nb_inst_memory); |
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153 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,"out_MEMORY_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load) |
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154 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,"out_MEMORY_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load) |
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155 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD ,"out_MEMORY_OUT_DATA_RD ",Tgeneral_data_t ,_param->_nb_inst_memory); // data (load) |
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156 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE ,"out_MEMORY_OUT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_memory); |
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157 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,"out_MEMORY_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_memory); |
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158 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE ,"out_MEMORY_OUT_DATA_RE ",Tspecial_data_t ,_param->_nb_inst_memory); |
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159 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,"out_MEMORY_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_memory); |
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160 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,"out_MEMORY_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_memory); |
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161 | ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",Taddress_t ,_param->_nb_inst_memory); |
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162 | ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_cache_port); |
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163 | ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_cache_port); |
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164 | ALLOC1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,"out_DCACHE_REQ_CONTEXT_ID ",Tcontext_t ,_param->_nb_cache_port); |
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165 | ALLOC1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,"out_DCACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_cache_port); |
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166 | ALLOC1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,"out_DCACHE_REQ_ADDRESS ",Tdcache_address_t ,_param->_nb_cache_port); |
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167 | ALLOC1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,"out_DCACHE_REQ_TYPE ",Tdcache_type_t ,_param->_nb_cache_port); |
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168 | ALLOC1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,"out_DCACHE_REQ_WDATA ",Tdcache_data_t ,_param->_nb_cache_port); |
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169 | ALLOC1_SC_SIGNAL( in_DCACHE_RSP_VAL ," in_DCACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_cache_port); |
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170 | ALLOC1_SC_SIGNAL(out_DCACHE_RSP_ACK ,"out_DCACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_cache_port); |
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171 | ALLOC1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ," in_DCACHE_RSP_CONTEXT_ID ",Tcontext_t ,_param->_nb_cache_port); |
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172 | ALLOC1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ," in_DCACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_cache_port); |
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173 | ALLOC1_SC_SIGNAL( in_DCACHE_RSP_RDATA ," in_DCACHE_RSP_RDATA ",Tdcache_data_t ,_param->_nb_cache_port); |
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174 | ALLOC1_SC_SIGNAL( in_DCACHE_RSP_ERROR ," in_DCACHE_RSP_ERROR ",Tdcache_error_t ,_param->_nb_cache_port); |
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175 | ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_VAL ,"out_BYPASS_MEMORY_VAL ",Tcontrol_t ,_param->_nb_bypass_memory); |
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176 | ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"out_BYPASS_MEMORY_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_bypass_memory); |
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177 | ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,"out_BYPASS_MEMORY_NUM_REG ",Tgeneral_address_t,_param->_nb_bypass_memory); |
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178 | ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_DATA ,"out_BYPASS_MEMORY_DATA ",Tgeneral_data_t ,_param->_nb_bypass_memory); |
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179 | |
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180 | /******************************************************** |
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181 | * Instanciation |
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182 | ********************************************************/ |
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183 | |
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184 | cout << "<" << name << "> Instanciation of _Load_store_unit" << endl; |
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185 | |
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186 | (*(_Load_store_unit->in_CLOCK)) (*(in_CLOCK)); |
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187 | (*(_Load_store_unit->in_NRESET)) (*(in_NRESET)); |
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188 | |
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189 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_VAL ,_param->_nb_inst_memory); |
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190 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_IN_ACK ,_param->_nb_inst_memory); |
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191 | if (_param->_have_port_context_id) |
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192 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory); |
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193 | if (_param->_have_port_front_end_id) |
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194 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory); |
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195 | if (_param->_have_port_ooo_engine_id) |
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196 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory); |
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197 | if (_param->_have_port_rob_ptr) |
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198 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory); |
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199 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory); |
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200 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_TYPE ,_param->_nb_inst_memory); |
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201 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory); |
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202 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory); |
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203 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory); |
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204 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory); |
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205 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory); |
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206 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory); |
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207 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory); |
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208 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory); |
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209 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory); |
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210 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory); |
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211 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory); |
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212 | |
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213 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_VAL ,_param->_nb_inst_memory); |
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214 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_OUT_ACK ,_param->_nb_inst_memory); |
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215 | if (_param->_have_port_context_id) |
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216 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory); |
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217 | if (_param->_have_port_front_end_id) |
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218 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory); |
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219 | if (_param->_have_port_ooo_engine_id) |
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220 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory); |
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221 | if (_param->_have_port_rob_ptr) |
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222 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); |
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223 | //INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); |
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224 | //INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); |
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225 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); |
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226 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); |
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227 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory); |
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228 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory); |
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229 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory); |
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230 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory); |
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231 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory); |
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232 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory); |
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233 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory); |
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234 | |
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235 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_VAL ,_param->_nb_cache_port); |
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236 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_REQ_ACK ,_param->_nb_cache_port); |
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237 | if (_param->_have_port_dcache_context_id) |
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238 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port); |
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239 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port); |
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240 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port); |
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241 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_TYPE ,_param->_nb_cache_port); |
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242 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_WDATA ,_param->_nb_cache_port); |
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243 | |
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244 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_VAL ,_param->_nb_cache_port); |
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245 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_RSP_ACK ,_param->_nb_cache_port); |
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246 | if (_param->_have_port_dcache_context_id) |
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247 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port); |
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248 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port); |
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249 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_RDATA ,_param->_nb_cache_port); |
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250 | INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_ERROR ,_param->_nb_cache_port); |
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251 | |
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252 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory); |
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253 | if (_param->_have_port_ooo_engine_id) |
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254 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory); |
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255 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory); |
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256 | INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory); |
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257 | |
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258 | |
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259 | cout << "<" << name << "> Start Simulation ............" << endl; |
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260 | Time * _time = new Time(); |
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261 | |
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262 | /******************************************************** |
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263 | * Simulation - Begin |
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264 | ********************************************************/ |
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265 | |
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266 | // Initialisation |
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267 | |
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268 | const uint32_t seed = 0; |
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269 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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270 | |
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271 | srand(seed); |
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272 | |
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273 | const int32_t percent_transaction_memory_out = 100; |
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274 | const int32_t percent_transaction_dcache = 100; |
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275 | const uint32_t miss_rate = 0; |
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276 | const uint32_t miss_penality = 0; |
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277 | |
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278 | uint32_t nb_request_memory_out=0; |
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279 | |
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280 | MemoryRequest_t tab_request [_param->_nb_packet]; |
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281 | priority_queue<MemoryRequest_t> fifo_request; |
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282 | |
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283 | const uint32_t size_memory = 0x100; |
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284 | // emulation of memory |
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285 | Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, size_memory, _param->_size_general_data); |
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286 | Cache_t * _cache = new Cache_t (miss_rate, miss_penality); |
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287 | |
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288 | SC_START(0); |
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289 | |
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290 | LABEL("Initialisation"); |
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291 | |
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292 | in_MEMORY_IN_VAL [0]->write(0); |
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293 | in_MEMORY_OUT_ACK[0]->write(0); |
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294 | in_DCACHE_REQ_ACK[0]->write(0); |
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295 | in_DCACHE_RSP_VAL[0]->write(0); |
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296 | |
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297 | in_NRESET ->write(0); |
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298 | SC_START(5); |
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299 | in_NRESET ->write(5); |
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300 | |
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301 | LABEL("Loop of Test"); |
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302 | |
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303 | try |
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304 | { |
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305 | LABEL("Structure's initialisation"); |
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306 | |
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307 | bool store_queue_use [_param->_size_store_queue]; |
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308 | uint32_t nb_store_slot_use = 0; |
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309 | bool load_queue_use [_param->_size_load_queue ]; |
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310 | |
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311 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
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312 | store_queue_use [i] = false; |
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313 | for (uint32_t i=0; i<_param->_size_load_queue ; i++) |
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314 | load_queue_use [i] = false; |
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315 | |
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316 | |
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317 | //-------------------------------------------------------------------------------------------------------------- |
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318 | // c c f o p o t s l i d d w n w |
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319 | // y o r o a p y t o m a a r u r |
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320 | // c n o o c e p o a m t t i m i |
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321 | // l t n _ k r e r d e a a t _ t |
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322 | // e e t e e a e _ d _ _ e r e |
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323 | // x _ n t t _ p i r r _ _ _ |
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324 | // t e g _ i p t a a b r g s |
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325 | // _ n i i o t r t d _ p |
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326 | // i d n d n r _ r e |
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327 | // d _ e _ w d c |
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328 | // i _ w r _ |
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329 | // d i r i k |
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330 | // d i t o |
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331 | // t e |
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332 | // e |
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333 | // |
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334 | tab_request[ 0].modif( 5,0,0,0, 0,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x10 ,0xdead1234,0,0,0); |
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335 | |
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336 | tab_request[ 1].modif(10,0,0,0, 0,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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337 | |
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338 | // READ 32b |
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339 | tab_request[ 2].modif(12,0,0,0, 2,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,1,0,0xdead1234); |
---|
340 | tab_request[ 3].modif(13,0,0,0, 3,OPERATION_MEMORY_LOAD_32_S ,TYPE_MEMORY,1,1,0x10 ,0x0 ,0x0 ,1,2,0,0xdead1234); |
---|
341 | |
---|
342 | // READ 16b |
---|
343 | tab_request[ 4].modif(14,0,0,0, 4,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,2,0x10 ,0x0 ,0x0 ,1,3,0,0x00001234); |
---|
344 | tab_request[ 5].modif(15,0,0,0, 5,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,3,0x12 ,0x0 ,0x0 ,1,4,0,0x0000dead); |
---|
345 | tab_request[ 6].modif(16,0,0,0, 6,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,5,0,0x00001234); |
---|
346 | tab_request[ 7].modif(17,0,0,0, 7,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,1,0x12 ,0x0 ,0x0 ,1,6,0,0xffffdead); |
---|
347 | |
---|
348 | // READ 8b |
---|
349 | tab_request[ 8].modif(18,0,0,0, 8,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,7,0,0x00000034); |
---|
350 | tab_request[ 9].modif(19,0,0,0, 9,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,8,0,0x00000012); |
---|
351 | tab_request[10].modif(20,0,0,0,10,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,9,0,0x000000ad); |
---|
352 | tab_request[11].modif(21,0,0,0,11,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,1,0,0x000000de); |
---|
353 | tab_request[12].modif(22,0,0,0,12,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,2,0,0x00000034); |
---|
354 | tab_request[13].modif(23,0,0,0,13,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,3,0,0x00000012); |
---|
355 | tab_request[14].modif(24,0,0,0,14,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,4,0,0xffffffad); |
---|
356 | tab_request[15].modif(25,0,0,0,15,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,5,0,0xffffffde); |
---|
357 | |
---|
358 | // STORE 16b |
---|
359 | tab_request[16].modif(30,0,0,0,16,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x20 ,0x0 ,0xffffabcd,0,0,0); |
---|
360 | tab_request[17].modif(31,0,0,0,17,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x22 ,0x0 ,0xffffdcba,0,0,0); |
---|
361 | tab_request[18].modif(35,0,0,0,18,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
362 | tab_request[19].modif(36,0,0,0,19,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
363 | tab_request[20].modif(40,0,0,0,20,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x20 ,0x0 ,0x0 ,1,0,0,0xdcbaabcd); |
---|
364 | |
---|
365 | // STORE 8b and head / valid out order |
---|
366 | tab_request[21].modif(50,0,0,0,21,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,3,0,0x1 ,0x4 ,0xffffff56,0,0,0); |
---|
367 | tab_request[22].modif(55,0,0,0,22,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x1 ,0x0 ,0x0 ,0,0,0); |
---|
368 | tab_request[23].modif(48,0,0,0,23,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,0,0,0x0 ,0x4 ,0xffffff78,0,0,0); |
---|
369 | tab_request[24].modif(43,0,0,0,24,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
370 | tab_request[25].modif(47,0,0,0,25,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,1,0,0x3 ,0x4 ,0xffffff12,0,0,0); |
---|
371 | tab_request[26].modif(49,0,0,0,26,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
372 | tab_request[27].modif(57,0,0,0,27,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x2 ,0x4 ,0xffffff34,0,0,0); |
---|
373 | tab_request[28].modif(44,0,0,0,28,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
374 | tab_request[29].modif(70,0,0,0,29,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x2 ,0x2 ,0x0 ,1,0,0,0x12345678); |
---|
375 | |
---|
376 | // CHECK - with a store not present, store format is >= |
---|
377 | tab_request[30].modif(180,0,0,0,30,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x30 ,0x21071981,0,0,0); |
---|
378 | tab_request[31].modif(179,0,0,0,31,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
379 | tab_request[32].modif(173,0,0,0,32,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x30 ,0x0 ,1,0,0,0x21071981); |
---|
380 | tab_request[33].modif(174,0,0,0,33,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,3,0x0 ,0x30 ,0x0 ,1,0,0,0x00001981); |
---|
381 | tab_request[34].modif(175,0,0,0,34,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,0,0x0 ,0x32 ,0x0 ,1,0,0,0x00002107); |
---|
382 | tab_request[35].modif(176,0,0,0,35,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,0,1,0x0 ,0x31 ,0x0 ,1,0,0,0x00000019); |
---|
383 | |
---|
384 | // CHECK - with a store not present, multiple store and format is different |
---|
385 | tab_request[36].modif(200,0,0,0,36,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x40 ,0xffffffff,0,0,0); |
---|
386 | tab_request[37].modif(200,0,0,0,37,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
387 | tab_request[38].modif(220,0,0,0,38,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x0 ,0x42 ,0xbaba ,0,0,0); |
---|
388 | tab_request[39].modif(245,0,0,0,39,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
389 | tab_request[40].modif(224,0,0,0,40,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x0 ,0x42 ,0xbe ,0,0,0); |
---|
390 | tab_request[41].modif(240,0,0,0,41,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
391 | tab_request[42].modif(228,0,0,0,42,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0xf00d ,0,0,0); |
---|
392 | tab_request[43].modif(235,0,0,0,43,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
393 | tab_request[44].modif(210,0,0,0,44,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x40 ,0x0 ,1,0,0,0xbabef00d); |
---|
394 | tab_request[45].modif(211,0,0,0,45,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,2,3,0x0 ,0x40 ,0x0 ,1,0,0,0xbabaffff); |
---|
395 | tab_request[46].modif(212,0,0,0,46,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0x0 ,1,0,0,0xbabeffff); |
---|
396 | tab_request[47].modif(213,0,0,0,47,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,3,1,0x0 ,0x42 ,0x0 ,1,0,0,0xffffffbe); |
---|
397 | |
---|
398 | |
---|
399 | // CHECK - with different ooo_engine_id |
---|
400 | tab_request[48].modif(300,0,0,0,48,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x0 ,0xdad1900d,0,0,0); |
---|
401 | tab_request[49].modif(300,0,0,0,49,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
402 | tab_request[50].modif(300,0,0,1,50,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x55508570,0,0,0); |
---|
403 | tab_request[51].modif(300,0,0,1,51,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
404 | |
---|
405 | |
---|
406 | tab_request[52].modif(320,0,0,0,52,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,2,0x0 ,0x2 ,0x0 ,1,0,0,0xffffdad1); |
---|
407 | tab_request[53].modif(321,0,0,1,53,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,3,0x0 ,0x0 ,0x0 ,1,0,0,0xffff8570); |
---|
408 | |
---|
409 | |
---|
410 | // with a little exception |
---|
411 | tab_request[54].modif(330,0,0,1,54,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x0 ,0x0 ,0xffff6996,0,0,1); |
---|
412 | tab_request[55].modif(340,0,0,1,55,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
413 | tab_request[56].modif(322,0,0,1,56,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,1,0,0,0x00000069); // they are a bypass (because, the cpu go in exception handler ... load is not use) |
---|
414 | tab_request[57].modif(350,0,0,1,57,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // the memory have not change |
---|
415 | |
---|
416 | |
---|
417 | // multiple event |
---|
418 | // * store : miss_spec and aligment, priority : miss_spec > aligment |
---|
419 | // * load : miss_spec and aligment, priority : miss_spec > aligment |
---|
420 | tab_request[58].modif(410,0,0,0,58,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,0,0,1); |
---|
421 | tab_request[59].modif(415,0,0,0,59,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
422 | |
---|
423 | tab_request[60].modif(430,0,0,0,60,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x0 ,0x0 ,1,0,0,0xdad1900d); |
---|
424 | tab_request[61].modif(400,0,0,0,61,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,3,0x0 ,0x3 ,0x0 ,1,0,0); // miss_spec and alignment |
---|
425 | tab_request[62].modif(450,0,0,0,62,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,1,0,0); // bus error and alignement |
---|
426 | tab_request[63].modif(460,0,0,0,63,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,1,0x0 ,size_memory+1,0x0 ,1,0,0); // bus error and alignement |
---|
427 | |
---|
428 | |
---|
429 | |
---|
430 | tab_request[64].modif(500,0,0,0,64,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,0,0,0); // bus error |
---|
431 | tab_request[65].modif(505,0,0,0,65,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
---|
432 | tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // just to wait the dcache_rsp |
---|
433 | |
---|
434 | const uint32_t nb_request = 66;//_param->_nb_packet; |
---|
435 | // const uint32_t nb_request = 64;//_param->_nb_packet; |
---|
436 | |
---|
437 | for (uint32_t i=0; i<nb_request; i++) |
---|
438 | { |
---|
439 | std::cout << tab_request [i] << std::endl; |
---|
440 | fifo_request.push(tab_request [i]); |
---|
441 | } |
---|
442 | LABEL("Simulation ..."); |
---|
443 | |
---|
444 | while (nb_request_memory_out < nb_request) |
---|
445 | { |
---|
446 | cout << "*********************************************" << endl; |
---|
447 | cout << "Dump STORE_QUEUE_USE : " << endl; |
---|
448 | cout << " use " << nb_store_slot_use << endl; |
---|
449 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
---|
450 | cout << " [" << i << "] " << store_queue_use [i] << endl; |
---|
451 | cout << "Dump LOAD_QUEUE_USE : " << endl; |
---|
452 | for (uint32_t i=0; i<_param->_size_load_queue ; i++) |
---|
453 | cout << " [" << i << "] " << load_queue_use [i] << endl; |
---|
454 | cout << "*********************************************" << endl; |
---|
455 | |
---|
456 | |
---|
457 | // ***** MEMORY_IN ***** |
---|
458 | |
---|
459 | // memory_in_val depends of three factors : |
---|
460 | // 1) request's fifo is not empty ? |
---|
461 | // 2) the slot destination is free ? |
---|
462 | // 3) The head of request's fifo can be issue : the number of cycle is more than current cycle |
---|
463 | |
---|
464 | bool can_execute = false; |
---|
465 | |
---|
466 | if (not fifo_request.empty()) |
---|
467 | { |
---|
468 | can_execute = simulation_cycle() >= fifo_request.top()._cycle; |
---|
469 | if (is_operation_memory_store(fifo_request.top()._operation)) |
---|
470 | can_execute &= (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation); |
---|
471 | else |
---|
472 | can_execute &= not load_queue_use [fifo_request.top()._load_queue_ptr_write]; |
---|
473 | } |
---|
474 | in_MEMORY_IN_VAL [0]->write(can_execute); |
---|
475 | |
---|
476 | if (not fifo_request.empty()) |
---|
477 | { |
---|
478 | if (_param->_have_port_context_id) |
---|
479 | in_MEMORY_IN_CONTEXT_ID [0]->write (fifo_request.top()._context_id ); |
---|
480 | if (_param->_have_port_front_end_id) |
---|
481 | in_MEMORY_IN_FRONT_END_ID [0]->write (fifo_request.top()._front_end_id ); |
---|
482 | if (_param->_have_port_ooo_engine_id) |
---|
483 | in_MEMORY_IN_OOO_ENGINE_ID [0]->write (fifo_request.top()._ooo_engine_id ); |
---|
484 | if (_param->_have_port_rob_ptr) |
---|
485 | in_MEMORY_IN_PACKET_ID [0]->write (fifo_request.top()._packet_id ); |
---|
486 | in_MEMORY_IN_OPERATION [0]->write (fifo_request.top()._operation ); |
---|
487 | in_MEMORY_IN_TYPE [0]->write (fifo_request.top()._type ); |
---|
488 | in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[0]->write (fifo_request.top()._store_queue_ptr_write); |
---|
489 | if (_param->_have_port_load_queue_ptr) |
---|
490 | in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE [0]->write (fifo_request.top()._load_queue_ptr_write ); |
---|
491 | in_MEMORY_IN_IMMEDIAT [0]->write (fifo_request.top()._immediat ); |
---|
492 | in_MEMORY_IN_DATA_RA [0]->write (fifo_request.top()._data_ra ); |
---|
493 | in_MEMORY_IN_DATA_RB [0]->write (fifo_request.top()._data_rb ); |
---|
494 | // in_MEMORY_IN_WRITE_RD [0]->write (fifo_request.top()._write_rd ); |
---|
495 | in_MEMORY_IN_NUM_REG_RD [0]->write (fifo_request.top()._num_reg_rd ); |
---|
496 | } |
---|
497 | in_MEMORY_OUT_ACK[0]->write((rand()%100)<percent_transaction_memory_out); |
---|
498 | |
---|
499 | // ***** DCACHE_REQ ***** |
---|
500 | in_DCACHE_REQ_ACK[0]->write((rand()%100)<percent_transaction_dcache); |
---|
501 | |
---|
502 | // ***** DCACHE_RSP ***** |
---|
503 | bool have_rsp = _cache->have_rsp (); |
---|
504 | in_DCACHE_RSP_VAL[0]->write(have_rsp); |
---|
505 | |
---|
506 | if (have_rsp) |
---|
507 | { |
---|
508 | in_DCACHE_RSP_CONTEXT_ID[0]->write(_cache->front()._context_id); |
---|
509 | in_DCACHE_RSP_PACKET_ID [0]->write(_cache->front()._packet_id ); |
---|
510 | in_DCACHE_RSP_RDATA [0]->write(_cache->front()._rdata ); |
---|
511 | in_DCACHE_RSP_ERROR [0]->write(_cache->front()._error ); |
---|
512 | } |
---|
513 | |
---|
514 | SC_START(0); |
---|
515 | |
---|
516 | LABEL("MEMORY_IN : %d - %d",in_MEMORY_IN_VAL [0]->read(),out_MEMORY_IN_ACK [0]->read()); |
---|
517 | if ( in_MEMORY_IN_VAL [0]->read() and out_MEMORY_IN_ACK [0]->read()) |
---|
518 | { |
---|
519 | Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID[0]->read(); |
---|
520 | |
---|
521 | LABEL(" * Accepted MEMORY_IN : %d",packet_id); |
---|
522 | cout << fifo_request.top(); |
---|
523 | |
---|
524 | if (is_operation_memory_store(fifo_request.top()._operation)) |
---|
525 | { |
---|
526 | if (not is_operation_memory_store_head(fifo_request.top()._operation)) |
---|
527 | { |
---|
528 | store_queue_use [fifo_request.top()._store_queue_ptr_write] = true; |
---|
529 | nb_store_slot_use ++; |
---|
530 | } |
---|
531 | } |
---|
532 | else |
---|
533 | load_queue_use [fifo_request.top()._load_queue_ptr_write] = true; |
---|
534 | |
---|
535 | fifo_request.pop(); |
---|
536 | } |
---|
537 | |
---|
538 | LABEL("MEMORY_OUT : %d - %d",out_MEMORY_OUT_VAL[0]->read(),in_MEMORY_OUT_ACK [0]->read()); |
---|
539 | if (out_MEMORY_OUT_VAL[0]->read() and in_MEMORY_OUT_ACK[0]->read()) |
---|
540 | { |
---|
541 | Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID[0]->read(); |
---|
542 | |
---|
543 | LABEL(" * Accepted MEMORY_OUT : %d",packet_id); |
---|
544 | |
---|
545 | if (is_operation_memory_store(tab_request[packet_id]._operation)) |
---|
546 | { |
---|
547 | store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false; |
---|
548 | nb_store_slot_use --; |
---|
549 | nb_request_memory_out +=2; |
---|
550 | |
---|
551 | } |
---|
552 | else |
---|
553 | { |
---|
554 | if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) |
---|
555 | { |
---|
556 | nb_request_memory_out ++; |
---|
557 | |
---|
558 | load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false; |
---|
559 | } |
---|
560 | else |
---|
561 | { |
---|
562 | std::cout << "seth - have a load_speculative." << std::endl; |
---|
563 | tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD[0]->read() != tab_request[packet_id]._data_wait); |
---|
564 | tab_request[packet_id]._previous_load_speculative = 1; |
---|
565 | } |
---|
566 | } |
---|
567 | |
---|
568 | // a lot of test |
---|
569 | TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID [0]->read(), tab_request[packet_id]._packet_id ); |
---|
570 | TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID [0]->read(), tab_request[packet_id]._context_id ); |
---|
571 | TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID [0]->read(), tab_request[packet_id]._front_end_id ); |
---|
572 | TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID[0]->read(), tab_request[packet_id]._ooo_engine_id); |
---|
573 | // TEST(Toperation_t , out_MEMORY_OUT_OPERATION [0]->read(), tab_request[packet_id]._operation ); |
---|
574 | // TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY ); |
---|
575 | |
---|
576 | if (is_operation_memory_load (tab_request[packet_id]._operation)) |
---|
577 | { |
---|
578 | TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD [0]->read(), tab_request[packet_id]._num_reg_rd ); |
---|
579 | } |
---|
580 | |
---|
581 | Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat; |
---|
582 | |
---|
583 | bool error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation)))); |
---|
584 | bool berr = (address >= size_memory); |
---|
585 | Texception_t exception = out_MEMORY_OUT_EXCEPTION[0]->read(); |
---|
586 | |
---|
587 | if (is_operation_memory_store(tab_request[packet_id]._operation)) |
---|
588 | { |
---|
589 | TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD [0]->read(), 0); |
---|
590 | |
---|
591 | // store. |
---|
592 | // prioritary : miss_speculation > aligmnent > DBERR |
---|
593 | |
---|
594 | bool test_result_ko = false; |
---|
595 | |
---|
596 | if (tab_request[packet_id]._write_spec_ko) |
---|
597 | { |
---|
598 | TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION); |
---|
599 | } |
---|
600 | else |
---|
601 | if (error_alignment) |
---|
602 | { |
---|
603 | TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT); |
---|
604 | test_result_ko = true; |
---|
605 | } |
---|
606 | else |
---|
607 | if (berr) |
---|
608 | { |
---|
609 | // TODO NOT SUPPORTED |
---|
610 | // TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR); |
---|
611 | |
---|
612 | //test_result_ko = true; |
---|
613 | } |
---|
614 | else |
---|
615 | { |
---|
616 | TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE); |
---|
617 | } |
---|
618 | // In all case : test data |
---|
619 | if (test_result_ko) |
---|
620 | { |
---|
621 | TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), address); |
---|
622 | } |
---|
623 | } |
---|
624 | else |
---|
625 | { |
---|
626 | // load |
---|
627 | // prioritary : miss_speculation > aligmnent > DBERR |
---|
628 | |
---|
629 | bool is_load = is_operation_memory_load(tab_request[packet_id]._operation); |
---|
630 | |
---|
631 | if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) |
---|
632 | { |
---|
633 | bool test_result_ko = false; |
---|
634 | |
---|
635 | if (tab_request[packet_id]._write_spec_ko) |
---|
636 | { |
---|
637 | // IS A LOAD :D |
---|
638 | TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION); |
---|
639 | TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), 1); |
---|
640 | } |
---|
641 | else |
---|
642 | if (error_alignment) |
---|
643 | { |
---|
644 | TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT); |
---|
645 | TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), is_load); |
---|
646 | test_result_ko = true; |
---|
647 | } |
---|
648 | else |
---|
649 | if (berr) |
---|
650 | { |
---|
651 | TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR); |
---|
652 | TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load); |
---|
653 | test_result_ko = true; |
---|
654 | } |
---|
655 | else |
---|
656 | { |
---|
657 | TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE); |
---|
658 | TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load and not tab_request[packet_id]._previous_load_speculative); |
---|
659 | } |
---|
660 | // In all case : test data |
---|
661 | if (test_result_ko) |
---|
662 | { |
---|
663 | TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), address); |
---|
664 | } |
---|
665 | else |
---|
666 | { |
---|
667 | LABEL("out_MEMORY_OUT_DATA_RD[0]->read() : 0x%.8x",out_MEMORY_OUT_DATA_RD[0]->read()); |
---|
668 | LABEL("data_wait : 0x%.8x",tab_request[packet_id]._data_wait); |
---|
669 | |
---|
670 | TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), tab_request[packet_id]._data_wait); |
---|
671 | } |
---|
672 | } |
---|
673 | else |
---|
674 | { |
---|
675 | TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD [0]->read(), 1); |
---|
676 | } |
---|
677 | } |
---|
678 | } |
---|
679 | |
---|
680 | LABEL("DCACHE_REQ : %d - %d",out_DCACHE_REQ_VAL[0]->read(),in_DCACHE_REQ_ACK [0]->read()); |
---|
681 | if (out_DCACHE_REQ_VAL[0]->read() and in_DCACHE_REQ_ACK[0]->read()) |
---|
682 | { |
---|
683 | Tcontext_t context_id; |
---|
684 | Tpacket_t packet_id ; |
---|
685 | Tdcache_address_t address = out_DCACHE_REQ_ADDRESS[0]->read(); |
---|
686 | Tdcache_data_t rdata; |
---|
687 | Tdcache_error_t error = 0; |
---|
688 | if (_param->_have_port_dcache_context_id) |
---|
689 | context_id = out_DCACHE_REQ_CONTEXT_ID[0]->read(); |
---|
690 | else |
---|
691 | context_id = 0; |
---|
692 | |
---|
693 | packet_id = (out_DCACHE_REQ_PACKET_ID [0]->read())>>1; |
---|
694 | |
---|
695 | LABEL(" * Accepted DCACHE_REQ : %d",packet_id); |
---|
696 | |
---|
697 | if (address >= size_memory) |
---|
698 | { |
---|
699 | // Bus error |
---|
700 | error = DCACHE_ERROR_BUS_ERROR; |
---|
701 | rdata = address; // convention : cache return the address fautive ! |
---|
702 | } |
---|
703 | else |
---|
704 | { |
---|
705 | rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE[0]->read(), out_DCACHE_REQ_WDATA[0]->read()); |
---|
706 | LABEL(" * rdata : 0x%x",rdata); |
---|
707 | } |
---|
708 | |
---|
709 | // test type : send or not a respons ! |
---|
710 | if ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_SYNCHRONIZATION) or |
---|
711 | (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_8 ) or |
---|
712 | (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_16) or |
---|
713 | (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_32) or |
---|
714 | (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_64) or |
---|
715 | ((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_8 ) or |
---|
716 | (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_16) or |
---|
717 | (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_32) or |
---|
718 | (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_64) ))) |
---|
719 | { |
---|
720 | LABEL(" * have_dcache_rsp"); |
---|
721 | |
---|
722 | _cache->push (context_id, |
---|
723 | out_DCACHE_REQ_PACKET_ID [0]->read(), |
---|
724 | rdata, |
---|
725 | error); |
---|
726 | } |
---|
727 | } |
---|
728 | |
---|
729 | LABEL("DCACHE_RSP : %d - %d",in_DCACHE_RSP_VAL[0]->read(),out_DCACHE_RSP_ACK [0]->read()); |
---|
730 | if (in_DCACHE_RSP_VAL[0]->read() and out_DCACHE_RSP_ACK[0]->read()) |
---|
731 | { |
---|
732 | _cache->pop(); |
---|
733 | } |
---|
734 | |
---|
735 | _cache->end_cycle(); |
---|
736 | |
---|
737 | SC_START(1); |
---|
738 | } |
---|
739 | } |
---|
740 | catch (morpheo::ErrorMorpheo & error) |
---|
741 | { |
---|
742 | _memory->trace(); |
---|
743 | throw (error); |
---|
744 | } |
---|
745 | |
---|
746 | _memory->trace(); |
---|
747 | |
---|
748 | |
---|
749 | /******************************************************** |
---|
750 | * Simulation - End |
---|
751 | ********************************************************/ |
---|
752 | |
---|
753 | TEST_OK ("End of Simulation"); |
---|
754 | delete _time; |
---|
755 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
---|
756 | |
---|
757 | delete in_CLOCK; |
---|
758 | delete in_NRESET; |
---|
759 | |
---|
760 | DELETE1_SC_SIGNAL( in_MEMORY_IN_VAL ,_param->_nb_inst_memory); |
---|
761 | DELETE1_SC_SIGNAL(out_MEMORY_IN_ACK ,_param->_nb_inst_memory); |
---|
762 | DELETE1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory); |
---|
763 | DELETE1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory); |
---|
764 | DELETE1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory); |
---|
765 | DELETE1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory); |
---|
766 | DELETE1_SC_SIGNAL( in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory); |
---|
767 | DELETE1_SC_SIGNAL( in_MEMORY_IN_TYPE ,_param->_nb_inst_memory); |
---|
768 | DELETE1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory); |
---|
769 | DELETE1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory); |
---|
770 | DELETE1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory); |
---|
771 | DELETE1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory); |
---|
772 | DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory); |
---|
773 | DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory); |
---|
774 | DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory); |
---|
775 | DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory); |
---|
776 | DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory); |
---|
777 | DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory); |
---|
778 | DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory); |
---|
779 | |
---|
780 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_VAL ,_param->_nb_inst_memory); |
---|
781 | DELETE1_SC_SIGNAL( in_MEMORY_OUT_ACK ,_param->_nb_inst_memory); |
---|
782 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory); |
---|
783 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory); |
---|
784 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory); |
---|
785 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); |
---|
786 | //DELETE1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); |
---|
787 | //DELETE1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); |
---|
788 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); |
---|
789 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); |
---|
790 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory); |
---|
791 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory); |
---|
792 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory); |
---|
793 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory); |
---|
794 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory); |
---|
795 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory); |
---|
796 | DELETE1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory); |
---|
797 | |
---|
798 | DELETE1_SC_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_cache_port); |
---|
799 | DELETE1_SC_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_cache_port); |
---|
800 | DELETE1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port); |
---|
801 | DELETE1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port); |
---|
802 | DELETE1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port); |
---|
803 | DELETE1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_cache_port); |
---|
804 | DELETE1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_cache_port); |
---|
805 | |
---|
806 | DELETE1_SC_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_cache_port); |
---|
807 | DELETE1_SC_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_cache_port); |
---|
808 | DELETE1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port); |
---|
809 | DELETE1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port); |
---|
810 | DELETE1_SC_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_cache_port); |
---|
811 | DELETE1_SC_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_cache_port); |
---|
812 | |
---|
813 | DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory); |
---|
814 | DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory); |
---|
815 | DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory); |
---|
816 | DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory); |
---|
817 | #endif |
---|
818 | |
---|
819 | delete _Load_store_unit; |
---|
820 | delete _memory; |
---|
821 | delete _cache; |
---|
822 | #ifdef STATISTICS |
---|
823 | delete _parameters_statistics; |
---|
824 | #endif |
---|
825 | delete _param; |
---|
826 | } |
---|