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test2.cpp @ 78

Last change on this file since 78 was 78, checked in by rosiere, 16 years ago

Add :

Execute_loop (must be test systemC)
Prediction
- Direction : predifined scheme
- Branch Target Buffer
iFetch_unit
- ifetch_queue
- pc management
Decod_unit
- coming soon : support for custom operation
Rename_unit
- RAT
- Free_list
- Dependence RAW check
- Load store unit pointer
New Environnement (hierarchy_memory will remove in a next version)

Modif :

Manage Custom Operation
All component in execute_loop to use the new statistics management

Not Finish :

Return Address Stack
Environnement

File size: 40.9 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include <queue>
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
11
12	#define CYCLE_MAX 1024
13
14	#define LABEL(str) \
15	{ \
16	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
17	} while(0)
18
19	#define SC_START(cycle_offset) \
20	do \
21	{ \
22	/cout << "SC_START (begin)" << endl;/ \
23	\
24	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
25	if (cycle_offset != 0) \
26	{ \
27	cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
28	} \
29	\
30	if (cycle_current > CYCLE_MAX) \
31	{ \
32	TEST_KO("Maximal cycles Reached"); \
33	} \
34	sc_start(cycle_offset); \
35	/cout << "SC_START (end )" << endl;/ \
36	} while(0)
37
38
39	//===================================================================={test}
40	void test2 (void)
41	{
42	std::string name = "Test_Load_store_queue_manual";
43
44	cout << "<" << name << "> : Simulation SystemC" << endl;
45
46
47	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
48	(
49	4, //_size_store_queue
50	4, //_size_load_queue
51	2, //_size_speculative_access_queue
52	2, //_nb_port_check
53	SPECULATIVE_LOAD_COMMIT, //_speculative_load
54	0, //_nb_bypass_memory
55	1, //_nb_context
56	1, //_nb_front_end
57	2, //_nb_ooo_engine
58	128,//_nb_packet
59	32, //_size_general_data
60	2 , //_size_special_data
61	64, //_nb_general_register
62	16 //_nb_special_register
63	);
64
65	#ifdef STATISTICS
66	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
67	#endif
68
69	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
70	#ifdef STATISTICS
71	_parameters_statistics,
72	#endif
73	_param);
74
75	#ifdef SYSTEMC
76	/*********************************************************************
77	* Déclarations des signaux
78	*********************************************************************/
79	string rename = "";
80
81	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
82	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
83
84	sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str());
85	sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str());
86	sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str());
87	sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str());
88	sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str());
89	sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str());
90	sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str());
91	sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str());
92	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
93	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
94	sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());
95	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str());
96	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str());
97	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str());
98	sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());
99	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());
100	sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str());
101	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());
102	sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());
103
104	sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
105	sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
106	sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
107	sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str());
108	sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str());
109	sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
110	// sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str());
111	sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str());
112	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());
113	sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
114	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());
115	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());
116	sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
117	sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());
118	sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());
119	sc_signal<Tcontrol_t > * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal<Tcontrol_t >(rename.c_str());
120	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_ADDRESS = new sc_signal<Tgeneral_data_t >(rename.c_str());
121
122	sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
123	sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
124	sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
125	sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
126	sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str());
127	sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str());
128	sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
129
130	sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
131	sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
132	sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
133	sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
134	sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
135	sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str());
136
137	sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory];
138	sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory];
139	sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory];
140	sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory];
141
142	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
143	{
144	out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str());
145	out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str());
146	out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
147	out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str());
148	}
149
150	/********************************************************
151	* Instanciation
152	********************************************************/
153
154	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
155
156	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
157	((_Load_store_unit->in_NRESET)) ((in_NRESET));
158
159	((_Load_store_unit-> in_MEMORY_IN_VAL ))(( in_MEMORY_IN_VAL ));
160	((_Load_store_unit->out_MEMORY_IN_ACK ))((out_MEMORY_IN_ACK ));
161	if (_param->_have_port_context_id)
162	((_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(( in_MEMORY_IN_CONTEXT_ID ));
163	if (_param->_have_port_front_end_id)
164	((_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(( in_MEMORY_IN_FRONT_END_ID ));
165	if (_param->_have_port_ooo_engine_id)
166	((_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(( in_MEMORY_IN_OOO_ENGINE_ID ));
167	if (_param->_have_port_packet_id)
168	((_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(( in_MEMORY_IN_PACKET_ID ));
169	((_Load_store_unit-> in_MEMORY_IN_OPERATION ))(( in_MEMORY_IN_OPERATION ));
170	((_Load_store_unit-> in_MEMORY_IN_TYPE ))(( in_MEMORY_IN_TYPE ));
171	((_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
172	if (_param->_have_port_load_queue_ptr)
173	((_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
174	((_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(( in_MEMORY_IN_HAS_IMMEDIAT ));
175	((_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(( in_MEMORY_IN_IMMEDIAT ));
176	((_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(( in_MEMORY_IN_DATA_RA ));
177	((_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(( in_MEMORY_IN_DATA_RB ));
178	((_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(( in_MEMORY_IN_DATA_RC ));
179	((_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(( in_MEMORY_IN_WRITE_RD ));
180	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(( in_MEMORY_IN_NUM_REG_RD ));
181	((_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(( in_MEMORY_IN_WRITE_RE ));
182	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(( in_MEMORY_IN_NUM_REG_RE ));
183
184	((_Load_store_unit->out_MEMORY_OUT_VAL ))((out_MEMORY_OUT_VAL ));
185	((_Load_store_unit-> in_MEMORY_OUT_ACK ))(( in_MEMORY_OUT_ACK ));
186	if (_param->_have_port_context_id)
187	((_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))((out_MEMORY_OUT_CONTEXT_ID ));
188	if (_param->_have_port_front_end_id)
189	((_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))((out_MEMORY_OUT_FRONT_END_ID ));
190	if (_param->_have_port_ooo_engine_id)
191	((_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))((out_MEMORY_OUT_OOO_ENGINE_ID ));
192	if (_param->_have_port_packet_id)
193	((_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))((out_MEMORY_OUT_PACKET_ID ));
194	// ((_Load_store_unit->out_MEMORY_OUT_OPERATION ))((out_MEMORY_OUT_OPERATION ));
195	((_Load_store_unit->out_MEMORY_OUT_TYPE ))((out_MEMORY_OUT_TYPE ));
196	((_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))((out_MEMORY_OUT_WRITE_RD ));
197	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))((out_MEMORY_OUT_NUM_REG_RD ));
198	((_Load_store_unit->out_MEMORY_OUT_DATA_RD ))((out_MEMORY_OUT_DATA_RD ));
199	((_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))((out_MEMORY_OUT_WRITE_RE ));
200	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))((out_MEMORY_OUT_NUM_REG_RE ));
201	((_Load_store_unit->out_MEMORY_OUT_DATA_RE ))((out_MEMORY_OUT_DATA_RE ));
202	((_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))((out_MEMORY_OUT_EXCEPTION ));
203	((_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))((out_MEMORY_OUT_NO_SEQUENCE ));
204	((_Load_store_unit->out_MEMORY_OUT_ADDRESS ))((out_MEMORY_OUT_ADDRESS ));
205
206	((_Load_store_unit->out_DCACHE_REQ_VAL ))((out_DCACHE_REQ_VAL ));
207	((_Load_store_unit-> in_DCACHE_REQ_ACK ))(( in_DCACHE_REQ_ACK ));
208	if (_param->_have_port_dcache_context_id)
209	((_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))((out_DCACHE_REQ_CONTEXT_ID));
210	((_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))((out_DCACHE_REQ_PACKET_ID ));
211	((_Load_store_unit->out_DCACHE_REQ_ADDRESS ))((out_DCACHE_REQ_ADDRESS ));
212	((_Load_store_unit->out_DCACHE_REQ_TYPE ))((out_DCACHE_REQ_TYPE ));
213	((_Load_store_unit->out_DCACHE_REQ_WDATA ))((out_DCACHE_REQ_WDATA ));
214
215	((_Load_store_unit-> in_DCACHE_RSP_VAL ))(( in_DCACHE_RSP_VAL ));
216	((_Load_store_unit->out_DCACHE_RSP_ACK ))((out_DCACHE_RSP_ACK ));
217	if (_param->_have_port_dcache_context_id)
218	((_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(( in_DCACHE_RSP_CONTEXT_ID));
219	((_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(( in_DCACHE_RSP_PACKET_ID ));
220	((_Load_store_unit-> in_DCACHE_RSP_RDATA ))(( in_DCACHE_RSP_RDATA ));
221	((_Load_store_unit-> in_DCACHE_RSP_ERROR ))(( in_DCACHE_RSP_ERROR ));
222
223	{
224	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
225	{
226	((_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))((out_BYPASS_MEMORY_VAL [i]));
227	if (_param->_have_port_ooo_engine_id)
228	((_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))((out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
229	((_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))((out_BYPASS_MEMORY_NUM_REG [i]));
230	((_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))((out_BYPASS_MEMORY_DATA [i]));
231	}
232	}
233	cout << "<" << name << "> Start Simulation ............" << endl;
234	Time * _time = new Time();
235
236	/********************************************************
237	* Simulation - Begin
238	********************************************************/
239
240	// Initialisation
241
242	const uint32_t seed = 0;
243	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
244
245	srand(seed);
246
247	const int32_t percent_transaction_memory_out = 100;
248	const int32_t percent_transaction_dcache = 100;
249	const uint32_t miss_rate = 0;
250	const uint32_t miss_penality = 0;
251
252	uint32_t nb_request_memory_out=0;
253
254	MemoryRequest_t tab_request [_param->_nb_packet];
255	priority_queue<MemoryRequest_t> fifo_request;
256
257	const uint32_t size_memory = 0x100;
258	// emulation of memory
259	Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, size_memory, _param->_size_general_data);
260	Cache_t * _cache = new Cache_t (miss_rate, miss_penality);
261
262	SC_START(0);
263
264	LABEL("Initialisation");
265
266	in_MEMORY_IN_VAL ->write(0);
267	in_MEMORY_OUT_ACK->write(0);
268	in_DCACHE_REQ_ACK->write(0);
269	in_DCACHE_RSP_VAL->write(0);
270
271	in_NRESET ->write(0);
272	SC_START(5);
273	in_NRESET ->write(5);
274
275	LABEL("Loop of Test");
276
277	try
278	{
279	LABEL("Structure's initialisation");
280
281	bool store_queue_use [_param->_size_store_queue];
282	uint32_t nb_store_slot_use = 0;
283	bool load_queue_use [_param->_size_load_queue ];
284
285	for (uint32_t i=0; i<_param->_size_store_queue; i++)
286	store_queue_use [i] = false;
287	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
288	load_queue_use [i] = false;
289
290
291	//--------------------------------------------------------------------------------------------------------------
292	// c c f o p o t s l i d d w n w
293	// y o r o a p y t o m a a r u r
294	// c n o o c e p o a m t t i m i
295	// l t n _ k r e r d e a a t _ t
296	// e e t e e a e _ d _ _ e r e
297	// x _ n t t _ p i r r _ _ _
298	// t e g _ i p t a a b r g s
299	// _ n i i o t r t d _ p
300	// i d n d n r _ r e
301	// d _ e _ w d c
302	// i _ w r _
303	// d i r i k
304	// d i t o
305	// t e
306	// e
307	//
308	tab_request[ 0].modif( 5,0,0,0, 0,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x10 ,0xdead1234,0,0,0);
309
310	tab_request[ 1].modif(10,0,0,0, 0,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
311
312	// READ 32b
313	tab_request[ 2].modif(12,0,0,0, 2,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,1,0,0xdead1234);
314	tab_request[ 3].modif(13,0,0,0, 3,OPERATION_MEMORY_LOAD_32_S ,TYPE_MEMORY,1,1,0x10 ,0x0 ,0x0 ,1,2,0,0xdead1234);
315
316	// READ 16b
317	tab_request[ 4].modif(14,0,0,0, 4,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,2,0x10 ,0x0 ,0x0 ,1,3,0,0x00001234);
318	tab_request[ 5].modif(15,0,0,0, 5,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,3,0x12 ,0x0 ,0x0 ,1,4,0,0x0000dead);
319	tab_request[ 6].modif(16,0,0,0, 6,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,5,0,0x00001234);
320	tab_request[ 7].modif(17,0,0,0, 7,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,1,0x12 ,0x0 ,0x0 ,1,6,0,0xffffdead);
321
322	// READ 8b
323	tab_request[ 8].modif(18,0,0,0, 8,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,7,0,0x00000034);
324	tab_request[ 9].modif(19,0,0,0, 9,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,8,0,0x00000012);
325	tab_request[10].modif(20,0,0,0,10,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,9,0,0x000000ad);
326	tab_request[11].modif(21,0,0,0,11,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,1,0,0x000000de);
327	tab_request[12].modif(22,0,0,0,12,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,2,0,0x00000034);
328	tab_request[13].modif(23,0,0,0,13,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,3,0,0x00000012);
329	tab_request[14].modif(24,0,0,0,14,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,4,0,0xffffffad);
330	tab_request[15].modif(25,0,0,0,15,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,5,0,0xffffffde);
331
332	// STORE 16b
333	tab_request[16].modif(30,0,0,0,16,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x20 ,0x0 ,0xffffabcd,0,0,0);
334	tab_request[17].modif(31,0,0,0,17,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x22 ,0x0 ,0xffffdcba,0,0,0);
335	tab_request[18].modif(35,0,0,0,18,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
336	tab_request[19].modif(36,0,0,0,19,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
337	tab_request[20].modif(40,0,0,0,20,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x20 ,0x0 ,0x0 ,1,0,0,0xdcbaabcd);
338
339	// STORE 8b and head / valid out order
340	tab_request[21].modif(50,0,0,0,21,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,3,0,0x1 ,0x4 ,0xffffff56,0,0,0);
341	tab_request[22].modif(55,0,0,0,22,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x1 ,0x0 ,0x0 ,0,0,0);
342	tab_request[23].modif(48,0,0,0,23,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,0,0,0x0 ,0x4 ,0xffffff78,0,0,0);
343	tab_request[24].modif(43,0,0,0,24,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
344	tab_request[25].modif(47,0,0,0,25,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,1,0,0x3 ,0x4 ,0xffffff12,0,0,0);
345	tab_request[26].modif(49,0,0,0,26,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
346	tab_request[27].modif(57,0,0,0,27,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x2 ,0x4 ,0xffffff34,0,0,0);
347	tab_request[28].modif(44,0,0,0,28,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
348	tab_request[29].modif(70,0,0,0,29,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x2 ,0x2 ,0x0 ,1,0,0,0x12345678);
349
350	// CHECK - with a store not present, store format is >=
351	tab_request[30].modif(180,0,0,0,30,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x30 ,0x21071981,0,0,0);
352	tab_request[31].modif(179,0,0,0,31,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
353	tab_request[32].modif(173,0,0,0,32,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x30 ,0x0 ,1,0,0,0x21071981);
354	tab_request[33].modif(174,0,0,0,33,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,3,0x0 ,0x30 ,0x0 ,1,0,0,0x00001981);
355	tab_request[34].modif(175,0,0,0,34,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,0,0x0 ,0x32 ,0x0 ,1,0,0,0x00002107);
356	tab_request[35].modif(176,0,0,0,35,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,0,1,0x0 ,0x31 ,0x0 ,1,0,0,0x00000019);
357
358	// CHECK - with a store not present, multiple store and format is different
359	tab_request[36].modif(200,0,0,0,36,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x40 ,0xffffffff,0,0,0);
360	tab_request[37].modif(200,0,0,0,37,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
361	tab_request[38].modif(220,0,0,0,38,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x0 ,0x42 ,0xbaba ,0,0,0);
362	tab_request[39].modif(245,0,0,0,39,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
363	tab_request[40].modif(224,0,0,0,40,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x0 ,0x42 ,0xbe ,0,0,0);
364	tab_request[41].modif(240,0,0,0,41,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
365	tab_request[42].modif(228,0,0,0,42,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0xf00d ,0,0,0);
366	tab_request[43].modif(235,0,0,0,43,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
367	tab_request[44].modif(210,0,0,0,44,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x40 ,0x0 ,1,0,0,0xbabef00d);
368	tab_request[45].modif(211,0,0,0,45,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,2,3,0x0 ,0x40 ,0x0 ,1,0,0,0xbabaffff);
369	tab_request[46].modif(212,0,0,0,46,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0x0 ,1,0,0,0xbabeffff);
370	tab_request[47].modif(213,0,0,0,47,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,3,1,0x0 ,0x42 ,0x0 ,1,0,0,0xffffffbe);
371
372
373	// CHECK - with different ooo_engine_id
374	tab_request[48].modif(300,0,0,0,48,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x0 ,0xdad1900d,0,0,0);
375	tab_request[49].modif(300,0,0,0,49,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
376	tab_request[50].modif(300,0,0,1,50,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x55508570,0,0,0);
377	tab_request[51].modif(300,0,0,1,51,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
378
379
380	tab_request[52].modif(320,0,0,0,52,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,2,0x0 ,0x2 ,0x0 ,1,0,0,0xffffdad1);
381	tab_request[53].modif(321,0,0,1,53,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,3,0x0 ,0x0 ,0x0 ,1,0,0,0xffff8570);
382
383
384	// with a little exception
385	tab_request[54].modif(330,0,0,1,54,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x0 ,0x0 ,0xffff6996,0,0,1);
386	tab_request[55].modif(340,0,0,1,55,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
387	tab_request[56].modif(322,0,0,1,56,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,1,0,0,0x00000069); // they are a bypass (because, the cpu go in exception handler ... load is not use)
388	tab_request[57].modif(350,0,0,1,57,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // the memory have not change
389
390
391	// multiple event
392	// * store : miss_spec and aligment, priority : miss_spec > aligment
393	// * load : miss_spec and aligment, priority : miss_spec > aligment
394	tab_request[58].modif(410,0,0,0,58,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,0,0,1);
395	tab_request[59].modif(415,0,0,0,59,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
396
397	tab_request[60].modif(430,0,0,0,60,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x0 ,0x0 ,1,0,0,0xdad1900d);
398	tab_request[61].modif(400,0,0,0,61,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,3,0x0 ,0x3 ,0x0 ,1,0,0); // miss_spec and alignment
399	tab_request[62].modif(450,0,0,0,62,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,1,0,0); // bus error and alignement
400	tab_request[63].modif(460,0,0,0,63,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,1,0x0 ,size_memory+1,0x0 ,1,0,0); // bus error and alignement
401
402
403
404	tab_request[64].modif(500,0,0,0,64,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,0,0,0); // bus error
405	tab_request[65].modif(505,0,0,0,65,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
406	tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // just to wait the dcache_rsp
407
408	const uint32_t nb_request = 64;//_param->_nb_packet;
409
410	for (uint32_t i=0; i<nb_request; i++)
411	{
412	std::cout << tab_request [i] << std::endl;
413	fifo_request.push(tab_request [i]);
414	}
415	LABEL("Simulation ...");
416
417	while (nb_request_memory_out < nb_request)
418	{
419	cout << "*********************************************" << endl;
420	cout << "Dump STORE_QUEUE_USE : " << endl;
421	cout << " use " << nb_store_slot_use << endl;
422	for (uint32_t i=0; i<_param->_size_store_queue; i++)
423	cout << " [" << i << "] " << store_queue_use [i] << endl;
424	cout << "Dump LOAD_QUEUE_USE : " << endl;
425	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
426	cout << " [" << i << "] " << load_queue_use [i] << endl;
427	cout << "*********************************************" << endl;
428
429
430	// *** MEMORY_IN ***
431
432	// memory_in_val depends of three factors :
433	// 1) request's fifo is not empty ?
434	// 2) the slot destination is free ?
435	// 3) The head of request's fifo can be issue : the number of cycle is more than current cycle
436
437	bool can_execute = false;
438
439	if (not fifo_request.empty())
440	{
441	can_execute = sc_simulation_time() >= fifo_request.top()._cycle;
442	if (is_operation_memory_store(fifo_request.top()._operation))
443	can_execute &= (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
444	else
445	can_execute &= not load_queue_use [fifo_request.top()._load_queue_ptr_write];
446	}
447	in_MEMORY_IN_VAL ->write(can_execute);
448
449	if (not fifo_request.empty())
450	{
451	if (_param->_have_port_context_id)
452	in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );
453	if (_param->_have_port_front_end_id)
454	in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id );
455	if (_param->_have_port_ooo_engine_id)
456	in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id );
457	if (_param->_have_port_packet_id)
458	in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );
459	in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );
460	in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );
461	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
462	if (_param->_have_port_load_queue_ptr)
463	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
464	in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );
465	in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );
466	in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );
467	// in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );
468	in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );
469	}
470	in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
471
472	// *** DCACHE_REQ ***
473	in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
474
475	// *** DCACHE_RSP ***
476	bool have_rsp = _cache->have_rsp ();
477	in_DCACHE_RSP_VAL->write(have_rsp);
478
479	if (have_rsp)
480	{
481	in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
482	in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
483	in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata );
484	in_DCACHE_RSP_ERROR ->write(_cache->front()._error );
485	}
486
487	SC_START(0);
488
489	LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
490	if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
491	{
492	Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID->read();
493
494	LABEL(" * Accepted MEMORY_IN : " + toString(packet_id));
495	cout << fifo_request.top();
496
497	if (is_operation_memory_store(fifo_request.top()._operation))
498	{
499	if (not is_operation_memory_store_head(fifo_request.top()._operation))
500	{
501	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
502	nb_store_slot_use ++;
503	}
504	}
505	else
506	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
507
508	fifo_request.pop();
509	}
510
511	LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
512	if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())
513	{
514	Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read();
515
516	LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id));
517
518	if (is_operation_memory_store(tab_request[packet_id]._operation))
519	{
520	store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
521	nb_store_slot_use --;
522	nb_request_memory_out +=2;
523
524	}
525	else
526	{
527	if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
528	{
529	nb_request_memory_out ++;
530
531	load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false;
532	}
533	else
534	{
535	std::cout << "seth - have a load_speculative." << std::endl;
536	tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD->read() != tab_request[packet_id]._data_wait);
537	tab_request[packet_id]._previous_load_speculative = 1;
538	}
539	}
540
541	std::cout << "kane - nb_request_memory_out : " << nb_request_memory_out << std::endl;
542
543	// a lot of test
544	TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id );
545	TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id );
546	TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
547	TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
548	// TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation );
549	TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY );
550
551	if (is_operation_memory_load (tab_request[packet_id]._operation))
552	{
553	TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd );
554	}
555
556	Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
557
558	bool error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))));
559	bool berr = (address >= size_memory);
560	Texception_t exception = out_MEMORY_OUT_EXCEPTION->read();
561
562	if (is_operation_memory_store(tab_request[packet_id]._operation))
563	{
564	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 0);
565
566	// store.
567	// prioritary : miss_speculation > aligmnent > DBERR
568
569	bool test_result_ko = false;
570
571	if (tab_request[packet_id]._write_spec_ko)
572	{
573	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
574	}
575	else
576	if (error_alignment)
577	{
578	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
579	test_result_ko = true;
580	}
581	else
582	if (berr)
583	{
584	// TODO NOT SUPPORTED
585	// TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
586
587	//test_result_ko = true;
588	}
589	else
590	{
591	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
592	}
593	// In all case : test data
594	if (test_result_ko)
595	{
596	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address);
597	}
598	}
599	else
600	{
601	// load
602	// prioritary : miss_speculation > aligmnent > DBERR
603
604	bool is_load = is_operation_memory_load(tab_request[packet_id]._operation);
605
606	if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
607	{
608	bool test_result_ko = false;
609
610	if (tab_request[packet_id]._write_spec_ko)
611	{
612	// IS A LOAD :D
613	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
614	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), 1);
615	}
616	else
617	if (error_alignment)
618	{
619	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
620	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), is_load);
621	test_result_ko = true;
622	}
623	else
624	if (berr)
625	{
626	TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
627	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load);
628	test_result_ko = true;
629	}
630	else
631	{
632	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
633	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load and not tab_request[packet_id]._previous_load_speculative);
634	}
635	// In all case : test data
636	if (test_result_ko)
637	{
638	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address);
639	}
640	else
641	{
642	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), tab_request[packet_id]._data_wait);
643	}
644	}
645	else
646	{
647	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 1);
648	}
649	}
650	}
651
652	LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
653	if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read())
654	{
655	Tcontext_t context_id;
656	Tpacket_t packet_id ;
657	Tdcache_address_t address = out_DCACHE_REQ_ADDRESS->read();
658	Tdcache_data_t rdata;
659	Tdcache_error_t error = 0;
660	if (_param->_have_port_dcache_context_id)
661	context_id = out_DCACHE_REQ_CONTEXT_ID->read();
662	else
663	context_id = 0;
664
665	packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
666
667	LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id));
668
669	if (address >= size_memory)
670	{
671	// Bus error
672	error = DCACHE_ERROR_BUS_ERROR;
673	rdata = address; // convention : cache return the address fautive !
674	}
675	else
676	{
677	rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
678	LABEL(" * rdata : " + toString(rdata));
679	}
680
681	// test type : send or not a respons !
682	if ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_SYNCHRONIZATION) or
683	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD) or
684	((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_8 ) or
685	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_16) or
686	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_32) or
687	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_64) )))
688	{
689	LABEL(" * have_dcache_rsp");
690
691	_cache->push (context_id,
692	out_DCACHE_REQ_PACKET_ID ->read(),
693	rdata,
694	error);
695	}
696	}
697
698	LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read()));
699	if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
700	{
701	_cache->pop();
702	}
703
704	_cache->end_cycle();
705
706	SC_START(1);
707	}
708	}
709	catch (morpheo::ErrorMorpheo & error)
710	{
711	_memory->trace();
712	throw (error);
713	}
714
715	_memory->trace();
716
717
718	/********************************************************
719	* Simulation - End
720	********************************************************/
721
722	TEST_OK ("End of Simulation");
723	delete _time;
724	cout << "<" << name << "> ............ Stop Simulation" << endl;
725
726	delete in_CLOCK;
727	delete in_NRESET;
728
729	delete in_MEMORY_IN_VAL ;
730	delete out_MEMORY_IN_ACK ;
731	delete in_MEMORY_IN_CONTEXT_ID ;
732	delete in_MEMORY_IN_FRONT_END_ID ;
733	delete in_MEMORY_IN_OOO_ENGINE_ID ;
734	delete in_MEMORY_IN_PACKET_ID ;
735	delete in_MEMORY_IN_OPERATION ;
736	delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
737	delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
738	delete in_MEMORY_IN_HAS_IMMEDIAT;
739	delete in_MEMORY_IN_IMMEDIAT ;
740	delete in_MEMORY_IN_DATA_RA ;
741	delete in_MEMORY_IN_DATA_RB ;
742	delete in_MEMORY_IN_DATA_RC ;
743	delete in_MEMORY_IN_WRITE_RD ;
744	delete in_MEMORY_IN_NUM_REG_RD ;
745	delete in_MEMORY_IN_WRITE_RE ;
746	delete in_MEMORY_IN_NUM_REG_RE ;
747
748	delete out_MEMORY_OUT_VAL ;
749	delete in_MEMORY_OUT_ACK ;
750	delete out_MEMORY_OUT_CONTEXT_ID;
751	delete out_MEMORY_OUT_FRONT_END_ID;
752	delete out_MEMORY_OUT_OOO_ENGINE_ID;
753	delete out_MEMORY_OUT_PACKET_ID ;
754	// delete out_MEMORY_OUT_OPERATION ;
755	delete out_MEMORY_OUT_TYPE ;
756	delete out_MEMORY_OUT_WRITE_RD ;
757	delete out_MEMORY_OUT_NUM_REG_RD;
758	delete out_MEMORY_OUT_DATA_RD ;
759	delete out_MEMORY_OUT_WRITE_RE ;
760	delete out_MEMORY_OUT_NUM_REG_RE;
761	delete out_MEMORY_OUT_DATA_RE ;
762	delete out_MEMORY_OUT_EXCEPTION ;
763	delete out_MEMORY_OUT_NO_SEQUENCE;
764	delete out_MEMORY_OUT_ADDRESS ;
765
766	delete out_DCACHE_REQ_VAL ;
767	delete in_DCACHE_REQ_ACK ;
768	delete out_DCACHE_REQ_CONTEXT_ID;
769	delete out_DCACHE_REQ_PACKET_ID ;
770	delete out_DCACHE_REQ_ADDRESS ;
771	delete out_DCACHE_REQ_TYPE ;
772	delete out_DCACHE_REQ_WDATA ;
773
774	delete in_DCACHE_RSP_VAL ;
775	delete out_DCACHE_RSP_ACK ;
776	delete in_DCACHE_RSP_CONTEXT_ID;
777	delete in_DCACHE_RSP_PACKET_ID ;
778	delete in_DCACHE_RSP_RDATA ;
779	delete in_DCACHE_RSP_ERROR ;
780
781	{
782	delete [] out_BYPASS_MEMORY_VAL ;
783	delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
784	delete [] out_BYPASS_MEMORY_NUM_REG ;
785	delete [] out_BYPASS_MEMORY_DATA ;
786	}
787	#endif
788
789	delete _Load_store_unit;
790	delete _memory;
791	delete _cache;
792	#ifdef STATISTICS
793	delete _parameters_statistics;
794	#endif
795	delete _param;
796	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp @ 78

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