[59] | 1 | #ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Load_store_unit_h |
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| 2 | #define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Load_store_unit_h |
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| 3 | |
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| 4 | /* |
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| 5 | * $Id$ |
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| 6 | * |
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| 7 | * [ Description ] |
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| 8 | * |
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[62] | 9 | * Ce composant peut être amélioré en placant deux ptr de lecture au lieu d'un : un pour l'accès au cache et un pour le commit |
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[59] | 10 | */ |
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| 11 | |
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| 12 | #ifdef SYSTEMC |
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| 13 | #include "systemc.h" |
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| 14 | #endif |
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| 15 | |
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| 16 | #include <iostream> |
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| 17 | #include "Common/include/ToString.h" |
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| 18 | #include "Common/include/Debug.h" |
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| 19 | |
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| 20 | #include "Behavioural/Generic/Queue_Control/include/Queue_Control.h" |
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| 21 | |
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| 22 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h" |
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| 23 | #include "Behavioural/Generic/Queue_Control/include/Queue_Control.h" |
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| 24 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h" |
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| 25 | #ifdef STATISTICS |
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[71] | 26 | #include "Behavioural/include/Stat.h" |
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[59] | 27 | #endif |
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| 28 | #include "Behavioural/include/Component.h" |
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| 29 | #ifdef VHDL |
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| 30 | #include "Behavioural/include/Vhdl.h" |
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| 31 | #endif |
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| 32 | |
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| 33 | namespace morpheo { |
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| 34 | namespace behavioural { |
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| 35 | namespace core { |
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| 36 | namespace multi_execute_loop { |
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| 37 | namespace execute_loop { |
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| 38 | namespace multi_execute_unit { |
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| 39 | namespace execute_unit { |
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| 40 | namespace load_store_unit { |
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| 41 | |
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| 42 | |
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| 43 | class Load_store_unit |
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| 44 | #if SYSTEMC |
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| 45 | : public sc_module |
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| 46 | #endif |
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| 47 | { |
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| 48 | // -----[ fields ]---------------------------------------------------- |
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| 49 | // Parameters |
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[75] | 50 | protected : const std::string _name; |
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[59] | 51 | |
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| 52 | protected : const Parameters * _param; |
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| 53 | |
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| 54 | #ifdef STATISTICS |
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[71] | 55 | private : Stat * _stat; |
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| 56 | |
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| 57 | private : counter_t * _stat_use_store_queue; |
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| 58 | private : counter_t * _stat_use_load_queue; |
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| 59 | private : counter_t * _stat_use_speculative_access_queue; |
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| 60 | |
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| 61 | private : counter_t * _stat_average_use_store_queue; |
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| 62 | private : counter_t * _stat_average_use_load_queue; |
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| 63 | private : counter_t * _stat_average_use_speculative_access_queue; |
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| 64 | |
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| 65 | private : counter_t * _stat_percent_use_store_queue; |
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| 66 | private : counter_t * _stat_percent_use_load_queue; |
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| 67 | private : counter_t * _stat_percent_use_speculative_access_queue; |
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| 68 | |
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| 69 | // private : counter_t * _stat_nb_load_miss_speculation; |
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| 70 | // private : counter_t * _stat_nb_head_ko; |
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| 71 | |
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| 72 | // private : counter_t * _stat_nb_inst_load; |
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| 73 | // private : counter_t * _stat_nb_inst_store; |
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| 74 | // private : counter_t * _stat_nb_inst_lock; |
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| 75 | // private : counter_t * _stat_nb_inst_prefetch; |
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| 76 | // private : counter_t * _stat_nb_inst_invalid; |
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| 77 | // private : counter_t * _stat_nb_inst_flush; |
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| 78 | // private : counter_t * _stat_nb_inst_sync; |
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[59] | 79 | #endif |
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| 80 | |
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| 81 | public : Component * _component; |
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| 82 | private : Interfaces * _interfaces; |
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| 83 | |
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| 84 | #ifdef SYSTEMC |
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| 85 | // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 86 | // Interface |
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| 87 | public : SC_CLOCK * in_CLOCK ; |
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| 88 | public : SC_IN (Tcontrol_t) * in_NRESET ; |
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| 89 | |
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| 90 | // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 91 | public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_VAL ; |
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| 92 | public : SC_OUT(Tcontrol_t ) * out_MEMORY_IN_ACK ; |
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| 93 | public : SC_IN (Tcontext_t ) * in_MEMORY_IN_CONTEXT_ID ; |
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[71] | 94 | public : SC_IN (Tcontext_t ) * in_MEMORY_IN_FRONT_END_ID; |
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| 95 | public : SC_IN (Tcontext_t ) * in_MEMORY_IN_OOO_ENGINE_ID; |
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[59] | 96 | public : SC_IN (Tpacket_t ) * in_MEMORY_IN_PACKET_ID ; |
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| 97 | public : SC_IN (Toperation_t ) * in_MEMORY_IN_OPERATION ; |
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[76] | 98 | //public : SC_IN (Ttype_t ) * in_MEMORY_IN_TYPE ; |
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[59] | 99 | public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; |
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[76] | 100 | public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; |
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[59] | 101 | //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_HAS_IMMEDIAT; |
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| 102 | public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_IMMEDIAT ; // memory address |
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| 103 | public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RA ; // memory address |
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| 104 | public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RB ; // data (store) |
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| 105 | //public : SC_IN (Tspecial_data_t ) * in_MEMORY_IN_DATA_RC ; |
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[71] | 106 | //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RD ; // = (operation==load) |
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[59] | 107 | public : SC_IN (Tgeneral_address_t) * in_MEMORY_IN_NUM_REG_RD ; // destination (load) |
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| 108 | //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RE ; |
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| 109 | //public : SC_IN (Tspecial_address_t) * in_MEMORY_IN_NUM_REG_RE ; |
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| 110 | |
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| 111 | // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 112 | public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_VAL ; |
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| 113 | public : SC_IN (Tcontrol_t ) * in_MEMORY_OUT_ACK ; |
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| 114 | public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_CONTEXT_ID; |
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[71] | 115 | public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_FRONT_END_ID; |
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| 116 | public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_OOO_ENGINE_ID; |
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[59] | 117 | public : SC_OUT(Tpacket_t ) * out_MEMORY_OUT_PACKET_ID ; |
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| 118 | public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RD ; // = (operation==load) |
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| 119 | public : SC_OUT(Tgeneral_address_t) * out_MEMORY_OUT_NUM_REG_RD; // destination (load) |
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| 120 | public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_DATA_RD ; // data (load) |
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| 121 | //public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RE ; |
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| 122 | //public : SC_OUT(Tspecial_address_t) * out_MEMORY_OUT_NUM_REG_RE; |
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| 123 | //public : SC_OUT(Tspecial_data_t ) * out_MEMORY_OUT_DATA_RE ; |
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| 124 | public : SC_OUT(Texception_t ) * out_MEMORY_OUT_EXCEPTION ; |
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| 125 | |
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| 126 | // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 127 | public : SC_OUT(Tcontrol_t ) * out_DCACHE_REQ_VAL ; |
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| 128 | public : SC_IN (Tcontrol_t ) * in_DCACHE_REQ_ACK ; |
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| 129 | public : SC_OUT(Tcontext_t ) * out_DCACHE_REQ_CONTEXT_ID; |
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| 130 | public : SC_OUT(Tpacket_t ) * out_DCACHE_REQ_PACKET_ID ; |
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| 131 | public : SC_OUT(Tdcache_address_t ) * out_DCACHE_REQ_ADDRESS ; |
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| 132 | public : SC_OUT(Tdcache_type_t ) * out_DCACHE_REQ_TYPE ; |
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| 133 | public : SC_OUT(Tdcache_data_t ) * out_DCACHE_REQ_WDATA ; |
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| 134 | |
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| 135 | // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 136 | public : SC_IN (Tcontrol_t ) * in_DCACHE_RSP_VAL ; |
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| 137 | public : SC_OUT(Tcontrol_t ) * out_DCACHE_RSP_ACK ; |
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| 138 | public : SC_IN (Tcontext_t ) * in_DCACHE_RSP_CONTEXT_ID; |
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| 139 | public : SC_IN (Tpacket_t ) * in_DCACHE_RSP_PACKET_ID ; |
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| 140 | public : SC_IN (Tdcache_data_t ) * in_DCACHE_RSP_RDATA ; |
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| 141 | public : SC_IN (Tdcache_error_t ) * in_DCACHE_RSP_ERROR ; |
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| 142 | |
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| 143 | // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 144 | public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ; |
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[71] | 145 | public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; |
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[59] | 146 | public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_MEMORY_NUM_REG ; |
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| 147 | public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ; |
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| 148 | |
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| 149 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 150 | protected : Tstore_queue_entry_t * _store_queue; |
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| 151 | protected : Tload_queue_entry_t * _load_queue; |
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| 152 | protected : Tspeculative_access_queue_entry_t * _speculative_access_queue; |
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| 153 | protected : morpheo::behavioural::generic::queue_control::Queue_Control * _speculative_access_queue_control; |
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| 154 | |
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| 155 | // function pointer |
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| 156 | public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_transition ) (void); |
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| 157 | public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMoore ) (void); |
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| 158 | public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_dcache) (void); |
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| 159 | public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_insert) (void); |
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| 160 | public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_retire) (void); |
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| 161 | |
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| 162 | // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 163 | |
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| 164 | // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 165 | |
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[62] | 166 | // Registers |
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[71] | 167 | public : Tlsq_ptr_t reg_STORE_QUEUE_PTR_READ; |
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| 168 | //public : Tlsq_ptr_t reg_LOAD_QUEUE_PTR_READ ; |
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| 169 | public : Tlsq_ptr_t reg_LOAD_QUEUE_CHECK_PRIORITY ; |
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[59] | 170 | |
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[62] | 171 | // signal |
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[71] | 172 | public : Tlsq_ptr_t internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ ; |
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| 173 | |
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[59] | 174 | private : Tcontrol_t internal_MEMORY_IN_ACK; |
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| 175 | private : Tcontrol_t internal_MEMORY_OUT_VAL; |
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| 176 | private : Tselect_queue_t internal_MEMORY_OUT_SELECT_QUEUE; |
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[71] | 177 | public : Tlsq_ptr_t internal_MEMORY_OUT_PTR; |
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[62] | 178 | |
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[71] | 179 | private : Tcontrol_t internal_DCACHE_RSP_ACK; |
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[62] | 180 | private : Tcontrol_t internal_DCACHE_REQ_VAL; |
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| 181 | private : Tselect_queue_t internal_DCACHE_REQ_SELECT_QUEUE; |
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[59] | 182 | #endif |
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| 183 | |
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| 184 | // -----[ methods ]--------------------------------------------------- |
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| 185 | |
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| 186 | #ifdef SYSTEMC |
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| 187 | SC_HAS_PROCESS (Load_store_unit); |
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| 188 | #endif |
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| 189 | public : Load_store_unit |
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| 190 | ( |
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| 191 | #ifdef SYSTEMC |
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| 192 | sc_module_name name, |
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| 193 | #else |
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[75] | 194 | std::string name, |
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[59] | 195 | #endif |
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| 196 | #ifdef STATISTICS |
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| 197 | morpheo::behavioural::Parameters_Statistics * param_statistics, |
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| 198 | #endif |
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| 199 | Parameters * param ); |
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| 200 | public : ~Load_store_unit (void); |
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| 201 | |
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| 202 | #ifdef SYSTEMC |
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| 203 | private : void allocation (void); |
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| 204 | private : void deallocation (void); |
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| 205 | |
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| 206 | public : void transition (void); |
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| 207 | public : void genMoore (void); |
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| 208 | public : void genMealy_dcache (void); |
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| 209 | public : void genMealy_insert (void); |
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| 210 | public : void genMealy_retire (void); |
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| 211 | |
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| 212 | public : void function_speculative_load_commit_transition (void); |
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| 213 | public : void function_speculative_load_commit_genMoore (void); |
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| 214 | public : void function_speculative_load_commit_genMealy_dcache (void); |
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| 215 | public : void function_speculative_load_commit_genMealy_insert (void); |
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| 216 | public : void function_speculative_load_commit_genMealy_retire (void); |
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| 217 | #endif |
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[71] | 218 | |
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[59] | 219 | #ifdef STATISTICS |
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[71] | 220 | public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics); |
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[59] | 221 | #endif |
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| 222 | |
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| 223 | #if VHDL |
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| 224 | public : void vhdl (void); |
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| 225 | private : void vhdl_declaration (Vhdl * & vhdl); |
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| 226 | private : void vhdl_body (Vhdl * & vhdl); |
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| 227 | #endif |
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| 228 | |
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[71] | 229 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 230 | private : void end_cycle (void); |
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[59] | 231 | #endif |
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| 232 | }; |
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| 233 | |
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| 234 | }; // end namespace load_store_unit |
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| 235 | }; // end namespace execute_unit |
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| 236 | }; // end namespace multi_execute_unit |
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| 237 | }; // end namespace execute_loop |
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| 238 | }; // end namespace multi_execute_loop |
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| 239 | }; // end namespace core |
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| 240 | |
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| 241 | }; // end namespace behavioural |
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| 242 | }; // end namespace morpheo |
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| 243 | |
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| 244 | #endif |
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