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Load_store_unit_allocation.cpp @ 138

Last change on this file since 138 was 138, checked in by rosiere, 14 years ago
1) add counters_t type for interface 2) fix in check load in load_store_unit 3) add parameters (but not yet implemented) 4) change environment and add script (distcc_env.sh ...) 5) add warning if an unser change rename flag with l.mtspr instruction 6) ...
Property svn:keywords set to `Id`
File size: 11.9 KB

Rev	Line
[59]	1	#ifdef SYSTEMC
	2	/*
	3	* $Id: Load_store_unit_allocation.cpp 138 2010-05-12 17:34:01Z rosiere $
	4	*
[88]	5	* [ Description ]
[59]	6	*
	7	*/
	8
	9	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
[88]	10	#include "Behavioural/include/Allocation.h"
[124]	11	#include "Common/include/Filename.h"
[59]	12
	13	namespace morpheo {
	14	namespace behavioural {
	15	namespace core {
	16	namespace multi_execute_loop {
	17	namespace execute_loop {
	18	namespace multi_execute_unit {
	19	namespace execute_unit {
	20	namespace load_store_unit {
	21
	22
	23
	24	#undef FUNCTION
	25	#define FUNCTION "Load_store_unit::allocation"
	26	void Load_store_unit::allocation (void)
	27	{
	28	log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
	29
[82]	30	_component = new Component (_usage);
[59]	31
	32	Entity * entity = _component->set_entity (_name
	33	,"Load_store_unit"
	34	#ifdef POSITION
	35	,COMBINATORY
	36	#endif
	37	);
	38
	39	_interfaces = entity->set_interfaces();
	40
[88]	41	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	42	{
	43	Interface * interface = _interfaces->set_interface(""
	44	#ifdef POSITION
	45	,IN
	46	,SOUTH,
[88]	47	_("Generalist interface")
[59]	48	#endif
	49	);
	50
	51	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
	52	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
	53	}
[88]	54
	55	// ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	56	{
[112]	57	ALLOC1_INTERFACE_BEGIN("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory);
[59]	58
[88]	59	ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL ,VAL);
	60	ALLOC1_VALACK_OUT(out_MEMORY_IN_ACK ,ACK);
	61	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );
	62	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id );
	63	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id );
	64	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr );
	65	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation );
	66	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type );
[136]	67	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CANCEL ,"cancel" ,Tcontrol_t ,1 );
[88]	68	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr );
[122]	69	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr );
	70	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_EMPTY ,"store_queue_empty" ,Tcontrol_t ,1);
[88]	71	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr );
	72	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 );
	73	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data );
	74	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data );
	75	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data );
	76	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data );
	77	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 );
[97]	78	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register );
[88]	79	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 );
[97]	80	ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register );
[112]	81
	82	ALLOC1_INTERFACE_END(_param->_nb_inst_memory);
[59]	83	}
	84
[88]	85	// ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	86	{
[112]	87	ALLOC1_INTERFACE_BEGIN("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory);
[59]	88
[88]	89	ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL ,VAL);
	90	ALLOC1_VALACK_IN ( in_MEMORY_OUT_ACK ,ACK);
	91	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );
	92	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id );
	93	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OOO_ENGINE_ID,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id );
	94	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr );
	95	// ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation );
[97]	96	// ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type );
[136]	97	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CANCEL ,"cancel" ,Tcontrol_t ,1 );
[88]	98	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 );
	99	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register );
	100	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data );
	101	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 );
[97]	102	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register );
	103	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data );
[88]	104	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception );
	105	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 );
[97]	106	ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address);
[112]	107
	108	ALLOC1_INTERFACE_END(_param->_nb_inst_memory);
[59]	109	}
	110
[88]	111	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	112	{
[112]	113	ALLOC1_INTERFACE_BEGIN("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port);
[59]	114
[88]	115	ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL);
	116	ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,ACK);
	117	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id );
	118	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id );
	119	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t,_param->_size_general_data);
	120	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type );
	121	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data);
[112]	122
	123	ALLOC1_INTERFACE_END(_param->_nb_cache_port);
[59]	124	}
[88]	125
	126	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	127	{
[112]	128	ALLOC1_INTERFACE_BEGIN("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port);
[59]	129
[88]	130	ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL);
	131	ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,ACK);
	132	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id );
	133	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id );
	134	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data);
	135	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error);
[112]	136
	137	ALLOC1_INTERFACE_END(_param->_nb_cache_port);
[59]	138	}
[88]	139	// ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	140
[88]	141	{
[112]	142	ALLOC1_INTERFACE_BEGIN("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory);
[59]	143
[88]	144	ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL ,VAL);
	145	ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t , _param->_size_ooo_engine_id );
	146	ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t, _param->_size_general_register);
	147	ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t , _param->_size_general_data );
[112]	148
	149	ALLOC1_INTERFACE_END(_param->_nb_bypass_memory);
[88]	150	}
[59]	151
[88]	152	// ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[117]	153	if (usage_is_set(_usage,USE_SYSTEMC))
	154	{
	155	_speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue);
[88]	156
[117]	157	ALLOC1(_store_queue ,Tstore_queue_entry_t ,_param->_size_store_queue);
	158	ALLOC1(_load_queue ,Tload_queue_entry_t ,_param->_size_load_queue);
	159	ALLOC1(_speculative_access_queue,Tspeculative_access_queue_entry_t,_param->_size_speculative_access_queue);
[88]	160
[117]	161	ALLOC1(reg_STORE_QUEUE_NB_CHECK ,Tlsq_ptr_t ,_param->_size_store_queue);
[138]	162	// ALLOC1(reg_STORE_QUEUE_INVALID ,Tcontrol_t ,_param->_size_store_queue);
[88]	163
[117]	164	// ALLOC1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,Tlsq_ptr_t ,_param->_nb_cache_port);
	165
	166	// ALLOC1(internal_MEMORY_IN_ACK ,Tcontrol_t ,_param->_nb_inst_memory);
	167	// ALLOC1(internal_MEMORY_OUT_VAL ,Tcontrol_t ,_param->_nb_inst_memory);
	168	// ALLOC1(internal_MEMORY_OUT_SELECT_QUEUE ,Tselect_queue_t,_param->_nb_inst_memory);
	169	// ALLOC1(internal_MEMORY_OUT_PTR ,Tlsq_ptr_t ,_param->_nb_inst_memory);
	170
	171	// ALLOC1(internal_DCACHE_RSP_ACK ,Tcontrol_t ,_param->_nb_cache_port );
	172	// ALLOC1(internal_DCACHE_REQ_VAL ,Tcontrol_t ,_param->_nb_cache_port );
	173	// ALLOC1(internal_DCACHE_REQ_SELECT_QUEUE ,Tselect_queue_t,_param->_nb_cache_port );
	174	}
	175
[88]	176	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	177
[59]	178	#ifdef POSITION
[88]	179	if (usage_is_set(_usage,USE_POSITION))
	180	_component->generate_file();
[59]	181	#endif
	182
[124]	183	#if defined(DEBUG) and defined(DEBUG_Load_store_unit) and (DEBUG_Load_store_unit == true)
[134]	184	if (log_file_generate)
	185	{
	186	directory_init ();
	187
	188	memory_log_file = new std::ofstream [_param->_nb_thread];
	189	for (uint32_t i=0; i<_param->_nb_thread; ++i)
	190	if (_param->_num_thread_valid [i])
	191	{
	192
	193	std::string filename = morpheo::filename(MORPHEO_LOG,
	194	"Memory_access-thread_"+toString(i),
	195	"",
	196	"log",
	197	_simulation_file_with_date,
	198	_simulation_file_with_pid ,
	199	true);
	200
	201	memory_log_file [i].open(filename.c_str() ,std::ios::out \| std::ios::trunc);
	202	}
	203	}
[124]	204	#endif
	205
[59]	206	log_printf(FUNC,Load_store_unit,FUNCTION,"End");
	207	};
	208
	209	}; // end namespace load_store_unit
	210	}; // end namespace execute_unit
	211	}; // end namespace multi_execute_unit
	212	}; // end namespace execute_loop
	213	}; // end namespace multi_execute_loop
	214	}; // end namespace core
	215
	216	}; // end namespace behavioural
	217	}; // end namespace morpheo
	218	#endif

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp @ 138

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