Changeset 117 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp

Timestamp:

May 16, 2009, 4:42:39 PM (15 years ago)

Author:

rosiere

Message:

1) Platforms : add new organization for test
2) Load_Store_Unit : add array to count nb_check in store_queue
3) Issue_queue and Core_Glue : rewrite the issue network
4) Special_Register_Unit : add reset value to register CID
5) Softwares : add multicontext test
6) Softwares : add SPECINT
7) Softwares : add MiBench?
7) Read_queue : inhib access for r0
8) Change Core_Glue (network) - dont yet support priority and load balancing scheme

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp

@@ -146 +146 @@
 
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {
+        _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue);
 
-//     internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port];
+        ALLOC1(_store_queue             ,Tstore_queue_entry_t             ,_param->_size_store_queue);
+        ALLOC1(_load_queue              ,Tload_queue_entry_t              ,_param->_size_load_queue);
+        ALLOC1(_speculative_access_queue,Tspeculative_access_queue_entry_t,_param->_size_speculative_access_queue);
 
-//     internal_MEMORY_IN_ACK           = new Tcontrol_t      [_param->_nb_inst_memory];
-//     internal_MEMORY_OUT_VAL          = new Tcontrol_t      [_param->_nb_inst_memory];
-//     internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory];
-//     internal_MEMORY_OUT_PTR          = new Tlsq_ptr_t      [_param->_nb_inst_memory];
-    
-//     internal_DCACHE_RSP_ACK          = new Tcontrol_t      [_param->_nb_cache_port];
-//     internal_DCACHE_REQ_VAL          = new Tcontrol_t      [_param->_nb_cache_port];
-//     internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port];
+        ALLOC1(reg_STORE_QUEUE_NB_CHECK                  ,Tlsq_ptr_t     ,_param->_size_store_queue);
+
+//      ALLOC1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,Tlsq_ptr_t     ,_param->_nb_cache_port);
+
+//      ALLOC1(internal_MEMORY_IN_ACK                    ,Tcontrol_t     ,_param->_nb_inst_memory);
+//      ALLOC1(internal_MEMORY_OUT_VAL                   ,Tcontrol_t     ,_param->_nb_inst_memory);
+//      ALLOC1(internal_MEMORY_OUT_SELECT_QUEUE          ,Tselect_queue_t,_param->_nb_inst_memory);
+//      ALLOC1(internal_MEMORY_OUT_PTR                   ,Tlsq_ptr_t     ,_param->_nb_inst_memory);
+                                                         
+//      ALLOC1(internal_DCACHE_RSP_ACK                   ,Tcontrol_t     ,_param->_nb_cache_port );
+//      ALLOC1(internal_DCACHE_REQ_VAL                   ,Tcontrol_t     ,_param->_nb_cache_port );
+//      ALLOC1(internal_DCACHE_REQ_SELECT_QUEUE          ,Tselect_queue_t,_param->_nb_cache_port );
+      }
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
@@ -164 +174 @@
       _component->generate_file();
 #endif
-
-    _store_queue                      = new Tstore_queue_entry_t              [_param->_size_store_queue];
-    _load_queue                       = new Tload_queue_entry_t               [_param->_size_load_queue];
-    _speculative_access_queue         = new Tspeculative_access_queue_entry_t [_param->_size_speculative_access_queue];
-    _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue);
 
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");