[59] | 1 | #ifdef SYSTEMC |
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| 2 | //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 3 | /* |
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| 4 | * $Id: Load_store_unit_function_speculative_load_commit_genMoore.cpp 117 2009-05-16 14:42:39Z rosiere $ |
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| 5 | * |
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[88] | 6 | * [ Description ] |
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[59] | 7 | * |
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| 8 | */ |
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| 9 | |
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| 10 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" |
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| 11 | |
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| 12 | namespace morpheo { |
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| 13 | namespace behavioural { |
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| 14 | namespace core { |
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| 15 | namespace multi_execute_loop { |
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| 16 | namespace execute_loop { |
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| 17 | namespace multi_execute_unit { |
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| 18 | namespace execute_unit { |
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| 19 | namespace load_store_unit { |
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| 20 | |
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| 21 | |
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| 22 | #undef FUNCTION |
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| 23 | #define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore" |
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| 24 | void Load_store_unit::function_speculative_load_commit_genMoore (void) |
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| 25 | { |
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[101] | 26 | log_begin(Load_store_unit,FUNCTION); |
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| 27 | log_function(Load_store_unit,FUNCTION,_name.c_str()); |
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[59] | 28 | |
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[88] | 29 | // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[59] | 30 | |
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[71] | 31 | Tcontext_t memory_out_context_id = 0; |
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| 32 | Tcontext_t memory_out_front_end_id = 0; |
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| 33 | Tcontext_t memory_out_ooo_engine_id = 0; |
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| 34 | Tpacket_t memory_out_packet_id = 0; |
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| 35 | Tcontrol_t memory_out_write_rd = 0; |
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| 36 | Tgeneral_address_t memory_out_num_reg_rd = 0; |
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| 37 | Tgeneral_data_t memory_out_data_rd = 0; |
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| 38 | // Tcontrol_t memory_out_write_re = 0; |
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| 39 | // Tspecial_address_t memory_out_num_reg_re = 0; |
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| 40 | // Tspecial_data_t memory_out_data_re = 0; |
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| 41 | Texception_t memory_out_exception = 0; |
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[59] | 42 | |
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[71] | 43 | internal_MEMORY_OUT_VAL = 0; |
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[59] | 44 | |
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[62] | 45 | // Test store and load queue |
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[59] | 46 | |
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[101] | 47 | log_printf(TRACE,Load_store_unit,FUNCTION," * Test MEMORY_OUT"); |
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[71] | 48 | |
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[101] | 49 | log_printf(TRACE,Load_store_unit,FUNCTION," * Load queue"); |
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[71] | 50 | for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++) |
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| 51 | // for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++) |
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[59] | 52 | { |
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[71] | 53 | // internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue; |
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| 54 | internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK) or |
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| 55 | (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT)); |
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[59] | 56 | |
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[71] | 57 | if (internal_MEMORY_OUT_VAL) |
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| 58 | { |
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| 59 | log_printf(TRACE,Load_store_unit,FUNCTION," * find : %d",internal_MEMORY_OUT_PTR); |
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| 60 | internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE; |
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| 61 | |
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| 62 | memory_out_context_id = _load_queue [internal_MEMORY_OUT_PTR]._context_id; |
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| 63 | memory_out_front_end_id = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id; |
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| 64 | memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id; |
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| 65 | memory_out_packet_id = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ; |
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| 66 | memory_out_write_rd = _load_queue [internal_MEMORY_OUT_PTR]._write_rd ; |
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| 67 | memory_out_num_reg_rd = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd; |
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| 68 | |
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| 69 | Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata; |
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| 70 | Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data, |
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| 71 | data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift, |
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| 72 | _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed, |
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| 73 | _load_queue [internal_MEMORY_OUT_PTR]._access_size); |
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[101] | 74 | log_printf(TRACE,Load_store_unit,FUNCTION," * data (old) : %.8x",data_old); |
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| 75 | log_printf(TRACE,Load_store_unit,FUNCTION," * data (new) : %.8x",data_new); |
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[104] | 76 | log_printf(TRACE,Load_store_unit,FUNCTION," * address : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address); |
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[71] | 77 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata); |
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| 78 | log_printf(TRACE,Load_store_unit,FUNCTION," * shift : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift); |
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| 79 | log_printf(TRACE,Load_store_unit,FUNCTION," * signed? : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed); |
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| 80 | log_printf(TRACE,Load_store_unit,FUNCTION," * access_size : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size); |
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| 81 | |
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| 82 | Texception_t exception = _load_queue [internal_MEMORY_OUT_PTR]._exception; |
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| 83 | bool have_exception = ((exception != EXCEPTION_MEMORY_NONE) and |
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| 84 | (exception != EXCEPTION_MEMORY_MISS_SPECULATION)); |
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| 85 | |
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| 86 | // if exception, rdata content the address of load, else content read data. |
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| 87 | memory_out_data_rd = (have_exception)?data_old:data_new; |
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| 88 | memory_out_exception = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception; |
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| 89 | |
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[104] | 90 | log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",exception); |
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| 91 | log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",memory_out_exception); |
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| 92 | |
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[71] | 93 | break; // we have find a entry !!! stop the search |
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| 94 | } |
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[59] | 95 | } |
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| 96 | |
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[71] | 97 | if (not internal_MEMORY_OUT_VAL) |
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| 98 | { |
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[101] | 99 | log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue"); |
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[117] | 100 | // Can retire an store instruction if : |
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| 101 | // * state is commit |
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| 102 | // * none load must check this store |
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| 103 | if ((_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) and |
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| 104 | (reg_STORE_QUEUE_NB_CHECK [reg_STORE_QUEUE_PTR_READ] == 0)) |
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[71] | 105 | { |
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| 106 | log_printf(TRACE,Load_store_unit,FUNCTION," * find : %d",reg_STORE_QUEUE_PTR_READ); |
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| 107 | |
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| 108 | internal_MEMORY_OUT_VAL = 1; |
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| 109 | internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE; |
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| 110 | |
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| 111 | memory_out_context_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id; |
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| 112 | memory_out_front_end_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id; |
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| 113 | memory_out_ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id; |
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| 114 | memory_out_packet_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._packet_id ; |
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| 115 | // memory_out_write_rd |
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| 116 | // memory_out_num_reg_rd |
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| 117 | memory_out_data_rd = _store_queue [reg_STORE_QUEUE_PTR_READ]._address; // to the exception |
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| 118 | memory_out_exception = _store_queue [reg_STORE_QUEUE_PTR_READ]._exception; |
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| 119 | } |
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| 120 | } |
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[62] | 121 | // write output |
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[88] | 122 | PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL); |
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[59] | 123 | |
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[71] | 124 | if (_param->_have_port_context_id) |
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[88] | 125 | PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID [0], memory_out_context_id ); |
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[71] | 126 | if (_param->_have_port_front_end_id) |
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[88] | 127 | PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id ); |
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[71] | 128 | if (_param->_have_port_ooo_engine_id) |
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[88] | 129 | PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id); |
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| 130 | if (_param->_have_port_rob_ptr) |
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| 131 | PORT_WRITE(out_MEMORY_OUT_PACKET_ID [0], memory_out_packet_id ); |
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| 132 | // PORT_WRITE(out_MEMORY_OUT_OPERATION [0], memory_out_operation ); |
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[97] | 133 | // PORT_WRITE(out_MEMORY_OUT_TYPE [0], TYPE_MEMORY ); |
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[88] | 134 | PORT_WRITE(out_MEMORY_OUT_WRITE_RD [0], memory_out_write_rd ); |
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| 135 | PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD [0], memory_out_num_reg_rd ); |
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| 136 | PORT_WRITE(out_MEMORY_OUT_DATA_RD [0], memory_out_data_rd ); |
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| 137 | // PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], memory_out_write_re ); |
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| 138 | // PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], memory_out_num_reg_re ); |
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| 139 | // PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], memory_out_data_re ); |
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| 140 | PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], 0); |
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| 141 | PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], 0); |
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| 142 | PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], 0); |
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| 143 | PORT_WRITE(out_MEMORY_OUT_EXCEPTION [0], memory_out_exception ); |
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| 144 | PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE [0], 0); |
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| 145 | PORT_WRITE(out_MEMORY_OUT_ADDRESS [0], 0); |
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[59] | 146 | |
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[88] | 147 | // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 148 | |
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[62] | 149 | Tcontext_t dcache_req_context_id; |
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| 150 | Tpacket_t dcache_req_packet_id ; |
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| 151 | Tdcache_address_t dcache_req_address ; |
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| 152 | Tdcache_type_t dcache_req_type ; |
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| 153 | Tdcache_data_t dcache_req_wdata ; |
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| 154 | |
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[101] | 155 | log_printf(TRACE,Load_store_unit,FUNCTION," * Test DCACHE_REQ"); |
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[62] | 156 | |
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[71] | 157 | internal_DCACHE_REQ_VAL = 0; |
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[62] | 158 | |
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[71] | 159 | internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0]; |
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[62] | 160 | |
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[71] | 161 | // Test store and load queue |
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| 162 | if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE) |
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[62] | 163 | { |
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[101] | 164 | log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ); |
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[71] | 165 | |
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[62] | 166 | internal_DCACHE_REQ_VAL = 1; |
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[71] | 167 | internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE; |
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[62] | 168 | |
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[71] | 169 | if (_param->_have_port_dcache_context_id) |
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| 170 | { |
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| 171 | Tcontext_t context_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id; |
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| 172 | Tcontext_t front_end_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id; |
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| 173 | Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id; |
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| 174 | |
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| 175 | dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) | |
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| 176 | (front_end_id <<(_param->_size_context_id)) | |
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| 177 | (context_id)); |
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| 178 | } |
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| 179 | |
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| 180 | dcache_req_packet_id = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write); |
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[101] | 181 | dcache_req_address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb; |
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[71] | 182 | dcache_req_type = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation); |
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[101] | 183 | |
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| 184 | // log_printf(TRACE,Load_store_unit,FUNCTION," * address : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address); |
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| 185 | // log_printf(TRACE,Load_store_unit,FUNCTION," * mask : %.8x",_param->_mask_address_msb); |
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| 186 | log_printf(TRACE,Load_store_unit,FUNCTION," * dcache_req_address : %.8x",dcache_req_address); |
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| 187 | |
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[71] | 188 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 189 | dcache_req_wdata = 0; |
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| 190 | #endif |
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[62] | 191 | } |
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[71] | 192 | else |
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| 193 | { |
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| 194 | // Test an store must be commited. |
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| 195 | if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE) |
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| 196 | { |
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| 197 | internal_DCACHE_REQ_VAL = 1; |
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| 198 | internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE; |
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| 199 | |
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| 200 | if (_param->_have_port_dcache_context_id) |
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| 201 | { |
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| 202 | Tcontext_t context_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id; |
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| 203 | Tcontext_t front_end_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id; |
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| 204 | Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id; |
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| 205 | |
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| 206 | dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) | |
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| 207 | (front_end_id <<(_param->_size_context_id)) | |
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| 208 | (context_id)); |
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| 209 | } |
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[62] | 210 | |
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[71] | 211 | // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours) |
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| 212 | dcache_req_packet_id = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ); |
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[104] | 213 | dcache_req_address = _store_queue [reg_STORE_QUEUE_PTR_READ]._address; |
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[71] | 214 | dcache_req_type = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation); |
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[104] | 215 | dcache_req_wdata = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata; |
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[71] | 216 | } |
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| 217 | } |
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| 218 | |
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[88] | 219 | PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL); |
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[71] | 220 | if (_param->_have_port_dcache_context_id) |
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[88] | 221 | PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id); |
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| 222 | PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id ); |
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| 223 | PORT_WRITE(out_DCACHE_REQ_ADDRESS [0], dcache_req_address ); |
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| 224 | PORT_WRITE(out_DCACHE_REQ_TYPE [0], dcache_req_type ); |
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| 225 | PORT_WRITE(out_DCACHE_REQ_WDATA [0], dcache_req_wdata ); |
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[62] | 226 | |
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[101] | 227 | log_end(Load_store_unit,FUNCTION); |
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[59] | 228 | }; |
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| 229 | |
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| 230 | }; // end namespace load_store_unit |
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| 231 | }; // end namespace execute_unit |
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| 232 | }; // end namespace multi_execute_unit |
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| 233 | }; // end namespace execute_loop |
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| 234 | }; // end namespace multi_execute_loop |
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| 235 | }; // end namespace core |
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| 236 | |
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| 237 | }; // end namespace behavioural |
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| 238 | }; // end namespace morpheo |
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| 239 | #endif |
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| 240 | //#endif |
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