source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp @ 123

Last change on this file since 123 was 123, checked in by rosiere, 15 years ago

1) Fix performance
2) add auto generation to SPECINT2000
3) add reset in genMoore and genMealy
  • Property svn:keywords set to Id
File size: 12.7 KB
Line 
1#ifdef SYSTEMC
2//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
3/*
4 * $Id: Load_store_unit_function_speculative_load_commit_genMoore.cpp 123 2009-06-08 20:43:30Z rosiere $
5 *
6 * [ Description ]
7 *
8 */
9
10#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
11
12namespace morpheo                    {
13namespace behavioural {
14namespace core {
15namespace multi_execute_loop {
16namespace execute_loop {
17namespace multi_execute_unit {
18namespace execute_unit {
19namespace load_store_unit {
20
21
22#undef  FUNCTION
23#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore"
24  void Load_store_unit::function_speculative_load_commit_genMoore (void)
25  {
26    log_begin(Load_store_unit,FUNCTION);
27    log_function(Load_store_unit,FUNCTION,_name.c_str());
28
29    if (PORT_READ(in_NRESET))
30      {
31    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
32
33    Tcontext_t         memory_out_context_id    = 0;
34    Tcontext_t         memory_out_front_end_id  = 0;
35    Tcontext_t         memory_out_ooo_engine_id = 0;
36    Tpacket_t          memory_out_packet_id     = 0;
37    Tcontrol_t         memory_out_write_rd      = 0;
38    Tgeneral_address_t memory_out_num_reg_rd    = 0;
39    Tgeneral_data_t    memory_out_data_rd       = 0;
40//  Tcontrol_t         memory_out_write_re      = 0;
41//  Tspecial_address_t memory_out_num_reg_re    = 0;
42//  Tspecial_data_t    memory_out_data_re       = 0;
43    Tcontrol_t         memory_out_no_sequence   = 0;
44    Texception_t       memory_out_exception     = 0;
45
46    internal_MEMORY_OUT_VAL = 0;
47
48    // Test store and load queue
49
50    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
51
52    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
53    for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
54//     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
55      {
56//      internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
57        internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK) or
58                                   (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT));
59       
60        if (internal_MEMORY_OUT_VAL)
61          {
62            log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
63            internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE;
64           
65            memory_out_context_id    = _load_queue [internal_MEMORY_OUT_PTR]._context_id;
66            memory_out_front_end_id  = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id;
67            memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
68            memory_out_packet_id     = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ;
69            memory_out_write_rd      = _load_queue [internal_MEMORY_OUT_PTR]._write_rd  ;
70            memory_out_num_reg_rd    = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd;
71
72            Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata;
73            Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data,
74                                                             data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift,
75                                                             _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
76                                                             _load_queue [internal_MEMORY_OUT_PTR]._access_size);
77            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
78            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
79            log_printf(TRACE,Load_store_unit,FUNCTION,"      * address      : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address);
80            log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
81            log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
82            log_printf(TRACE,Load_store_unit,FUNCTION,"      * signed?      : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed);
83            log_printf(TRACE,Load_store_unit,FUNCTION,"      * access_size  : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size);
84
85            Texception_t exception      = _load_queue [internal_MEMORY_OUT_PTR]._exception;
86            bool         have_exception = ((exception != EXCEPTION_MEMORY_NONE) and
87                                           (exception != EXCEPTION_MEMORY_MISS_SPECULATION));
88
89            // if exception, rdata content the address of load, else content read data.
90            memory_out_data_rd       = (have_exception)?data_old:data_new;
91            memory_out_exception     = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception;
92
93            log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",exception);
94            log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",memory_out_exception);
95
96            break; // we have find a entry !!! stop the search
97          }
98      }
99
100    if (not internal_MEMORY_OUT_VAL)
101      {
102        log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
103
104        for (uint32_t i=0; i<_param->_size_store_queue; ++i)
105          {
106            internal_MEMORY_OUT_PTR = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
107            // Can retire an store instruction if :
108            //  * state is commit
109            //  * none load must check this store
110
111
112            bool val_head = ((i==0) and
113                             (_store_queue [internal_MEMORY_OUT_PTR]._state       == STORE_QUEUE_COMMIT) and
114                             (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == true) and
115                             (reg_STORE_QUEUE_NB_CHECK [internal_MEMORY_OUT_PTR] == 0)
116                             );
117
118            bool val_commit = ((_store_queue [internal_MEMORY_OUT_PTR]._state       != STORE_QUEUE_EMPTY) and
119                               (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == false));
120
121            if (val_head or val_commit)
122              {
123                log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
124               
125                internal_MEMORY_OUT_VAL          = 1;
126                internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
127               
128                memory_out_context_id    = _store_queue [internal_MEMORY_OUT_PTR]._context_id;
129                memory_out_front_end_id  = _store_queue [internal_MEMORY_OUT_PTR]._front_end_id;
130                memory_out_ooo_engine_id = _store_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
131                memory_out_packet_id     = _store_queue [internal_MEMORY_OUT_PTR]._packet_id ;
132//              memory_out_write_rd     
133//              memory_out_num_reg_rd   
134                memory_out_data_rd       = _store_queue [internal_MEMORY_OUT_PTR]._address; // to the exception
135                memory_out_exception     = _store_queue [internal_MEMORY_OUT_PTR]._exception;
136                memory_out_no_sequence   = val_commit;
137                break; // find an entry
138              }
139
140          }
141      }
142
143    // write output
144    if (_param->_have_port_context_id)
145    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
146    if (_param->_have_port_front_end_id)
147    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
148    if (_param->_have_port_ooo_engine_id)
149    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
150    if (_param->_have_port_rob_ptr)
151    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
152//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
153//  PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
154    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
155    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
156    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
157//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
158//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
159//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
160    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
161    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
162    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
163    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
164    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], memory_out_no_sequence  );// hack
165#ifdef DEBUG
166    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], memory_out_data_rd);
167#else
168    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
169#endif
170
171    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
172
173    Tcontext_t        dcache_req_context_id = 0;
174    Tpacket_t         dcache_req_packet_id  = 0;
175    Tdcache_address_t dcache_req_address    = 0;
176    Tdcache_type_t    dcache_req_type       = 0;
177    Tdcache_data_t    dcache_req_wdata      = 0;
178
179    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
180
181    internal_DCACHE_REQ_VAL = 0;
182
183    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0];
184
185    // Test store and load queue
186    if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
187      {
188        log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
189
190        internal_DCACHE_REQ_VAL          = 1;
191        internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
192
193        if (_param->_have_port_dcache_context_id)
194          {
195            Tcontext_t context_id    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
196            Tcontext_t front_end_id  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
197            Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
198           
199            dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
200                                     (front_end_id <<(_param->_size_context_id)) |
201                                     (context_id));
202          }
203
204        dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
205        dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
206        dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
207
208//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
209//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
210        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
211
212#ifdef SYSTEMC_VHDL_COMPATIBILITY
213        dcache_req_wdata      = 0;
214#endif
215      }
216    else
217      {
218        // Test an store must be commited.
219        if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
220          {
221            internal_DCACHE_REQ_VAL          = 1;
222            internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
223           
224            if (_param->_have_port_dcache_context_id)
225              {
226                Tcontext_t context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
227                Tcontext_t front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
228                Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
229               
230                dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
231                                         (front_end_id <<(_param->_size_context_id)) |
232                                         (context_id));
233              }
234
235            // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours)
236            dcache_req_packet_id  = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ);
237            dcache_req_address    = _store_queue [reg_STORE_QUEUE_PTR_READ]._address;
238            dcache_req_type       = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation);
239            dcache_req_wdata      = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata;
240          }
241      }
242
243    if (_param->_have_port_dcache_context_id)
244    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
245    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
246    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
247    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
248    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
249      }
250    else
251      {
252        // Reset
253    internal_MEMORY_OUT_VAL = 0;
254//  internal_MEMORY_OUT_PTR =0
255//  internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
256
257    internal_DCACHE_REQ_VAL = 0;
258    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = 0;
259//  internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
260      }
261
262    // Write output
263    PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL);
264    PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL);
265
266
267    log_end(Load_store_unit,FUNCTION);
268  };
269
270}; // end namespace load_store_unit
271}; // end namespace execute_unit
272}; // end namespace multi_execute_unit
273}; // end namespace execute_loop
274}; // end namespace multi_execute_loop
275}; // end namespace core
276
277}; // end namespace behavioural
278}; // end namespace morpheo             
279#endif
280//#endif
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