1 | #ifdef SYSTEMC |
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2 | //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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3 | /* |
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4 | * $Id: Load_store_unit_function_speculative_load_commit_genMoore.cpp 123 2009-06-08 20:43:30Z rosiere $ |
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5 | * |
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6 | * [ Description ] |
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7 | * |
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8 | */ |
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9 | |
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10 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" |
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11 | |
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12 | namespace morpheo { |
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13 | namespace behavioural { |
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14 | namespace core { |
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15 | namespace multi_execute_loop { |
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16 | namespace execute_loop { |
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17 | namespace multi_execute_unit { |
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18 | namespace execute_unit { |
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19 | namespace load_store_unit { |
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20 | |
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21 | |
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22 | #undef FUNCTION |
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23 | #define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore" |
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24 | void Load_store_unit::function_speculative_load_commit_genMoore (void) |
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25 | { |
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26 | log_begin(Load_store_unit,FUNCTION); |
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27 | log_function(Load_store_unit,FUNCTION,_name.c_str()); |
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28 | |
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29 | if (PORT_READ(in_NRESET)) |
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30 | { |
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31 | // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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32 | |
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33 | Tcontext_t memory_out_context_id = 0; |
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34 | Tcontext_t memory_out_front_end_id = 0; |
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35 | Tcontext_t memory_out_ooo_engine_id = 0; |
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36 | Tpacket_t memory_out_packet_id = 0; |
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37 | Tcontrol_t memory_out_write_rd = 0; |
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38 | Tgeneral_address_t memory_out_num_reg_rd = 0; |
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39 | Tgeneral_data_t memory_out_data_rd = 0; |
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40 | // Tcontrol_t memory_out_write_re = 0; |
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41 | // Tspecial_address_t memory_out_num_reg_re = 0; |
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42 | // Tspecial_data_t memory_out_data_re = 0; |
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43 | Tcontrol_t memory_out_no_sequence = 0; |
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44 | Texception_t memory_out_exception = 0; |
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45 | |
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46 | internal_MEMORY_OUT_VAL = 0; |
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47 | |
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48 | // Test store and load queue |
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49 | |
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50 | log_printf(TRACE,Load_store_unit,FUNCTION," * Test MEMORY_OUT"); |
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51 | |
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52 | log_printf(TRACE,Load_store_unit,FUNCTION," * Load queue"); |
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53 | for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++) |
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54 | // for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++) |
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55 | { |
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56 | // internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue; |
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57 | internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK) or |
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58 | (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT)); |
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59 | |
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60 | if (internal_MEMORY_OUT_VAL) |
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61 | { |
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62 | log_printf(TRACE,Load_store_unit,FUNCTION," * find : %d",internal_MEMORY_OUT_PTR); |
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63 | internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE; |
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64 | |
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65 | memory_out_context_id = _load_queue [internal_MEMORY_OUT_PTR]._context_id; |
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66 | memory_out_front_end_id = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id; |
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67 | memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id; |
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68 | memory_out_packet_id = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ; |
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69 | memory_out_write_rd = _load_queue [internal_MEMORY_OUT_PTR]._write_rd ; |
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70 | memory_out_num_reg_rd = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd; |
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71 | |
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72 | Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata; |
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73 | Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data, |
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74 | data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift, |
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75 | _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed, |
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76 | _load_queue [internal_MEMORY_OUT_PTR]._access_size); |
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77 | log_printf(TRACE,Load_store_unit,FUNCTION," * data (old) : %.8x",data_old); |
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78 | log_printf(TRACE,Load_store_unit,FUNCTION," * data (new) : %.8x",data_new); |
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79 | log_printf(TRACE,Load_store_unit,FUNCTION," * address : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address); |
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80 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata); |
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81 | log_printf(TRACE,Load_store_unit,FUNCTION," * shift : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift); |
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82 | log_printf(TRACE,Load_store_unit,FUNCTION," * signed? : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed); |
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83 | log_printf(TRACE,Load_store_unit,FUNCTION," * access_size : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size); |
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84 | |
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85 | Texception_t exception = _load_queue [internal_MEMORY_OUT_PTR]._exception; |
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86 | bool have_exception = ((exception != EXCEPTION_MEMORY_NONE) and |
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87 | (exception != EXCEPTION_MEMORY_MISS_SPECULATION)); |
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88 | |
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89 | // if exception, rdata content the address of load, else content read data. |
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90 | memory_out_data_rd = (have_exception)?data_old:data_new; |
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91 | memory_out_exception = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception; |
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92 | |
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93 | log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",exception); |
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94 | log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",memory_out_exception); |
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95 | |
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96 | break; // we have find a entry !!! stop the search |
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97 | } |
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98 | } |
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99 | |
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100 | if (not internal_MEMORY_OUT_VAL) |
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101 | { |
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102 | log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue"); |
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103 | |
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104 | for (uint32_t i=0; i<_param->_size_store_queue; ++i) |
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105 | { |
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106 | internal_MEMORY_OUT_PTR = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; |
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107 | // Can retire an store instruction if : |
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108 | // * state is commit |
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109 | // * none load must check this store |
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110 | |
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111 | |
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112 | bool val_head = ((i==0) and |
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113 | (_store_queue [internal_MEMORY_OUT_PTR]._state == STORE_QUEUE_COMMIT) and |
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114 | (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == true) and |
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115 | (reg_STORE_QUEUE_NB_CHECK [internal_MEMORY_OUT_PTR] == 0) |
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116 | ); |
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117 | |
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118 | bool val_commit = ((_store_queue [internal_MEMORY_OUT_PTR]._state != STORE_QUEUE_EMPTY) and |
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119 | (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == false)); |
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120 | |
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121 | if (val_head or val_commit) |
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122 | { |
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123 | log_printf(TRACE,Load_store_unit,FUNCTION," * find : %d",internal_MEMORY_OUT_PTR); |
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124 | |
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125 | internal_MEMORY_OUT_VAL = 1; |
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126 | internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE; |
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127 | |
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128 | memory_out_context_id = _store_queue [internal_MEMORY_OUT_PTR]._context_id; |
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129 | memory_out_front_end_id = _store_queue [internal_MEMORY_OUT_PTR]._front_end_id; |
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130 | memory_out_ooo_engine_id = _store_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id; |
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131 | memory_out_packet_id = _store_queue [internal_MEMORY_OUT_PTR]._packet_id ; |
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132 | // memory_out_write_rd |
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133 | // memory_out_num_reg_rd |
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134 | memory_out_data_rd = _store_queue [internal_MEMORY_OUT_PTR]._address; // to the exception |
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135 | memory_out_exception = _store_queue [internal_MEMORY_OUT_PTR]._exception; |
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136 | memory_out_no_sequence = val_commit; |
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137 | break; // find an entry |
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138 | } |
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139 | |
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140 | } |
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141 | } |
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142 | |
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143 | // write output |
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144 | if (_param->_have_port_context_id) |
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145 | PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID [0], memory_out_context_id ); |
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146 | if (_param->_have_port_front_end_id) |
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147 | PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id ); |
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148 | if (_param->_have_port_ooo_engine_id) |
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149 | PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id); |
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150 | if (_param->_have_port_rob_ptr) |
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151 | PORT_WRITE(out_MEMORY_OUT_PACKET_ID [0], memory_out_packet_id ); |
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152 | // PORT_WRITE(out_MEMORY_OUT_OPERATION [0], memory_out_operation ); |
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153 | // PORT_WRITE(out_MEMORY_OUT_TYPE [0], TYPE_MEMORY ); |
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154 | PORT_WRITE(out_MEMORY_OUT_WRITE_RD [0], memory_out_write_rd ); |
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155 | PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD [0], memory_out_num_reg_rd ); |
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156 | PORT_WRITE(out_MEMORY_OUT_DATA_RD [0], memory_out_data_rd ); |
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157 | // PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], memory_out_write_re ); |
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158 | // PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], memory_out_num_reg_re ); |
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159 | // PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], memory_out_data_re ); |
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160 | PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], 0); |
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161 | PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], 0); |
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162 | PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], 0); |
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163 | PORT_WRITE(out_MEMORY_OUT_EXCEPTION [0], memory_out_exception ); |
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164 | PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE [0], memory_out_no_sequence );// hack |
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165 | #ifdef DEBUG |
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166 | PORT_WRITE(out_MEMORY_OUT_ADDRESS [0], memory_out_data_rd); |
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167 | #else |
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168 | PORT_WRITE(out_MEMORY_OUT_ADDRESS [0], 0); |
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169 | #endif |
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170 | |
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171 | // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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172 | |
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173 | Tcontext_t dcache_req_context_id = 0; |
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174 | Tpacket_t dcache_req_packet_id = 0; |
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175 | Tdcache_address_t dcache_req_address = 0; |
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176 | Tdcache_type_t dcache_req_type = 0; |
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177 | Tdcache_data_t dcache_req_wdata = 0; |
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178 | |
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179 | log_printf(TRACE,Load_store_unit,FUNCTION," * Test DCACHE_REQ"); |
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180 | |
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181 | internal_DCACHE_REQ_VAL = 0; |
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182 | |
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183 | internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0]; |
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184 | |
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185 | // Test store and load queue |
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186 | if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE) |
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187 | { |
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188 | log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ); |
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189 | |
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190 | internal_DCACHE_REQ_VAL = 1; |
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191 | internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE; |
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192 | |
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193 | if (_param->_have_port_dcache_context_id) |
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194 | { |
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195 | Tcontext_t context_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id; |
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196 | Tcontext_t front_end_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id; |
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197 | Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id; |
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198 | |
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199 | dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) | |
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200 | (front_end_id <<(_param->_size_context_id)) | |
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201 | (context_id)); |
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202 | } |
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203 | |
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204 | dcache_req_packet_id = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write); |
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205 | dcache_req_address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb; |
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206 | dcache_req_type = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation); |
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207 | |
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208 | // log_printf(TRACE,Load_store_unit,FUNCTION," * address : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address); |
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209 | // log_printf(TRACE,Load_store_unit,FUNCTION," * mask : %.8x",_param->_mask_address_msb); |
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210 | log_printf(TRACE,Load_store_unit,FUNCTION," * dcache_req_address : %.8x",dcache_req_address); |
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211 | |
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212 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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213 | dcache_req_wdata = 0; |
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214 | #endif |
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215 | } |
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216 | else |
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217 | { |
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218 | // Test an store must be commited. |
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219 | if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE) |
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220 | { |
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221 | internal_DCACHE_REQ_VAL = 1; |
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222 | internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE; |
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223 | |
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224 | if (_param->_have_port_dcache_context_id) |
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225 | { |
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226 | Tcontext_t context_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id; |
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227 | Tcontext_t front_end_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id; |
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228 | Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id; |
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229 | |
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230 | dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) | |
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231 | (front_end_id <<(_param->_size_context_id)) | |
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232 | (context_id)); |
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233 | } |
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234 | |
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235 | // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours) |
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236 | dcache_req_packet_id = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ); |
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237 | dcache_req_address = _store_queue [reg_STORE_QUEUE_PTR_READ]._address; |
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238 | dcache_req_type = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation); |
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239 | dcache_req_wdata = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata; |
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240 | } |
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241 | } |
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242 | |
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243 | if (_param->_have_port_dcache_context_id) |
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244 | PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id); |
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245 | PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id ); |
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246 | PORT_WRITE(out_DCACHE_REQ_ADDRESS [0], dcache_req_address ); |
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247 | PORT_WRITE(out_DCACHE_REQ_TYPE [0], dcache_req_type ); |
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248 | PORT_WRITE(out_DCACHE_REQ_WDATA [0], dcache_req_wdata ); |
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249 | } |
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250 | else |
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251 | { |
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252 | // Reset |
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253 | internal_MEMORY_OUT_VAL = 0; |
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254 | // internal_MEMORY_OUT_PTR =0 |
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255 | // internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE; |
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256 | |
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257 | internal_DCACHE_REQ_VAL = 0; |
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258 | internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = 0; |
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259 | // internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE; |
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260 | } |
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261 | |
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262 | // Write output |
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263 | PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL); |
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264 | PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL); |
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265 | |
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266 | |
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267 | log_end(Load_store_unit,FUNCTION); |
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268 | }; |
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269 | |
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270 | }; // end namespace load_store_unit |
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271 | }; // end namespace execute_unit |
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272 | }; // end namespace multi_execute_unit |
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273 | }; // end namespace execute_loop |
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274 | }; // end namespace multi_execute_loop |
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275 | }; // end namespace core |
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276 | |
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277 | }; // end namespace behavioural |
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278 | }; // end namespace morpheo |
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279 | #endif |
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280 | //#endif |
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