[55] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/include/test.h" |
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| 10 | #include "Common/include/Test.h" |
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| 11 | |
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[69] | 12 | #define NB_ITERATION 2 |
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| 13 | #define CYCLE_MAX (2048*NB_ITERATION) |
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[55] | 14 | |
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| 15 | #define LABEL(str) \ |
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| 16 | { \ |
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| 17 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \ |
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| 18 | } while(0) |
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| 19 | |
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| 20 | static uint32_t cycle = 0; |
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| 21 | |
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| 22 | #define SC_START(cycle_offset) \ |
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| 23 | do \ |
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| 24 | { \ |
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| 25 | /*cout << "SC_START (begin)" << endl;*/ \ |
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| 26 | \ |
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| 27 | uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ |
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| 28 | sc_start(cycle_offset); \ |
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| 29 | if (cycle_current != cycle) \ |
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| 30 | { \ |
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| 31 | cycle = cycle_current; \ |
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| 32 | cout << "##########[ cycle "<< cycle << " ]" << endl; \ |
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| 33 | } \ |
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| 34 | \ |
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| 35 | if (cycle_current > CYCLE_MAX) \ |
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| 36 | { \ |
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| 37 | TEST_KO("Maximal cycles Reached"); \ |
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| 38 | } \ |
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| 39 | /*cout << "SC_START (end )" << endl;*/ \ |
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| 40 | } while(0) |
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| 41 | |
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| 42 | void test (string name, |
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| 43 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::reservation_station::Parameters * _param) |
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| 44 | { |
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| 45 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 46 | |
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| 47 | #ifdef STATISTICS |
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| 48 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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| 49 | #endif |
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| 50 | |
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| 51 | Reservation_station * _Reservation_station = new Reservation_station (name.c_str(), |
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| 52 | #ifdef STATISTICS |
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| 53 | _parameters_statistics, |
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| 54 | #endif |
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| 55 | _param); |
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| 56 | |
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| 57 | #ifdef SYSTEMC |
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| 58 | /********************************************************************* |
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| 59 | * Déclarations des signaux |
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| 60 | *********************************************************************/ |
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| 61 | string rename = ""; |
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| 62 | |
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| 63 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 64 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 65 | |
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[69] | 66 | sc_signal<Tcontrol_t > * in_INSERT_VAL = new sc_signal<Tcontrol_t >; |
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| 67 | sc_signal<Tcontrol_t > * out_INSERT_ACK = new sc_signal<Tcontrol_t >; |
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| 68 | sc_signal<Tcontext_t > * in_INSERT_CONTEXT_ID = new sc_signal<Tcontext_t >; |
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| 69 | sc_signal<Tcontext_t > * in_INSERT_FRONT_END_ID = new sc_signal<Tcontext_t >; |
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| 70 | sc_signal<Tcontext_t > * in_INSERT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >; |
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| 71 | sc_signal<Tpacket_t > * in_INSERT_ROB_ID = new sc_signal<Tpacket_t >; |
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| 72 | sc_signal<Toperation_t > * in_INSERT_OPERATION = new sc_signal<Toperation_t >; |
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| 73 | sc_signal<Ttype_t > * in_INSERT_TYPE = new sc_signal<Ttype_t >; |
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| 74 | sc_signal<Tcontrol_t > * in_INSERT_HAS_IMMEDIAT = new sc_signal<Tcontrol_t >; |
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| 75 | sc_signal<Tgeneral_data_t > * in_INSERT_IMMEDIAT = new sc_signal<Tgeneral_data_t >; |
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| 76 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RA = new sc_signal<Tcontrol_t >; |
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| 77 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RA = new sc_signal<Tgeneral_address_t>; |
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| 78 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RA_VAL = new sc_signal<Tcontrol_t >; |
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| 79 | sc_signal<Tgeneral_data_t > * in_INSERT_DATA_RA = new sc_signal<Tgeneral_data_t >; |
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| 80 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RB = new sc_signal<Tcontrol_t >; |
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| 81 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RB = new sc_signal<Tgeneral_address_t>; |
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| 82 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RB_VAL = new sc_signal<Tcontrol_t >; |
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| 83 | sc_signal<Tgeneral_data_t > * in_INSERT_DATA_RB = new sc_signal<Tgeneral_data_t >; |
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| 84 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RC = new sc_signal<Tcontrol_t >; |
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| 85 | sc_signal<Tspecial_address_t> * in_INSERT_NUM_REG_RC = new sc_signal<Tspecial_address_t>; |
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| 86 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RC_VAL = new sc_signal<Tcontrol_t >; |
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| 87 | sc_signal<Tspecial_data_t > * in_INSERT_DATA_RC = new sc_signal<Tspecial_data_t >; |
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| 88 | sc_signal<Tcontrol_t > * in_INSERT_WRITE_RD = new sc_signal<Tcontrol_t >; |
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| 89 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>; |
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| 90 | sc_signal<Tcontrol_t > * in_INSERT_WRITE_RE = new sc_signal<Tcontrol_t >; |
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| 91 | sc_signal<Tspecial_address_t> * in_INSERT_NUM_REG_RE = new sc_signal<Tspecial_address_t>; |
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[55] | 92 | |
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[69] | 93 | sc_signal<Tcontrol_t > ** out_RETIRE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 94 | sc_signal<Tcontrol_t > ** in_RETIRE_ACK = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 95 | sc_signal<Tcontext_t > ** out_RETIRE_CONTEXT_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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| 96 | sc_signal<Tcontext_t > ** out_RETIRE_FRONT_END_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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| 97 | sc_signal<Tcontext_t > ** out_RETIRE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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| 98 | sc_signal<Tpacket_t > ** out_RETIRE_ROB_ID = new sc_signal<Tpacket_t > * [_param->_nb_inst_retire]; |
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| 99 | sc_signal<Toperation_t > ** out_RETIRE_OPERATION = new sc_signal<Toperation_t > * [_param->_nb_inst_retire]; |
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| 100 | sc_signal<Ttype_t > ** out_RETIRE_TYPE = new sc_signal<Ttype_t > * [_param->_nb_inst_retire]; |
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| 101 | sc_signal<Tcontrol_t > ** out_RETIRE_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 102 | sc_signal<Tgeneral_data_t > ** out_RETIRE_IMMEDIAT = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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| 103 | sc_signal<Tgeneral_data_t > ** out_RETIRE_DATA_RA = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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| 104 | sc_signal<Tgeneral_data_t > ** out_RETIRE_DATA_RB = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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| 105 | sc_signal<Tspecial_data_t > ** out_RETIRE_DATA_RC = new sc_signal<Tspecial_data_t > * [_param->_nb_inst_retire]; |
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| 106 | sc_signal<Tcontrol_t > ** out_RETIRE_WRITE_RD = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 107 | sc_signal<Tgeneral_address_t> ** out_RETIRE_NUM_REG_RD = new sc_signal<Tgeneral_address_t> * [_param->_nb_inst_retire]; |
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| 108 | sc_signal<Tcontrol_t > ** out_RETIRE_WRITE_RE = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 109 | sc_signal<Tspecial_address_t> ** out_RETIRE_NUM_REG_RE = new sc_signal<Tspecial_address_t> * [_param->_nb_inst_retire]; |
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[55] | 110 | |
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[69] | 111 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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[55] | 112 | { |
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[69] | 113 | out_RETIRE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 114 | in_RETIRE_ACK [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 115 | out_RETIRE_CONTEXT_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 116 | out_RETIRE_FRONT_END_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 117 | out_RETIRE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 118 | out_RETIRE_ROB_ID [i] = new sc_signal<Tpacket_t > (rename.c_str()); |
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| 119 | out_RETIRE_OPERATION [i] = new sc_signal<Toperation_t > (rename.c_str()); |
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| 120 | out_RETIRE_TYPE [i] = new sc_signal<Ttype_t > (rename.c_str()); |
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| 121 | out_RETIRE_HAS_IMMEDIAT [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 122 | out_RETIRE_IMMEDIAT [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 123 | out_RETIRE_DATA_RA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 124 | out_RETIRE_DATA_RB [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 125 | out_RETIRE_DATA_RC [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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| 126 | out_RETIRE_WRITE_RD [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 127 | out_RETIRE_NUM_REG_RD [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 128 | out_RETIRE_WRITE_RE [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 129 | out_RETIRE_NUM_REG_RE [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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[55] | 130 | } |
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| 131 | |
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[69] | 132 | sc_signal<Tcontrol_t > ** in_GPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_gpr_write]; |
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| 133 | sc_signal<Tcontext_t > ** in_GPR_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_gpr_write]; |
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| 134 | sc_signal<Tgeneral_address_t> ** in_GPR_WRITE_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_gpr_write]; |
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| 135 | sc_signal<Tgeneral_data_t > ** in_GPR_WRITE_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_gpr_write]; |
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[55] | 136 | |
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| 137 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
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| 138 | { |
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[69] | 139 | in_GPR_WRITE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 140 | in_GPR_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 141 | in_GPR_WRITE_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 142 | in_GPR_WRITE_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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[55] | 143 | } |
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| 144 | |
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[69] | 145 | sc_signal<Tcontrol_t > ** in_SPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_spr_write]; |
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| 146 | sc_signal<Tcontext_t > ** in_SPR_WRITE_OOO_ENGINE_ID= new sc_signal<Tcontext_t > * [_param->_nb_spr_write]; |
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| 147 | sc_signal<Tspecial_address_t> ** in_SPR_WRITE_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_spr_write]; |
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| 148 | sc_signal<Tspecial_data_t > ** in_SPR_WRITE_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_spr_write]; |
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[55] | 149 | |
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| 150 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
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| 151 | { |
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[69] | 152 | in_SPR_WRITE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 153 | in_SPR_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 154 | in_SPR_WRITE_NUM_REG [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 155 | in_SPR_WRITE_DATA [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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[55] | 156 | } |
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| 157 | |
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[69] | 158 | sc_signal<Tcontext_t > ** in_BYPASS_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_write]; |
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| 159 | sc_signal<Tcontrol_t > ** in_BYPASS_WRITE_GPR_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_write]; |
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| 160 | sc_signal<Tgeneral_address_t> ** in_BYPASS_WRITE_GPR_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_write]; |
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| 161 | sc_signal<Tgeneral_data_t > ** in_BYPASS_WRITE_GPR_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_write]; |
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| 162 | sc_signal<Tcontrol_t > ** in_BYPASS_WRITE_SPR_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_write]; |
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| 163 | sc_signal<Tspecial_address_t> ** in_BYPASS_WRITE_SPR_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_bypass_write]; |
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| 164 | sc_signal<Tspecial_data_t > ** in_BYPASS_WRITE_SPR_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_bypass_write]; |
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[55] | 165 | |
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| 166 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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| 167 | { |
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[69] | 168 | in_BYPASS_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 169 | in_BYPASS_WRITE_GPR_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 170 | in_BYPASS_WRITE_GPR_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 171 | in_BYPASS_WRITE_GPR_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 172 | in_BYPASS_WRITE_SPR_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 173 | in_BYPASS_WRITE_SPR_NUM_REG [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 174 | in_BYPASS_WRITE_SPR_DATA [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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[55] | 175 | } |
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[69] | 176 | sc_signal<Tcontrol_t > ** in_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory]; |
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| 177 | sc_signal<Tcontext_t > ** in_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory]; |
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| 178 | sc_signal<Tgeneral_address_t> ** in_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory]; |
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| 179 | sc_signal<Tgeneral_data_t > ** in_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory]; |
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[55] | 180 | |
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| 181 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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| 182 | { |
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[69] | 183 | in_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 184 | in_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 185 | in_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 186 | in_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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[55] | 187 | } |
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| 188 | |
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| 189 | /******************************************************** |
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| 190 | * Instanciation |
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| 191 | ********************************************************/ |
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| 192 | |
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| 193 | cout << "<" << name << "> Instanciation of _Reservation_station" << endl; |
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| 194 | |
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| 195 | (*(_Reservation_station->in_CLOCK)) (*(in_CLOCK)); |
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| 196 | (*(_Reservation_station->in_NRESET)) (*(in_NRESET)); |
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| 197 | |
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[69] | 198 | (*(_Reservation_station-> in_INSERT_VAL )) (*( in_INSERT_VAL )); |
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| 199 | (*(_Reservation_station->out_INSERT_ACK )) (*(out_INSERT_ACK )); |
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| 200 | if (_param->_have_port_context_id) |
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| 201 | (*(_Reservation_station-> in_INSERT_CONTEXT_ID )) (*( in_INSERT_CONTEXT_ID )); |
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| 202 | if (_param->_have_port_front_end_id) |
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| 203 | (*(_Reservation_station-> in_INSERT_FRONT_END_ID )) (*( in_INSERT_FRONT_END_ID )); |
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| 204 | if (_param->_have_port_ooo_engine_id) |
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| 205 | (*(_Reservation_station-> in_INSERT_OOO_ENGINE_ID )) (*( in_INSERT_OOO_ENGINE_ID )); |
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| 206 | if (_param->_have_port_rob_id) |
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| 207 | (*(_Reservation_station-> in_INSERT_ROB_ID )) (*( in_INSERT_ROB_ID )); |
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| 208 | (*(_Reservation_station-> in_INSERT_OPERATION )) (*( in_INSERT_OPERATION )); |
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| 209 | (*(_Reservation_station-> in_INSERT_TYPE )) (*( in_INSERT_TYPE )); |
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| 210 | (*(_Reservation_station-> in_INSERT_HAS_IMMEDIAT )) (*( in_INSERT_HAS_IMMEDIAT )); |
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| 211 | (*(_Reservation_station-> in_INSERT_IMMEDIAT )) (*( in_INSERT_IMMEDIAT )); |
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| 212 | // (*(_Reservation_station-> in_INSERT_READ_RA )) (*( in_INSERT_READ_RA )); |
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| 213 | (*(_Reservation_station-> in_INSERT_NUM_REG_RA )) (*( in_INSERT_NUM_REG_RA )); |
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| 214 | (*(_Reservation_station-> in_INSERT_DATA_RA_VAL )) (*( in_INSERT_DATA_RA_VAL )); |
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| 215 | (*(_Reservation_station-> in_INSERT_DATA_RA )) (*( in_INSERT_DATA_RA )); |
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| 216 | // (*(_Reservation_station-> in_INSERT_READ_RB )) (*( in_INSERT_READ_RB )); |
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| 217 | (*(_Reservation_station-> in_INSERT_NUM_REG_RB )) (*( in_INSERT_NUM_REG_RB )); |
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| 218 | (*(_Reservation_station-> in_INSERT_DATA_RB_VAL )) (*( in_INSERT_DATA_RB_VAL )); |
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| 219 | (*(_Reservation_station-> in_INSERT_DATA_RB )) (*( in_INSERT_DATA_RB )); |
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| 220 | // (*(_Reservation_station-> in_INSERT_READ_RC )) (*( in_INSERT_READ_RC )); |
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| 221 | (*(_Reservation_station-> in_INSERT_NUM_REG_RC )) (*( in_INSERT_NUM_REG_RC )); |
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| 222 | (*(_Reservation_station-> in_INSERT_DATA_RC_VAL )) (*( in_INSERT_DATA_RC_VAL )); |
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| 223 | (*(_Reservation_station-> in_INSERT_DATA_RC )) (*( in_INSERT_DATA_RC )); |
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| 224 | (*(_Reservation_station-> in_INSERT_WRITE_RD )) (*( in_INSERT_WRITE_RD )); |
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| 225 | (*(_Reservation_station-> in_INSERT_NUM_REG_RD )) (*( in_INSERT_NUM_REG_RD )); |
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| 226 | (*(_Reservation_station-> in_INSERT_WRITE_RE )) (*( in_INSERT_WRITE_RE )); |
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| 227 | (*(_Reservation_station-> in_INSERT_NUM_REG_RE )) (*( in_INSERT_NUM_REG_RE )); |
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[55] | 228 | |
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[69] | 229 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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[55] | 230 | { |
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[69] | 231 | (*(_Reservation_station->out_RETIRE_VAL [i])) (*(out_RETIRE_VAL [i])); |
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| 232 | (*(_Reservation_station-> in_RETIRE_ACK [i])) (*( in_RETIRE_ACK [i])); |
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| 233 | if (_param->_have_port_context_id) |
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| 234 | (*(_Reservation_station->out_RETIRE_CONTEXT_ID [i])) (*(out_RETIRE_CONTEXT_ID [i])); |
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| 235 | if (_param->_have_port_front_end_id) |
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| 236 | (*(_Reservation_station->out_RETIRE_FRONT_END_ID [i])) (*(out_RETIRE_FRONT_END_ID [i])); |
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| 237 | if (_param->_have_port_ooo_engine_id) |
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| 238 | (*(_Reservation_station->out_RETIRE_OOO_ENGINE_ID [i])) (*(out_RETIRE_OOO_ENGINE_ID [i])); |
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| 239 | if (_param->_have_port_rob_id) |
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| 240 | (*(_Reservation_station->out_RETIRE_ROB_ID [i])) (*(out_RETIRE_ROB_ID [i])); |
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| 241 | (*(_Reservation_station->out_RETIRE_OPERATION [i])) (*(out_RETIRE_OPERATION [i])); |
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| 242 | (*(_Reservation_station->out_RETIRE_TYPE [i])) (*(out_RETIRE_TYPE [i])); |
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| 243 | (*(_Reservation_station->out_RETIRE_HAS_IMMEDIAT [i])) (*(out_RETIRE_HAS_IMMEDIAT [i])); |
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| 244 | (*(_Reservation_station->out_RETIRE_IMMEDIAT [i])) (*(out_RETIRE_IMMEDIAT [i])); |
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| 245 | (*(_Reservation_station->out_RETIRE_DATA_RA [i])) (*(out_RETIRE_DATA_RA [i])); |
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| 246 | (*(_Reservation_station->out_RETIRE_DATA_RB [i])) (*(out_RETIRE_DATA_RB [i])); |
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| 247 | (*(_Reservation_station->out_RETIRE_DATA_RC [i])) (*(out_RETIRE_DATA_RC [i])); |
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| 248 | (*(_Reservation_station->out_RETIRE_WRITE_RD [i])) (*(out_RETIRE_WRITE_RD [i])); |
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| 249 | (*(_Reservation_station->out_RETIRE_NUM_REG_RD [i])) (*(out_RETIRE_NUM_REG_RD [i])); |
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| 250 | (*(_Reservation_station->out_RETIRE_WRITE_RE [i])) (*(out_RETIRE_WRITE_RE [i])); |
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| 251 | (*(_Reservation_station->out_RETIRE_NUM_REG_RE [i])) (*(out_RETIRE_NUM_REG_RE [i])); |
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[55] | 252 | } |
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| 253 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
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| 254 | { |
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| 255 | (*(_Reservation_station-> in_GPR_WRITE_VAL [i])) (*( in_GPR_WRITE_VAL [i])); |
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[69] | 256 | if (_param->_have_port_ooo_engine_id) |
---|
| 257 | (*(_Reservation_station-> in_GPR_WRITE_OOO_ENGINE_ID [i])) (*( in_GPR_WRITE_OOO_ENGINE_ID [i])); |
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[55] | 258 | (*(_Reservation_station-> in_GPR_WRITE_NUM_REG [i])) (*( in_GPR_WRITE_NUM_REG [i])); |
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| 259 | (*(_Reservation_station-> in_GPR_WRITE_DATA [i])) (*( in_GPR_WRITE_DATA [i])); |
---|
| 260 | } |
---|
| 261 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
| 262 | { |
---|
| 263 | (*(_Reservation_station-> in_SPR_WRITE_VAL [i])) (*( in_SPR_WRITE_VAL [i])); |
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[69] | 264 | if (_param->_have_port_ooo_engine_id) |
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| 265 | (*(_Reservation_station-> in_SPR_WRITE_OOO_ENGINE_ID [i])) (*( in_SPR_WRITE_OOO_ENGINE_ID [i])); |
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[55] | 266 | (*(_Reservation_station-> in_SPR_WRITE_NUM_REG [i])) (*( in_SPR_WRITE_NUM_REG [i])); |
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| 267 | (*(_Reservation_station-> in_SPR_WRITE_DATA [i])) (*( in_SPR_WRITE_DATA [i])); |
---|
| 268 | } |
---|
| 269 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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| 270 | { |
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[69] | 271 | if (_param->_have_port_ooo_engine_id) |
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| 272 | (*(_Reservation_station-> in_BYPASS_WRITE_OOO_ENGINE_ID [i])) (*( in_BYPASS_WRITE_OOO_ENGINE_ID [i])); |
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[55] | 273 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_VAL [i])) (*( in_BYPASS_WRITE_GPR_VAL [i])); |
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| 274 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_NUM_REG [i])) (*( in_BYPASS_WRITE_GPR_NUM_REG [i])); |
---|
| 275 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_DATA [i])) (*( in_BYPASS_WRITE_GPR_DATA [i])); |
---|
| 276 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_VAL [i])) (*( in_BYPASS_WRITE_SPR_VAL [i])); |
---|
| 277 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_NUM_REG [i])) (*( in_BYPASS_WRITE_SPR_NUM_REG [i])); |
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| 278 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_DATA [i])) (*( in_BYPASS_WRITE_SPR_DATA [i])); |
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| 279 | } |
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| 280 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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| 281 | { |
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| 282 | (*(_Reservation_station-> in_BYPASS_MEMORY_VAL [i])) (*( in_BYPASS_MEMORY_VAL [i])); |
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[69] | 283 | if (_param->_have_port_ooo_engine_id) |
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| 284 | (*(_Reservation_station-> in_BYPASS_MEMORY_OOO_ENGINE_ID [i])) (*( in_BYPASS_MEMORY_OOO_ENGINE_ID [i])); |
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[55] | 285 | (*(_Reservation_station-> in_BYPASS_MEMORY_NUM_REG [i])) (*( in_BYPASS_MEMORY_NUM_REG [i])); |
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| 286 | (*(_Reservation_station-> in_BYPASS_MEMORY_DATA [i])) (*( in_BYPASS_MEMORY_DATA [i])); |
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| 287 | } |
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| 288 | |
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| 289 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 290 | Time * _time = new Time(); |
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| 291 | |
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| 292 | /******************************************************** |
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| 293 | * Simulation - Begin |
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| 294 | ********************************************************/ |
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| 295 | |
---|
| 296 | // Initialisation |
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| 297 | |
---|
| 298 | const uint32_t nb_request = _param->_nb_packet; |
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[69] | 299 | const uint32_t seed = 0; |
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| 300 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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[55] | 301 | srand(seed); |
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| 302 | |
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[69] | 303 | Tcontext_t _ooo_engine_id [nb_request]; |
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[55] | 304 | Tcontrol_t _read_ra [nb_request]; |
---|
| 305 | Tgeneral_address_t _num_reg_ra [nb_request]; |
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| 306 | Tcontrol_t _read_rb [nb_request]; |
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| 307 | Tgeneral_address_t _num_reg_rb [nb_request]; |
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| 308 | Tcontrol_t _read_rc [nb_request]; |
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| 309 | Tspecial_address_t _num_reg_rc [nb_request]; |
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| 310 | |
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| 311 | // emulation of registerFile |
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[69] | 312 | Tcontrol_t _gpr_val [_param->_nb_general_register][_param->_nb_ooo_engine]; |
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| 313 | Tgeneral_data_t _gpr [_param->_nb_general_register][_param->_nb_ooo_engine]; |
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| 314 | Tcontrol_t _spr_val [_param->_nb_special_register][_param->_nb_ooo_engine]; |
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| 315 | Tspecial_data_t _spr [_param->_nb_special_register][_param->_nb_ooo_engine]; |
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[55] | 316 | |
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| 317 | SC_START(0); |
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| 318 | |
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| 319 | LABEL("Initialisation"); |
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[69] | 320 | in_INSERT_VAL ->write(0); |
---|
| 321 | for (uint32_t i=0; i<_param->_nb_inst_retire ; i++) |
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| 322 | in_RETIRE_ACK [i]->write(0); |
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[55] | 323 | for (uint32_t i=0; i<_param->_nb_gpr_write ; i++) |
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| 324 | in_GPR_WRITE_VAL [i]->write(0); |
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| 325 | for (uint32_t i=0; i<_param->_nb_spr_write ; i++) |
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| 326 | in_SPR_WRITE_VAL [i]->write(0); |
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| 327 | for (uint32_t i=0; i<_param->_nb_bypass_write ; i++) |
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| 328 | { |
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| 329 | in_BYPASS_WRITE_GPR_VAL [i]->write(0); |
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| 330 | in_BYPASS_WRITE_SPR_VAL [i]->write(0); |
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| 331 | } |
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| 332 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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| 333 | in_BYPASS_MEMORY_VAL [i]->write(0); |
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| 334 | |
---|
| 335 | in_NRESET->write(0); |
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| 336 | SC_START(5); |
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| 337 | in_NRESET->write(1); |
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| 338 | |
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| 339 | LABEL("Loop of Test"); |
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| 340 | |
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| 341 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 342 | { |
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| 343 | LABEL("Iteration "+toString(iteration)); |
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| 344 | |
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| 345 | int32_t percent_transaction_queue_in = (rand()%50)+25; |
---|
| 346 | int32_t percent_transaction_queue_out = (rand()%50)+25; |
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| 347 | int32_t percent_registerfile_valid = (rand()%50)+25; |
---|
| 348 | int32_t percent_transaction_registerfile = (rand()%50)+25; |
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| 349 | int32_t percent_transaction_bypass = (rand()%50)+25; |
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| 350 | |
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| 351 | LABEL("Initialisation"); |
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| 352 | |
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| 353 | for (uint32_t i=0; i<nb_request; i++) |
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| 354 | { |
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[69] | 355 | _ooo_engine_id [i] = rand()% _param->_nb_ooo_engine ; |
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[55] | 356 | _read_ra [i] = rand()% 2 ; |
---|
| 357 | _num_reg_ra [i] = rand()% _param->_nb_general_register ; |
---|
| 358 | _read_rb [i] = rand()% 2 ; |
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| 359 | _num_reg_rb [i] = rand()% _param->_nb_general_register ; |
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| 360 | _read_rc [i] = rand()% 2 ; |
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| 361 | _num_reg_rc [i] = rand()% _param->_nb_special_register ; |
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| 362 | } |
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| 363 | |
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| 364 | // emulation of registerFile |
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[69] | 365 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
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[55] | 366 | { |
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| 367 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
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| 368 | { |
---|
| 369 | _gpr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
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[69] | 370 | _gpr [i][j] = rand()%((1<<_param->_size_general_data)-1); |
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[55] | 371 | } |
---|
| 372 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
| 373 | { |
---|
| 374 | _spr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
---|
| 375 | _spr [i][j] = rand()%(1<<_param->_size_special_data); |
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| 376 | } |
---|
| 377 | } |
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| 378 | // End initialisation ....... |
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| 379 | |
---|
| 380 | uint32_t request_in = 0; |
---|
| 381 | uint32_t request_out = 0; |
---|
| 382 | bool request_out_wait [nb_request]; |
---|
| 383 | |
---|
| 384 | for (uint32_t i=0; i<nb_request; i++) |
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| 385 | request_out_wait [i] = true; |
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[69] | 386 | |
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| 387 | bool can_gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register]; |
---|
| 388 | bool can_spr_use [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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| 389 | bool need_gpr [_param->_nb_ooo_engine][_param->_nb_general_register]; |
---|
| 390 | bool need_spr [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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[55] | 391 | |
---|
[69] | 392 | |
---|
| 393 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
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| 394 | { |
---|
| 395 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
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| 396 | need_gpr [j][i] = false; |
---|
| 397 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
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| 398 | need_spr [j][i] = false; |
---|
| 399 | } |
---|
| 400 | |
---|
[55] | 401 | while (request_out < nb_request) |
---|
| 402 | { |
---|
[69] | 403 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
---|
[55] | 404 | { |
---|
[69] | 405 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
| 406 | can_gpr_use [j][i] = true; |
---|
| 407 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
| 408 | can_spr_use [j][i] = true; |
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[55] | 409 | } |
---|
[69] | 410 | |
---|
| 411 | Tcontrol_t insert_val = (request_in < nb_request) and ((rand()%100) < percent_transaction_queue_in); |
---|
| 412 | Tcontext_t insert_ooo_engine_id; |
---|
| 413 | Tgeneral_address_t insert_num_reg_ra; |
---|
| 414 | Tgeneral_address_t insert_num_reg_rb; |
---|
| 415 | Tspecial_address_t insert_num_reg_rc; |
---|
| 416 | |
---|
| 417 | in_INSERT_VAL ->write(insert_val); |
---|
| 418 | if (insert_val) |
---|
[55] | 419 | { |
---|
[69] | 420 | bool data_val; |
---|
| 421 | insert_ooo_engine_id = _ooo_engine_id [request_in]; |
---|
| 422 | insert_num_reg_ra = _num_reg_ra [request_in]; |
---|
| 423 | insert_num_reg_rb = _num_reg_rb [request_in]; |
---|
| 424 | insert_num_reg_rc = _num_reg_rc [request_in]; |
---|
[55] | 425 | |
---|
[69] | 426 | if (_param->_have_port_context_id) |
---|
| 427 | in_INSERT_CONTEXT_ID ->write((2*insert_ooo_engine_id)%_param->_nb_context ); |
---|
| 428 | if (_param->_have_port_front_end_id) |
---|
| 429 | in_INSERT_FRONT_END_ID ->write((3*insert_ooo_engine_id)%_param->_nb_front_end); |
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| 430 | if (_param->_have_port_ooo_engine_id) |
---|
| 431 | in_INSERT_OOO_ENGINE_ID ->write(insert_ooo_engine_id); |
---|
| 432 | if (_param->_have_port_rob_id) |
---|
| 433 | in_INSERT_ROB_ID ->write(request_in); |
---|
| 434 | in_INSERT_OPERATION ->write(0); |
---|
| 435 | in_INSERT_TYPE ->write(0); |
---|
| 436 | in_INSERT_HAS_IMMEDIAT->write(0); |
---|
| 437 | in_INSERT_IMMEDIAT ->write(0); |
---|
| 438 | // in_INSERT_READ_RA ->write(_read_ra[request_in]); |
---|
| 439 | data_val = not(_read_ra[request_in]) or _gpr_val[insert_num_reg_ra][insert_ooo_engine_id]; |
---|
[55] | 440 | |
---|
[69] | 441 | need_gpr [insert_ooo_engine_id][insert_num_reg_ra] |= not data_val; |
---|
[55] | 442 | |
---|
[69] | 443 | in_INSERT_NUM_REG_RA ->write(insert_num_reg_ra); |
---|
| 444 | in_INSERT_DATA_RA_VAL ->write(data_val); |
---|
| 445 | in_INSERT_DATA_RA ->write((data_val)?_gpr[insert_num_reg_ra][insert_ooo_engine_id]:0); |
---|
| 446 | // in_INSERT_READ_RB ->write(_read_rb[request_in]); |
---|
| 447 | data_val = not(_read_rb[request_in]) or _gpr_val[insert_num_reg_rb][insert_ooo_engine_id]; |
---|
| 448 | |
---|
| 449 | need_gpr [insert_ooo_engine_id][insert_num_reg_rb] |= not data_val; |
---|
| 450 | |
---|
| 451 | in_INSERT_NUM_REG_RB ->write(insert_num_reg_rb); |
---|
| 452 | in_INSERT_DATA_RB_VAL ->write(data_val); |
---|
| 453 | in_INSERT_DATA_RB ->write((data_val)?_gpr[insert_num_reg_rb][insert_ooo_engine_id]:0); |
---|
| 454 | // in_INSERT_READ_RC ->write(_read_rc[request_in]); |
---|
| 455 | data_val = not(_read_rc[request_in]) or _spr_val[insert_num_reg_rc][insert_ooo_engine_id]; |
---|
| 456 | |
---|
| 457 | need_spr [insert_ooo_engine_id][insert_num_reg_rc] |= not data_val; |
---|
| 458 | |
---|
| 459 | in_INSERT_NUM_REG_RC ->write(insert_num_reg_rc); |
---|
| 460 | in_INSERT_DATA_RC_VAL ->write(data_val); |
---|
| 461 | in_INSERT_DATA_RC ->write((data_val)?_spr[insert_num_reg_rc][insert_ooo_engine_id]:0); |
---|
| 462 | in_INSERT_WRITE_RD ->write(0); |
---|
| 463 | in_INSERT_NUM_REG_RD ->write(0); |
---|
| 464 | in_INSERT_WRITE_RE ->write(0); |
---|
| 465 | in_INSERT_NUM_REG_RE ->write(0); |
---|
| 466 | |
---|
| 467 | can_gpr_use [insert_ooo_engine_id][insert_num_reg_ra] = false; |
---|
| 468 | can_gpr_use [insert_ooo_engine_id][insert_num_reg_rb] = false; |
---|
| 469 | can_spr_use [insert_ooo_engine_id][insert_num_reg_rc] = false; |
---|
| 470 | } |
---|
| 471 | |
---|
| 472 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
---|
| 473 | in_RETIRE_ACK[i]->write((rand()%100)<percent_transaction_queue_out); |
---|
| 474 | |
---|
[55] | 475 | LABEL("Bypass Network :"); |
---|
| 476 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
| 477 | { |
---|
| 478 | Tgeneral_address_t num_reg = rand()% _param->_nb_general_register; |
---|
[69] | 479 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 480 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
| 481 | Tgeneral_data_t data = rand()%((1<<_param->_size_general_data)-1); |
---|
| 482 | |
---|
| 483 | val = (val and can_gpr_use [ooo_engine][num_reg] and need_gpr [ooo_engine][num_reg]); |
---|
[55] | 484 | |
---|
[69] | 485 | in_GPR_WRITE_VAL [i]->write(val); |
---|
| 486 | if (_param->_have_port_ooo_engine_id) |
---|
| 487 | in_GPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
| 488 | in_GPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
| 489 | in_GPR_WRITE_DATA [i]->write(data); |
---|
| 490 | |
---|
[55] | 491 | if (val) |
---|
| 492 | { |
---|
[69] | 493 | LABEL(" * GPR_WRITE ["+toString(i)+"] - gpr["+toString(num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(data)); |
---|
| 494 | can_gpr_use [ooo_engine][num_reg] = false; |
---|
| 495 | need_gpr [ooo_engine][num_reg] = false; |
---|
| 496 | |
---|
| 497 | |
---|
| 498 | _gpr [num_reg][ooo_engine] = data; |
---|
| 499 | _gpr_val [num_reg][ooo_engine] = 1; |
---|
[55] | 500 | } |
---|
| 501 | } |
---|
| 502 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
| 503 | { |
---|
| 504 | Tspecial_address_t num_reg = rand()% _param->_nb_special_register; |
---|
[69] | 505 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 506 | Tcontrol_t val = (_spr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
[55] | 507 | Tspecial_data_t data = rand()%(1<<_param->_size_special_data); |
---|
| 508 | |
---|
[69] | 509 | val = (val and can_spr_use [ooo_engine][num_reg] and need_spr[ooo_engine][num_reg]); |
---|
| 510 | |
---|
| 511 | in_SPR_WRITE_VAL [i]->write(val); |
---|
| 512 | if (_param->_have_port_ooo_engine_id) |
---|
| 513 | in_SPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
| 514 | in_SPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
| 515 | in_SPR_WRITE_DATA [i]->write(data); |
---|
| 516 | |
---|
[55] | 517 | if (val == 1) |
---|
| 518 | { |
---|
[69] | 519 | LABEL(" * SPR_WRITE ["+toString(i)+"] - spr["+toString(num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(data)); |
---|
| 520 | can_spr_use [ooo_engine][num_reg] = false; |
---|
| 521 | need_spr[ooo_engine][num_reg] = false; |
---|
| 522 | |
---|
| 523 | _spr [num_reg][ooo_engine] = data; |
---|
| 524 | _spr_val [num_reg][ooo_engine] = 1; |
---|
[55] | 525 | } |
---|
| 526 | } |
---|
| 527 | |
---|
| 528 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
---|
| 529 | { |
---|
[69] | 530 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 531 | if (_param->_have_port_ooo_engine_id) |
---|
| 532 | in_BYPASS_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
[55] | 533 | |
---|
| 534 | Tgeneral_address_t gpr_num_reg = rand()% _param->_nb_general_register; |
---|
[69] | 535 | Tcontrol_t gpr_val = (_gpr_val [gpr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
| 536 | Tgeneral_data_t gpr_data = rand()%((1<<_param->_size_general_data)-1); |
---|
[55] | 537 | |
---|
[69] | 538 | gpr_val = (gpr_val and can_gpr_use [ooo_engine][gpr_num_reg] and need_gpr[ooo_engine][gpr_num_reg]); |
---|
| 539 | |
---|
[55] | 540 | in_BYPASS_WRITE_GPR_VAL [i]->write(gpr_val); |
---|
| 541 | in_BYPASS_WRITE_GPR_NUM_REG[i]->write(gpr_num_reg); |
---|
| 542 | in_BYPASS_WRITE_GPR_DATA [i]->write(gpr_data); |
---|
| 543 | |
---|
| 544 | if (gpr_val) |
---|
| 545 | { |
---|
[69] | 546 | LABEL(" * BYPASS_WRITE ["+toString(i)+"] - gpr["+toString(gpr_num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(gpr_data)); |
---|
| 547 | can_gpr_use [ooo_engine][gpr_num_reg] = false; |
---|
| 548 | need_gpr[ooo_engine][gpr_num_reg] = false; |
---|
| 549 | |
---|
| 550 | _gpr [gpr_num_reg][ooo_engine] = gpr_data; |
---|
| 551 | _gpr_val [gpr_num_reg][ooo_engine] = 1; |
---|
[55] | 552 | } |
---|
| 553 | |
---|
| 554 | Tspecial_address_t spr_num_reg = rand()% _param->_nb_special_register; |
---|
[69] | 555 | Tcontrol_t spr_val = (_spr_val [spr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
[55] | 556 | Tspecial_data_t spr_data = rand()%(1<<_param->_size_special_data); |
---|
| 557 | |
---|
[69] | 558 | spr_val = (spr_val and can_spr_use [ooo_engine][spr_num_reg] and need_spr[ooo_engine][spr_num_reg]); |
---|
| 559 | |
---|
[55] | 560 | in_BYPASS_WRITE_SPR_VAL [i]->write(spr_val); |
---|
| 561 | in_BYPASS_WRITE_SPR_NUM_REG[i]->write(spr_num_reg); |
---|
| 562 | in_BYPASS_WRITE_SPR_DATA [i]->write(spr_data); |
---|
| 563 | |
---|
| 564 | if (spr_val) |
---|
| 565 | { |
---|
[69] | 566 | LABEL(" * BYPASS_WRITE ["+toString(i)+"] - spr["+toString(spr_num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(spr_data)); |
---|
| 567 | can_spr_use [ooo_engine][spr_num_reg] = false; |
---|
| 568 | need_spr[ooo_engine][spr_num_reg] = false; |
---|
| 569 | |
---|
| 570 | _spr [spr_num_reg][ooo_engine] = spr_data; |
---|
| 571 | _spr_val [spr_num_reg][ooo_engine] = 1; |
---|
[55] | 572 | } |
---|
| 573 | |
---|
| 574 | } |
---|
| 575 | |
---|
| 576 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
---|
| 577 | { |
---|
[69] | 578 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 579 | if (_param->_have_port_ooo_engine_id) |
---|
| 580 | in_BYPASS_MEMORY_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
[55] | 581 | |
---|
[69] | 582 | Tgeneral_address_t num_reg = rand()% _param->_nb_general_register; |
---|
| 583 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
| 584 | Tgeneral_data_t data = rand()%((1<<_param->_size_general_data)-1); |
---|
[55] | 585 | |
---|
[69] | 586 | val = (val and can_gpr_use [ooo_engine][num_reg] and need_gpr [ooo_engine][num_reg]); |
---|
[55] | 587 | |
---|
[69] | 588 | in_BYPASS_MEMORY_VAL [i]->write(val); |
---|
| 589 | in_BYPASS_MEMORY_NUM_REG[i]->write(num_reg); |
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| 590 | in_BYPASS_MEMORY_DATA [i]->write(data); |
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| 591 | |
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| 592 | if (val) |
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[55] | 593 | { |
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[69] | 594 | LABEL(" * BYPASS_MEMORY ["+toString(i)+"] - gpr["+toString(num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(data)); |
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| 595 | can_gpr_use [ooo_engine][num_reg] = false; |
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| 596 | need_gpr [ooo_engine][num_reg] = false; |
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| 597 | |
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| 598 | _gpr [num_reg][ooo_engine] = data; |
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| 599 | _gpr_val [num_reg][ooo_engine] = 1; |
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[55] | 600 | } |
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| 601 | } |
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| 602 | SC_START(0); // to mealy function |
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| 603 | |
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[69] | 604 | // LABEL("Test INSERT : "+toString(in_INSERT_VAL->read())+","+toString(out_INSERT_ACK->read())); |
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| 605 | if (( in_INSERT_VAL->read() == 1) and |
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| 606 | (out_INSERT_ACK->read() == 1)) |
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[55] | 607 | { |
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[69] | 608 | LABEL("Accepted INSERT number : "+toString(request_in)); |
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[55] | 609 | request_in ++; |
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| 610 | } |
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| 611 | |
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[69] | 612 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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[55] | 613 | { |
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[69] | 614 | LABEL("Test RETIRE "+toString(i)+" : "+toString(out_RETIRE_VAL[i]->read())+","+toString(in_RETIRE_ACK[i]->read())); |
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| 615 | if ((out_RETIRE_VAL [i]->read() == 1) and |
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| 616 | ( in_RETIRE_ACK [i]->read() == 1)) |
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[55] | 617 | { |
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[69] | 618 | Tpacket_t rob_id; |
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| 619 | if (_param->_have_port_rob_id) |
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| 620 | rob_id = out_RETIRE_ROB_ID [i]->read(); |
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| 621 | else |
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| 622 | rob_id = 0; |
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| 623 | LABEL("Accepted RETIRE ["+toString(i)+"] number : "+toString(rob_id)+", request number : "+toString(request_out)); |
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| 624 | TEST(bool, request_out_wait [rob_id] , true); |
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[55] | 625 | |
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| 626 | request_out ++; |
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[69] | 627 | request_out_wait [rob_id] = false; |
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[55] | 628 | |
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[69] | 629 | Tcontext_t ooo_engine_id = _ooo_engine_id [rob_id]; |
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[55] | 630 | |
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[69] | 631 | if (_param->_have_port_context_id) |
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| 632 | TEST(Tcontext_t ,out_RETIRE_CONTEXT_ID [i]->read(),(2*ooo_engine_id)%_param->_nb_context ); |
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| 633 | if (_param->_have_port_front_end_id) |
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| 634 | TEST(Tcontext_t ,out_RETIRE_FRONT_END_ID [i]->read(),(3*ooo_engine_id)%_param->_nb_front_end); |
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| 635 | if (_param->_have_port_ooo_engine_id) |
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| 636 | TEST(Tcontext_t ,out_RETIRE_OOO_ENGINE_ID[i]->read(),ooo_engine_id); |
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| 637 | |
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| 638 | if (_read_ra [rob_id]) |
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| 639 | TEST(Tgeneral_data_t ,out_RETIRE_DATA_RA [i]->read(),_gpr[_num_reg_ra[rob_id]][ooo_engine_id]); |
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[55] | 640 | |
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[69] | 641 | if (_read_rb [rob_id]) |
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| 642 | TEST(Tgeneral_data_t ,out_RETIRE_DATA_RB [i]->read(),_gpr[_num_reg_rb[rob_id]][ooo_engine_id]); |
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[55] | 643 | |
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[69] | 644 | if (_read_rc [rob_id]) |
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| 645 | TEST(Tspecial_data_t ,out_RETIRE_DATA_RC [i]->read(),_spr[_num_reg_rc[rob_id]][ooo_engine_id]); |
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| 646 | |
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| 647 | // need_gpr [ooo_engine_id][_num_reg_ra[rob_id]]= true; |
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| 648 | // need_gpr [ooo_engine_id][_num_reg_rb[rob_id]]= true; |
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| 649 | // need_spr [ooo_engine_id][_num_reg_rc[rob_id]]= true; |
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[55] | 650 | } |
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| 651 | } |
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| 652 | |
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| 653 | SC_START(1); |
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| 654 | } |
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| 655 | } |
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| 656 | |
---|
| 657 | /******************************************************** |
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| 658 | * Simulation - End |
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| 659 | ********************************************************/ |
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| 660 | |
---|
| 661 | TEST_OK ("End of Simulation"); |
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| 662 | delete _time; |
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| 663 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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| 664 | |
---|
| 665 | delete in_CLOCK ; |
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| 666 | delete in_NRESET; |
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| 667 | |
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[69] | 668 | delete in_INSERT_VAL ; |
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| 669 | delete out_INSERT_ACK ; |
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| 670 | if (_param->_have_port_context_id) |
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| 671 | delete in_INSERT_CONTEXT_ID ; |
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| 672 | if (_param->_have_port_front_end_id) |
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| 673 | delete in_INSERT_FRONT_END_ID ; |
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| 674 | if (_param->_have_port_ooo_engine_id) |
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| 675 | delete in_INSERT_OOO_ENGINE_ID ; |
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| 676 | if (_param->_have_port_rob_id) |
---|
| 677 | delete in_INSERT_ROB_ID ; |
---|
| 678 | delete in_INSERT_OPERATION ; |
---|
| 679 | delete in_INSERT_TYPE ; |
---|
| 680 | delete in_INSERT_HAS_IMMEDIAT; |
---|
| 681 | delete in_INSERT_IMMEDIAT ; |
---|
| 682 | //delete in_INSERT_READ_RA ; |
---|
| 683 | delete in_INSERT_NUM_REG_RA ; |
---|
| 684 | delete in_INSERT_DATA_RA_VAL ; |
---|
| 685 | delete in_INSERT_DATA_RA ; |
---|
| 686 | //delete in_INSERT_READ_RB ; |
---|
| 687 | delete in_INSERT_NUM_REG_RB ; |
---|
| 688 | delete in_INSERT_DATA_RB_VAL ; |
---|
| 689 | delete in_INSERT_DATA_RB ; |
---|
| 690 | //delete in_INSERT_READ_RC ; |
---|
| 691 | delete in_INSERT_NUM_REG_RC ; |
---|
| 692 | delete in_INSERT_DATA_RC_VAL ; |
---|
| 693 | delete in_INSERT_DATA_RC ; |
---|
| 694 | delete in_INSERT_WRITE_RD ; |
---|
| 695 | delete in_INSERT_NUM_REG_RD ; |
---|
| 696 | delete in_INSERT_WRITE_RE ; |
---|
| 697 | delete in_INSERT_NUM_REG_RE ; |
---|
[55] | 698 | |
---|
[69] | 699 | delete [] out_RETIRE_VAL ; |
---|
| 700 | delete [] in_RETIRE_ACK ; |
---|
| 701 | if (_param->_have_port_context_id) |
---|
| 702 | delete [] out_RETIRE_CONTEXT_ID ; |
---|
| 703 | if (_param->_have_port_front_end_id) |
---|
| 704 | delete [] out_RETIRE_FRONT_END_ID; |
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| 705 | if (_param->_have_port_ooo_engine_id) |
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| 706 | delete [] out_RETIRE_OOO_ENGINE_ID ; |
---|
| 707 | if (_param->_have_port_rob_id) |
---|
| 708 | delete [] out_RETIRE_ROB_ID ; |
---|
| 709 | delete [] out_RETIRE_OPERATION ; |
---|
| 710 | delete [] out_RETIRE_TYPE ; |
---|
| 711 | delete [] out_RETIRE_HAS_IMMEDIAT; |
---|
| 712 | delete [] out_RETIRE_IMMEDIAT ; |
---|
| 713 | delete [] out_RETIRE_DATA_RA ; |
---|
| 714 | delete [] out_RETIRE_DATA_RB ; |
---|
| 715 | delete [] out_RETIRE_DATA_RC ; |
---|
| 716 | delete [] out_RETIRE_WRITE_RD ; |
---|
| 717 | delete [] out_RETIRE_NUM_REG_RD ; |
---|
| 718 | delete [] out_RETIRE_WRITE_RE ; |
---|
| 719 | delete [] out_RETIRE_NUM_REG_RE ; |
---|
[55] | 720 | |
---|
| 721 | delete [] in_GPR_WRITE_VAL ; |
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[69] | 722 | if (_param->_have_port_ooo_engine_id) |
---|
| 723 | delete [] in_GPR_WRITE_OOO_ENGINE_ID; |
---|
[55] | 724 | delete [] in_GPR_WRITE_NUM_REG ; |
---|
| 725 | delete [] in_GPR_WRITE_DATA ; |
---|
| 726 | |
---|
| 727 | delete [] in_SPR_WRITE_VAL ; |
---|
[69] | 728 | if (_param->_have_port_ooo_engine_id) |
---|
| 729 | delete [] in_SPR_WRITE_OOO_ENGINE_ID; |
---|
[55] | 730 | delete [] in_SPR_WRITE_NUM_REG ; |
---|
| 731 | delete [] in_SPR_WRITE_DATA ; |
---|
| 732 | |
---|
[69] | 733 | if (_param->_have_port_ooo_engine_id) |
---|
| 734 | delete [] in_BYPASS_WRITE_OOO_ENGINE_ID ; |
---|
[55] | 735 | delete [] in_BYPASS_WRITE_GPR_VAL ; |
---|
| 736 | delete [] in_BYPASS_WRITE_GPR_NUM_REG; |
---|
| 737 | delete [] in_BYPASS_WRITE_GPR_DATA ; |
---|
| 738 | delete [] in_BYPASS_WRITE_SPR_VAL ; |
---|
| 739 | delete [] in_BYPASS_WRITE_SPR_NUM_REG; |
---|
| 740 | delete [] in_BYPASS_WRITE_SPR_DATA ; |
---|
| 741 | |
---|
| 742 | delete [] in_BYPASS_MEMORY_VAL ; |
---|
[69] | 743 | if (_param->_have_port_ooo_engine_id) |
---|
| 744 | delete [] in_BYPASS_MEMORY_OOO_ENGINE_ID; |
---|
[55] | 745 | delete [] in_BYPASS_MEMORY_NUM_REG ; |
---|
| 746 | delete [] in_BYPASS_MEMORY_DATA ; |
---|
| 747 | #endif |
---|
| 748 | |
---|
| 749 | delete _Reservation_station; |
---|
| 750 | #ifdef STATISTICS |
---|
| 751 | delete _parameters_statistics; |
---|
| 752 | #endif |
---|
| 753 | } |
---|