1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Reservation_station_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h" |
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10 | #include "Behavioural/include/Allocation.h" |
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11 | |
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12 | namespace morpheo { |
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13 | namespace behavioural { |
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14 | namespace core { |
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15 | namespace multi_execute_loop { |
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16 | namespace execute_loop { |
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17 | namespace multi_read_unit { |
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18 | namespace read_unit { |
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19 | namespace reservation_station { |
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20 | |
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21 | |
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22 | |
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23 | #undef FUNCTION |
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24 | #define FUNCTION "Reservation_station::allocation" |
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25 | void Reservation_station::allocation (void) |
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26 | { |
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27 | log_printf(FUNC,Reservation_station,FUNCTION,"Begin"); |
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28 | |
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29 | _component = new Component (_usage); |
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30 | |
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31 | Entity * entity = _component->set_entity (_name |
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32 | ,"Reservation_station" |
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33 | #ifdef POSITION |
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34 | ,COMBINATORY |
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35 | #endif |
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36 | ); |
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37 | |
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38 | _interfaces = entity->set_interfaces(); |
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39 | |
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40 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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41 | |
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42 | Interface * interface = _interfaces->set_interface("" |
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43 | #ifdef POSITION |
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44 | ,IN |
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45 | ,SOUTH, |
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46 | _("Generalist interface") |
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47 | #endif |
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48 | ); |
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49 | |
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50 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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51 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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52 | |
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53 | // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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54 | { |
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55 | ALLOC0_INTERFACE_BEGIN("insert",IN,EAST,_("Input of reservation_station")); |
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56 | |
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57 | ALLOC0_VALACK_IN ( in_INSERT_VAL ,VAL); |
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58 | ALLOC0_VALACK_OUT(out_INSERT_ACK ,ACK); |
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59 | ALLOC0_SIGNAL_IN ( in_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); |
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60 | ALLOC0_SIGNAL_IN ( in_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); |
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61 | ALLOC0_SIGNAL_IN ( in_INSERT_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); |
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62 | ALLOC0_SIGNAL_IN ( in_INSERT_ROB_ID ,"rob_id" ,Tpacket_t ,_param->_size_rob_ptr ); |
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63 | ALLOC0_SIGNAL_IN ( in_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); |
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64 | ALLOC0_SIGNAL_IN ( in_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); |
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65 | ALLOC0_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); |
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66 | ALLOC0_SIGNAL_IN ( in_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); |
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67 | ALLOC0_SIGNAL_IN ( in_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); |
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68 | ALLOC0_SIGNAL_IN ( in_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); |
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69 | // ALLOC0_SIGNAL_IN ( in_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); |
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70 | ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); |
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71 | ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RA_VAL ,"data_ra_val" ,Tcontrol_t ,1 ); |
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72 | ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data ); |
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73 | // ALLOC0_SIGNAL_IN ( in_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); |
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74 | ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); |
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75 | ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RB_VAL ,"data_rb_val" ,Tcontrol_t ,1 ); |
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76 | ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data ); |
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77 | // ALLOC0_SIGNAL_IN ( in_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); |
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78 | ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); |
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79 | ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RC_VAL ,"data_rc_val" ,Tcontrol_t ,1 ); |
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80 | ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); |
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81 | ALLOC0_SIGNAL_IN ( in_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); |
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82 | ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); |
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83 | ALLOC0_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); |
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84 | ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); |
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85 | |
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86 | ALLOC0_INTERFACE_END(); |
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87 | } |
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88 | |
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89 | // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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90 | { |
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91 | ALLOC1_INTERFACE_BEGIN("retire",OUT,WEST,_("Output of reservation_station"),_param->_nb_inst_retire); |
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92 | |
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93 | ALLOC1_VALACK_OUT(out_RETIRE_VAL ,VAL); |
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94 | ALLOC1_VALACK_IN ( in_RETIRE_ACK ,ACK); |
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95 | ALLOC1_SIGNAL_OUT(out_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); |
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96 | ALLOC1_SIGNAL_OUT(out_RETIRE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); |
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97 | ALLOC1_SIGNAL_OUT(out_RETIRE_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id); |
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98 | ALLOC1_SIGNAL_OUT(out_RETIRE_ROB_ID ,"rob_id" ,Tpacket_t ,_param->_size_rob_ptr); |
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99 | ALLOC1_SIGNAL_OUT(out_RETIRE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation); |
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100 | ALLOC1_SIGNAL_OUT(out_RETIRE_TYPE ,"type" ,Ttype_t ,_param->_size_type); |
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101 | ALLOC1_SIGNAL_OUT(out_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); |
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102 | ALLOC1_SIGNAL_OUT(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); |
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103 | ALLOC1_SIGNAL_OUT(out_RETIRE_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1); |
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104 | ALLOC1_SIGNAL_OUT(out_RETIRE_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data); |
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105 | ALLOC1_SIGNAL_OUT(out_RETIRE_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data); |
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106 | ALLOC1_SIGNAL_OUT(out_RETIRE_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data); |
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107 | ALLOC1_SIGNAL_OUT(out_RETIRE_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data); |
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108 | ALLOC1_SIGNAL_OUT(out_RETIRE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1); |
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109 | ALLOC1_SIGNAL_OUT(out_RETIRE_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); |
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110 | ALLOC1_SIGNAL_OUT(out_RETIRE_WRITE_RE ,"write_re" ,Tcontrol_t ,1); |
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111 | ALLOC1_SIGNAL_OUT(out_RETIRE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); |
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112 | |
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113 | ALLOC1_INTERFACE_END(_param->_nb_inst_retire); |
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114 | } |
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115 | |
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116 | // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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117 | { |
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118 | ALLOC1_INTERFACE_BEGIN("gpr_write",IN,SOUTH,_("Interface with write queue to bypass the write in the RegisterFile."),_param->_nb_gpr_write); |
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119 | |
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120 | ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL ,VAL); |
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121 | ALLOC1_SIGNAL_IN ( in_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); |
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122 | ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); |
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123 | ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); |
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124 | |
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125 | ALLOC1_INTERFACE_END(_param->_nb_gpr_write); |
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126 | } |
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127 | |
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128 | // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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129 | { |
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130 | ALLOC1_INTERFACE_BEGIN("spr_write",IN,SOUTH,_("Interface with write queue to bypass the write in the RegisterFile."),_param->_nb_spr_write); |
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131 | |
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132 | ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL ,VAL); |
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133 | ALLOC1_SIGNAL_IN ( in_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); |
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134 | ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); |
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135 | ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); |
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136 | |
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137 | ALLOC1_INTERFACE_END(_param->_nb_spr_write); |
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138 | } |
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139 | |
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140 | // ~~~~~[ Interface : "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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141 | { |
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142 | ALLOC1_INTERFACE_BEGIN("bypass_write",IN,NORTH,_("Interface with write queue to bypass the write in the RegisterFile."),_param->_nb_bypass_write); |
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143 | |
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144 | ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); |
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145 | ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1); |
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146 | ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_register); |
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147 | ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_data); |
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148 | ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1); |
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149 | ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register); |
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150 | ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data); |
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151 | |
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152 | ALLOC1_INTERFACE_END(_param->_nb_bypass_write); |
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153 | } |
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154 | |
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155 | // ~~~~~[ Interface : "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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156 | { |
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157 | ALLOC1_INTERFACE_BEGIN("bypass_memory",IN,NORTH,_("Interface with load/store unit to bypass the write in the RegisterFile."),_param->_nb_bypass_memory); |
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158 | |
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159 | ALLOC1_VALACK_IN ( in_BYPASS_MEMORY_VAL ,VAL); |
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160 | ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); |
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161 | ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); |
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162 | ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); |
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163 | |
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164 | ALLOC1_INTERFACE_END(_param->_nb_bypass_memory); |
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165 | } |
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166 | |
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167 | if (usage_is_set(_usage,USE_SYSTEMC)) |
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168 | { |
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169 | // ~~~~~[ internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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170 | ALLOC1(internal_RETIRE_VAL ,Tcontrol_t,_param->_nb_inst_retire); |
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171 | ALLOC1(internal_RETIRE_SLOT,uint32_t ,_param->_nb_inst_retire); |
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172 | } |
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173 | |
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174 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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175 | |
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176 | #ifdef POSITION |
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177 | if (usage_is_set(_usage,USE_POSITION)) |
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178 | _component->generate_file(); |
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179 | #endif |
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180 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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181 | _queue_valid = new bool [_param->_size_queue]; |
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182 | #else |
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183 | _queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control::Queue_Control(_param->_size_queue); |
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184 | #endif |
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185 | _queue = new Treservation_station_entry_t [_param->_size_queue]; |
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186 | |
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187 | log_printf(FUNC,Reservation_station,FUNCTION,"End"); |
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188 | }; |
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189 | |
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190 | }; // end namespace reservation_station |
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191 | }; // end namespace read_unit |
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192 | }; // end namespace multi_read_unit |
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193 | }; // end namespace execute_loop |
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194 | }; // end namespace multi_execute_loop |
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195 | }; // end namespace core |
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196 | |
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197 | }; // end namespace behavioural |
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198 | }; // end namespace morpheo |
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199 | #endif |
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