Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp
- Timestamp:
- Mar 18, 2009, 11:36:26 PM (15 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp
r97 r112 8 8 9 9 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h" 10 #include "Behavioural/include/Allocation.h" 10 11 11 12 namespace morpheo { … … 43 44 ,IN 44 45 ,SOUTH, 45 "Generalist interface"46 _("Generalist interface") 46 47 #endif 47 48 ); … … 50 51 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 51 52 52 // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~ 53 { 54 Interface_fifo * interface = _interfaces->set_interface("insert" 55 #ifdef POSITION 56 ,IN 57 ,EAST 58 ,"Input of reservation_station" 59 #endif 60 ); 61 62 in_INSERT_VAL = interface->set_signal_valack_in (VAL); 63 out_INSERT_ACK = interface->set_signal_valack_out (ACK); 64 if (_param->_have_port_context_id) 65 in_INSERT_CONTEXT_ID = interface->set_signal_in <Tcontext_t > ("context_id" ,_param->_size_context_id ); 66 if (_param->_have_port_front_end_id) 67 in_INSERT_FRONT_END_ID = interface->set_signal_in <Tcontext_t > ("front_end_id" ,_param->_size_front_end_id ); 68 if (_param->_have_port_ooo_engine_id) 69 in_INSERT_OOO_ENGINE_ID = interface->set_signal_in <Tcontext_t > ("ooo_engine_id" ,_param->_size_ooo_engine_id ); 70 if (_param->_have_port_rob_ptr) 71 in_INSERT_ROB_ID = interface->set_signal_in <Tpacket_t > ("rob_id" ,_param->_size_rob_ptr ); 72 in_INSERT_OPERATION = interface->set_signal_in <Toperation_t > ("operation" ,_param->_size_operation ); 73 in_INSERT_TYPE = interface->set_signal_in <Ttype_t > ("type" ,_param->_size_type ); 74 in_INSERT_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t> ("store_queue_ptr_write" ,_param->_size_store_queue_ptr); 75 if (_param->_have_port_load_queue_ptr) 76 in_INSERT_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t> ("load_queue_ptr_write" ,_param->_size_load_queue_ptr ); 77 in_INSERT_HAS_IMMEDIAT = interface->set_signal_in <Tcontrol_t > ("has_immediat" ,1 ); 78 in_INSERT_IMMEDIAT = interface->set_signal_in <Tgeneral_data_t > ("immediat" ,_param->_size_general_data ); 79 // in_INSERT_READ_RA = interface->set_signal_in <Tcontrol_t > ("read_ra" ,1 ); 80 in_INSERT_NUM_REG_RA = interface->set_signal_in <Tgeneral_address_t> ("num_reg_ra" ,_param->_size_general_register ); 81 in_INSERT_DATA_RA_VAL = interface->set_signal_in <Tcontrol_t > ("data_ra_val" ,1 ); 82 in_INSERT_DATA_RA = interface->set_signal_in <Tgeneral_data_t > ("data_ra" ,_param->_size_general_data ); 83 // in_INSERT_READ_RB = interface->set_signal_in <Tcontrol_t > ("read_rb" ,1 ); 84 in_INSERT_NUM_REG_RB = interface->set_signal_in <Tgeneral_address_t> ("num_reg_rb" ,_param->_size_general_register ); 85 in_INSERT_DATA_RB_VAL = interface->set_signal_in <Tcontrol_t > ("data_rb_val" ,1 ); 86 in_INSERT_DATA_RB = interface->set_signal_in <Tgeneral_data_t > ("data_rb" ,_param->_size_general_data ); 87 // in_INSERT_READ_RC = interface->set_signal_in <Tcontrol_t > ("read_rc" ,1 ); 88 in_INSERT_NUM_REG_RC = interface->set_signal_in <Tspecial_address_t> ("num_reg_rc" ,_param->_size_special_register ); 89 in_INSERT_DATA_RC_VAL = interface->set_signal_in <Tcontrol_t > ("data_rc_val" ,1 ); 90 in_INSERT_DATA_RC = interface->set_signal_in <Tspecial_data_t > ("data_rc" ,_param->_size_special_data ); 91 in_INSERT_WRITE_RD = interface->set_signal_in <Tcontrol_t > ("write_rd" ,1 ); 92 in_INSERT_NUM_REG_RD = interface->set_signal_in <Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register ); 93 in_INSERT_WRITE_RE = interface->set_signal_in <Tcontrol_t > ("write_re" ,1 ); 94 in_INSERT_NUM_REG_RE = interface->set_signal_in <Tspecial_address_t> ("num_reg_re" ,_param->_size_special_register ); 53 // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~ 54 { 55 ALLOC0_INTERFACE_BEGIN("insert",IN,EAST,_("Input of reservation_station")); 56 57 ALLOC0_VALACK_IN ( in_INSERT_VAL ,VAL); 58 ALLOC0_VALACK_OUT(out_INSERT_ACK ,ACK); 59 ALLOC0_SIGNAL_IN ( in_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 60 ALLOC0_SIGNAL_IN ( in_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 61 ALLOC0_SIGNAL_IN ( in_INSERT_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); 62 ALLOC0_SIGNAL_IN ( in_INSERT_ROB_ID ,"rob_id" ,Tpacket_t ,_param->_size_rob_ptr ); 63 ALLOC0_SIGNAL_IN ( in_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 64 ALLOC0_SIGNAL_IN ( in_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 65 ALLOC0_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 66 ALLOC0_SIGNAL_IN ( in_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 67 ALLOC0_SIGNAL_IN ( in_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 68 ALLOC0_SIGNAL_IN ( in_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); 69 // ALLOC0_SIGNAL_IN ( in_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); 70 ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); 71 ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RA_VAL ,"data_ra_val" ,Tcontrol_t ,1 ); 72 ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data ); 73 // ALLOC0_SIGNAL_IN ( in_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); 74 ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); 75 ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RB_VAL ,"data_rb_val" ,Tcontrol_t ,1 ); 76 ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data ); 77 // ALLOC0_SIGNAL_IN ( in_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); 78 ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); 79 ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RC_VAL ,"data_rc_val" ,Tcontrol_t ,1 ); 80 ALLOC0_SIGNAL_IN ( in_INSERT_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); 81 ALLOC0_SIGNAL_IN ( in_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 82 ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); 83 ALLOC0_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 84 ALLOC0_SIGNAL_IN ( in_INSERT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); 85 86 ALLOC0_INTERFACE_END(); 87 } 88 89 // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~ 90 { 91 ALLOC1_INTERFACE_BEGIN("retire",OUT,WEST,_("Output of reservation_station"),_param->_nb_inst_retire); 92 93 ALLOC1_VALACK_OUT(out_RETIRE_VAL ,VAL); 94 ALLOC1_VALACK_IN ( in_RETIRE_ACK ,ACK); 95 ALLOC1_SIGNAL_OUT(out_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 96 ALLOC1_SIGNAL_OUT(out_RETIRE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); 97 ALLOC1_SIGNAL_OUT(out_RETIRE_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id); 98 ALLOC1_SIGNAL_OUT(out_RETIRE_ROB_ID ,"rob_id" ,Tpacket_t ,_param->_size_rob_ptr); 99 ALLOC1_SIGNAL_OUT(out_RETIRE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation); 100 ALLOC1_SIGNAL_OUT(out_RETIRE_TYPE ,"type" ,Ttype_t ,_param->_size_type); 101 ALLOC1_SIGNAL_OUT(out_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); 102 ALLOC1_SIGNAL_OUT(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 103 ALLOC1_SIGNAL_OUT(out_RETIRE_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1); 104 ALLOC1_SIGNAL_OUT(out_RETIRE_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data); 105 ALLOC1_SIGNAL_OUT(out_RETIRE_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data); 106 ALLOC1_SIGNAL_OUT(out_RETIRE_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data); 107 ALLOC1_SIGNAL_OUT(out_RETIRE_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data); 108 ALLOC1_SIGNAL_OUT(out_RETIRE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1); 109 ALLOC1_SIGNAL_OUT(out_RETIRE_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); 110 ALLOC1_SIGNAL_OUT(out_RETIRE_WRITE_RE ,"write_re" ,Tcontrol_t ,1); 111 ALLOC1_SIGNAL_OUT(out_RETIRE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); 112 113 ALLOC1_INTERFACE_END(_param->_nb_inst_retire); 114 } 115 116 // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 117 { 118 ALLOC1_INTERFACE_BEGIN("gpr_write",IN,SOUTH,_("Interface with write queue to bypass the write in the RegisterFile."),_param->_nb_gpr_write); 119 120 ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL ,VAL); 121 ALLOC1_SIGNAL_IN ( in_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); 122 ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); 123 ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); 124 125 ALLOC1_INTERFACE_END(_param->_nb_gpr_write); 95 126 } 96 127 97 // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~ 98 out_RETIRE_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_inst_retire]; 99 in_RETIRE_ACK = new SC_IN (Tcontrol_t ) * [_param->_nb_inst_retire]; 100 if (_param->_have_port_context_id) 101 out_RETIRE_CONTEXT_ID = new SC_OUT(Tcontext_t ) * [_param->_nb_inst_retire]; 102 if (_param->_have_port_front_end_id) 103 out_RETIRE_FRONT_END_ID = new SC_OUT(Tcontext_t ) * [_param->_nb_inst_retire]; 104 if (_param->_have_port_ooo_engine_id) 105 out_RETIRE_OOO_ENGINE_ID = new SC_OUT(Tcontext_t ) * [_param->_nb_inst_retire]; 106 if (_param->_have_port_rob_ptr) 107 out_RETIRE_ROB_ID = new SC_OUT(Tpacket_t ) * [_param->_nb_inst_retire]; 108 out_RETIRE_OPERATION = new SC_OUT(Toperation_t ) * [_param->_nb_inst_retire]; 109 out_RETIRE_TYPE = new SC_OUT(Ttype_t ) * [_param->_nb_inst_retire]; 110 out_RETIRE_STORE_QUEUE_PTR_WRITE = new SC_OUT(Tlsq_ptr_t ) * [_param->_nb_inst_retire]; 111 if (_param->_have_port_load_queue_ptr) 112 out_RETIRE_LOAD_QUEUE_PTR_WRITE = new SC_OUT(Tlsq_ptr_t ) * [_param->_nb_inst_retire]; 113 out_RETIRE_HAS_IMMEDIAT = new SC_OUT(Tcontrol_t ) * [_param->_nb_inst_retire]; 114 out_RETIRE_IMMEDIAT = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_inst_retire]; 115 out_RETIRE_DATA_RA = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_inst_retire]; 116 out_RETIRE_DATA_RB = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_inst_retire]; 117 out_RETIRE_DATA_RC = new SC_OUT(Tspecial_data_t ) * [_param->_nb_inst_retire]; 118 out_RETIRE_WRITE_RD = new SC_OUT(Tcontrol_t ) * [_param->_nb_inst_retire]; 119 out_RETIRE_NUM_REG_RD = new SC_OUT(Tgeneral_address_t) * [_param->_nb_inst_retire]; 120 out_RETIRE_WRITE_RE = new SC_OUT(Tcontrol_t ) * [_param->_nb_inst_retire]; 121 out_RETIRE_NUM_REG_RE = new SC_OUT(Tspecial_address_t) * [_param->_nb_inst_retire]; 122 123 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 124 { 125 Interface_fifo * interface = _interfaces->set_interface("retire_"+toString(i) 126 #ifdef POSITION 127 ,OUT 128 ,WEST 129 ,"Output of reservation_station" 130 #endif 131 ); 132 out_RETIRE_VAL [i] = interface->set_signal_valack_out(VAL); 133 in_RETIRE_ACK [i] = interface->set_signal_valack_in (ACK); 134 if (_param->_have_port_context_id) 135 out_RETIRE_CONTEXT_ID [i] = interface->set_signal_out<Tcontext_t > ("context_id" ,_param->_size_context_id); 136 if (_param->_have_port_front_end_id) 137 out_RETIRE_FRONT_END_ID [i] = interface->set_signal_out<Tcontext_t > ("front_end_id" ,_param->_size_front_end_id); 138 if (_param->_have_port_ooo_engine_id) 139 out_RETIRE_OOO_ENGINE_ID[i] = interface->set_signal_out<Tcontext_t > ("ooo_engine_id",_param->_size_ooo_engine_id); 140 if (_param->_have_port_rob_ptr) 141 out_RETIRE_ROB_ID [i] = interface->set_signal_out<Tpacket_t > ("rob_id" ,_param->_size_rob_ptr); 142 out_RETIRE_OPERATION [i] = interface->set_signal_out<Toperation_t > ("operation" ,_param->_size_operation); 143 out_RETIRE_TYPE [i] = interface->set_signal_out<Ttype_t > ("type" ,_param->_size_type); 144 out_RETIRE_STORE_QUEUE_PTR_WRITE [i] = interface->set_signal_out<Tlsq_ptr_t> ("store_queue_ptr_write" ,_param->_size_store_queue_ptr); 145 if (_param->_have_port_load_queue_ptr) 146 out_RETIRE_LOAD_QUEUE_PTR_WRITE [i] = interface->set_signal_out<Tlsq_ptr_t> ("load_queue_ptr_write" ,_param->_size_load_queue_ptr ); 128 // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 129 { 130 ALLOC1_INTERFACE_BEGIN("spr_write",IN,SOUTH,_("Interface with write queue to bypass the write in the RegisterFile."),_param->_nb_spr_write); 131 132 ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL ,VAL); 133 ALLOC1_SIGNAL_IN ( in_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); 134 ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); 135 ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); 147 136 148 out_RETIRE_HAS_IMMEDIAT [i] = interface->set_signal_out<Tcontrol_t > ("has_immediat" ,1); 149 out_RETIRE_IMMEDIAT [i] = interface->set_signal_out<Tgeneral_data_t > ("immediat" ,_param->_size_general_data); 150 out_RETIRE_DATA_RA [i] = interface->set_signal_out<Tgeneral_data_t > ("data_ra" ,_param->_size_general_data); 151 out_RETIRE_DATA_RB [i] = interface->set_signal_out<Tgeneral_data_t > ("data_rb" ,_param->_size_general_data); 152 out_RETIRE_DATA_RC [i] = interface->set_signal_out<Tspecial_data_t > ("data_rc" ,_param->_size_special_data); 153 out_RETIRE_WRITE_RD [i] = interface->set_signal_out<Tcontrol_t > ("write_rd" ,1); 154 out_RETIRE_NUM_REG_RD [i] = interface->set_signal_out<Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register); 155 out_RETIRE_WRITE_RE [i] = interface->set_signal_out<Tcontrol_t > ("write_re" ,1); 156 out_RETIRE_NUM_REG_RE [i] = interface->set_signal_out<Tspecial_address_t> ("num_reg_re" ,_param->_size_special_register); 157 } 137 ALLOC1_INTERFACE_END(_param->_nb_spr_write); 138 } 158 139 159 // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 160 in_GPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; 161 if (_param->_have_port_ooo_engine_id) 162 in_GPR_WRITE_OOO_ENGINE_ID= new SC_IN (Tcontext_t ) * [_param->_nb_gpr_write]; 163 in_GPR_WRITE_NUM_REG = new SC_IN (Tgeneral_address_t) * [_param->_nb_gpr_write]; 164 in_GPR_WRITE_DATA = new SC_IN (Tgeneral_data_t ) * [_param->_nb_gpr_write]; 140 // ~~~~~[ Interface : "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 141 { 142 ALLOC1_INTERFACE_BEGIN("bypass_write",IN,NORTH,_("Interface with write queue to bypass the write in the RegisterFile."),_param->_nb_bypass_write); 165 143 166 for (uint32_t i=0; i<_param->_nb_gpr_write; i++) 167 { 168 Interface_fifo * interface = _interfaces->set_interface("gpr_write_"+toString(i) 169 #ifdef POSITION 170 , IN 171 ,SOUTH 172 , "Interface with write queue to bypass the write in the RegisterFile." 173 #endif 174 ); 144 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); 145 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1); 146 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_register); 147 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_data); 148 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1); 149 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register); 150 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data); 151 152 ALLOC1_INTERFACE_END(_param->_nb_bypass_write); 153 } 154 155 // ~~~~~[ Interface : "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 156 { 157 ALLOC1_INTERFACE_BEGIN("bypass_memory",IN,NORTH,_("Interface with load/store unit to bypass the write in the RegisterFile."),_param->_nb_bypass_memory); 175 158 176 in_GPR_WRITE_VAL [i] = interface->set_signal_valack_in (VAL); 177 if (_param->_have_port_ooo_engine_id) 178 in_GPR_WRITE_OOO_ENGINE_ID [i] = interface->set_signal_in <Tcontext_t > ("ooo_engine_id",_param->_size_ooo_engine_id); 179 in_GPR_WRITE_NUM_REG [i] = interface->set_signal_in <Tgeneral_address_t> ("num_reg" ,_param->_size_general_register); 180 in_GPR_WRITE_DATA [i] = interface->set_signal_in <Tgeneral_data_t > ("data" ,_param->_size_general_data); 181 } 182 183 // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 184 in_SPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; 185 if (_param->_have_port_ooo_engine_id) 186 in_SPR_WRITE_OOO_ENGINE_ID= new SC_IN (Tcontext_t ) * [_param->_nb_spr_write]; 187 in_SPR_WRITE_NUM_REG = new SC_IN (Tspecial_address_t) * [_param->_nb_spr_write]; 188 in_SPR_WRITE_DATA = new SC_IN (Tspecial_data_t ) * [_param->_nb_spr_write]; 189 190 for (uint32_t i=0; i<_param->_nb_spr_write; i++) 191 { 192 Interface_fifo * interface = _interfaces->set_interface("spr_write_"+toString(i) 193 #ifdef POSITION 194 , IN 195 ,SOUTH 196 , "Interface with write queue to bypass the write in the RegisterFile." 197 #endif 198 ); 199 200 in_SPR_WRITE_VAL [i] = interface->set_signal_valack_in (VAL); 201 if (_param->_have_port_ooo_engine_id) 202 in_SPR_WRITE_OOO_ENGINE_ID [i] = interface->set_signal_in <Tcontext_t > ("ooo_engine_id",_param->_size_ooo_engine_id); 203 in_SPR_WRITE_NUM_REG [i] = interface->set_signal_in <Tspecial_address_t> ("num_reg" ,_param->_size_special_register); 204 in_SPR_WRITE_DATA [i] = interface->set_signal_in <Tspecial_data_t > ("data" ,_param->_size_special_data); 205 } 206 207 // ~~~~~[ Interface : "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 208 if (_param->_have_port_ooo_engine_id) 209 in_BYPASS_WRITE_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_bypass_write]; 210 in_BYPASS_WRITE_GPR_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_bypass_write]; 211 in_BYPASS_WRITE_GPR_NUM_REG = new SC_IN (Tgeneral_address_t) * [_param->_nb_bypass_write]; 212 in_BYPASS_WRITE_GPR_DATA = new SC_IN (Tgeneral_data_t ) * [_param->_nb_bypass_write]; 213 in_BYPASS_WRITE_SPR_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_bypass_write]; 214 in_BYPASS_WRITE_SPR_NUM_REG = new SC_IN (Tspecial_address_t) * [_param->_nb_bypass_write]; 215 in_BYPASS_WRITE_SPR_DATA = new SC_IN (Tspecial_data_t ) * [_param->_nb_bypass_write]; 216 217 for (uint32_t i=0; i<_param->_nb_bypass_write; i++) 218 { 219 Interface_fifo * interface = _interfaces->set_interface("bypass_write_"+toString(i) 220 #ifdef POSITION 221 , IN 222 ,NORTH 223 , "Interface with write queue to bypass the write in the RegisterFile." 224 #endif 225 ); 226 227 if (_param->_have_port_ooo_engine_id) 228 in_BYPASS_WRITE_OOO_ENGINE_ID [i] = interface->set_signal_in <Tcontext_t > ("ooo_engine_id" ,_param->_size_ooo_engine_id); 229 in_BYPASS_WRITE_GPR_VAL [i] = interface->set_signal_valack_in ("gpr_val",VAL); 230 in_BYPASS_WRITE_GPR_NUM_REG [i] = interface->set_signal_in <Tgeneral_address_t> ("gpr_num_reg" ,_param->_size_general_register); 231 in_BYPASS_WRITE_GPR_DATA [i] = interface->set_signal_in <Tgeneral_data_t > ("gpr_data" ,_param->_size_general_data); 232 in_BYPASS_WRITE_SPR_VAL [i] = interface->set_signal_valack_in ("spr_val",VAL); 233 in_BYPASS_WRITE_SPR_NUM_REG [i] = interface->set_signal_in <Tspecial_address_t> ("spr_num_reg" ,_param->_size_special_register); 234 in_BYPASS_WRITE_SPR_DATA [i] = interface->set_signal_in <Tspecial_data_t > ("spr_data" ,_param->_size_special_data); 235 } 236 237 // ~~~~~[ Interface : "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 238 in_BYPASS_MEMORY_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_bypass_memory]; 239 if (_param->_have_port_ooo_engine_id) 240 in_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_IN (Tcontext_t ) * [_param->_nb_bypass_memory]; 241 in_BYPASS_MEMORY_NUM_REG = new SC_IN (Tgeneral_address_t) * [_param->_nb_bypass_memory]; 242 in_BYPASS_MEMORY_DATA = new SC_IN (Tgeneral_data_t ) * [_param->_nb_bypass_memory]; 243 244 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 245 { 246 Interface_fifo * interface = _interfaces->set_interface("bypass_memory_"+toString(i) 247 #ifdef POSITION 248 , IN 249 , NORTH 250 , "Interface with load/store unit to bypass the write in the RegisterFile." 251 #endif 252 ); 253 254 in_BYPASS_MEMORY_VAL [i] = interface->set_signal_valack_in (VAL); 255 if (_param->_have_port_ooo_engine_id) 256 in_BYPASS_MEMORY_OOO_ENGINE_ID[i] = interface->set_signal_in <Tcontext_t > ("ooo_engine_id",_param->_size_ooo_engine_id); 257 in_BYPASS_MEMORY_NUM_REG [i] = interface->set_signal_in <Tgeneral_address_t> ("num_reg" ,_param->_size_general_register); 258 in_BYPASS_MEMORY_DATA [i] = interface->set_signal_in <Tgeneral_data_t > ("data" ,_param->_size_general_data); 259 } 260 159 ALLOC1_VALACK_IN ( in_BYPASS_MEMORY_VAL ,VAL); 160 ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); 161 ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); 162 ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); 163 164 ALLOC1_INTERFACE_END(_param->_nb_bypass_memory); 165 } 261 166 262 167 if (usage_is_set(_usage,USE_SYSTEMC)) 263 168 { 264 169 // ~~~~~[ internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 265 internal_RETIRE_VAL = new Tcontrol_t [_param->_nb_inst_retire];266 internal_RETIRE_SLOT = new uint32_t [_param->_nb_inst_retire];170 ALLOC1(internal_RETIRE_VAL ,Tcontrol_t,_param->_nb_inst_retire); 171 ALLOC1(internal_RETIRE_SLOT,uint32_t ,_param->_nb_inst_retire); 267 172 } 268 173
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