[73] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id: Execute_queue_vhdl_declaration.cpp 96 2008-12-16 19:36:25Z moulu $ |
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| 4 | * |
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[96] | 5 | * [ Description ] |
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[73] | 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_execute_loop { |
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| 15 | namespace execute_loop { |
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| 16 | namespace multi_write_unit { |
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| 17 | namespace write_unit { |
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| 18 | namespace execute_queue { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Execute_queue::vhdl_declaration" |
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| 23 | void Execute_queue::vhdl_declaration (Vhdl * & vhdl) |
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| 24 | { |
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| 25 | log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); |
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[96] | 26 | |
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| 27 | for (uint32_t i=0; i<_param->_size_queue; ++i) |
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| 28 | { |
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| 29 | if (_param->_have_port_context_id) |
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| 30 | vhdl->set_signal("reg_CONTEXT_ID_"+toString(i),_param->_size_context_id); |
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| 31 | if (_param->_have_port_front_end_id) |
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| 32 | vhdl->set_signal("reg_FRONT_END_ID_"+toString(i),_param->_size_front_end_id); |
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| 33 | if (_param->_have_port_ooo_engine_id) |
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| 34 | vhdl->set_signal("reg_OOO_ENGINE_ID_"+toString(i),_param->_size_ooo_engine_id); |
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| 35 | if (_param->_have_port_rob_ptr) |
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| 36 | vhdl->set_signal("reg_PACKET_ID_"+toString(i),_param->_size_rob_ptr); |
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| 37 | vhdl->set_signal("reg_FLAGS_"+toString(i),_param->_size_special_data); |
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| 38 | vhdl->set_signal("reg_EXCEPTION_"+toString(i),_param->_size_exception); |
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| 39 | vhdl->set_signal("reg_NO_SEQUENCE_"+toString(i),1); |
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| 40 | vhdl->set_signal("reg_ADDRESS_"+toString(i),_param->_size_instruction_address); |
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| 41 | vhdl->set_signal("reg_DATA_"+toString(i),_param->_size_general_data); |
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| 42 | } |
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| 43 | |
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| 44 | vhdl->set_signal("reg_CURRENT_STATE",_param->_size_queue+1); |
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| 45 | |
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| 46 | vhdl->set_signal("sig_NEXT_STATE",_param->_size_queue+1); |
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| 47 | |
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| 48 | for (uint32_t i=0; i<_param->_size_queue-1; ++i) |
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| 49 | { |
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| 50 | vhdl->set_signal("sig_WEN_"+toString(i),1); |
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| 51 | vhdl->set_signal("sig_SEL_"+toString(i),1); |
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| 52 | } |
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| 53 | vhdl->set_signal("sig_WEN_"+toString(_param->_size_queue - 1),1); |
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| 54 | |
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| 55 | vhdl->set_signal("sig_IN_ACK",1); |
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| 56 | vhdl->set_signal("sig_OUT_VAL",1); |
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| 57 | |
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| 58 | for (uint32_t i=0; i<_param->_size_queue+1; ++i) |
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| 59 | vhdl->set_constant("STATE_"+toString(i),_param->_size_queue+1,1<<i); |
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| 60 | |
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[73] | 61 | log_printf(FUNC,Execute_queue,FUNCTION,"End"); |
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| 62 | }; |
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| 63 | |
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| 64 | }; // end namespace execute_queue |
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| 65 | }; // end namespace write_unit |
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| 66 | }; // end namespace multi_write_unit |
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| 67 | }; // end namespace execute_loop |
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| 68 | }; // end namespace multi_execute_loop |
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| 69 | }; // end namespace core |
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| 70 | |
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| 71 | }; // end namespace behavioural |
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| 72 | }; // end namespace morpheo |
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| 73 | #endif |
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[96] | 74 | // signal reg_0 : std_logic_vector (15 downto 0); |
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| 75 | // signal reg_1 : std_logic_vector (15 downto 0); |
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| 76 | // signal reg_2 : std_logic_vector (15 downto 0); |
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| 77 | // signal reg_3 : std_logic_vector (15 downto 0); |
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| 78 | // signal reg_CURRENT_STATE : std_logic_vector (4 downto 0); |
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| 79 | |
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| 80 | // signal sig_NEXT_STATE : std_logic_vector (4 downto 0); |
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| 81 | // signal sig_WEN0 : std_logic; |
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| 82 | // signal sig_SEL0 : std_logic; |
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| 83 | // signal sig_WEN1 : std_logic; |
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| 84 | // signal sig_SEL1 : std_logic; |
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| 85 | // signal sig_WEN2 : std_logic; |
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| 86 | // signal sig_SEL2 : std_logic; |
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| 87 | // signal sig_WEN3 : std_logic; |
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