1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Write_queue_genMoore.cpp 123 2009-06-08 20:43:30Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_execute_loop { |
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15 | namespace execute_loop { |
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16 | namespace multi_write_unit { |
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17 | namespace write_unit { |
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18 | namespace write_queue { |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Write_queue::genMoore" |
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23 | void Write_queue::genMoore (void) |
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24 | { |
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25 | log_begin(Write_queue,FUNCTION); |
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26 | log_function(Write_queue,FUNCTION,_name.c_str()); |
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27 | |
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28 | if (PORT_READ(in_NRESET)) |
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29 | { |
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30 | // -----[ Interface "bypass_write" ]---------------------------------- |
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31 | { |
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32 | std::list<write_queue_entry_t *>::iterator it = _queue->begin(); |
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33 | |
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34 | // first bypass is the write_queue_in |
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35 | uint32_t first_index = ((_param->_bypass_write_scheme == BYPASS_WRITE_FROM_ALU)?1:0); |
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36 | for (uint32_t i=first_index; i<_param->_nb_bypass_write; i++) |
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37 | { |
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38 | // before because first slot is on {GPR|SPR}_WRITE. Also, take next |
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39 | if (it != _queue->end()) |
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40 | it++; |
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41 | |
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42 | uint32_t index = i; |
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43 | // bool val = (i+1) < _queue->size(); |
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44 | bool val = (it != _queue->end()); |
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45 | |
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46 | if (val) |
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47 | { |
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48 | if (_param->_have_port_ooo_engine_id) |
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49 | PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], (*it)->_ooo_engine_id); |
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50 | PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG [index], (*it)->_num_reg_rd); |
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51 | PORT_WRITE(out_BYPASS_WRITE_GPR_DATA [index], (*it)->_data_rd ); |
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52 | PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG [index], (*it)->_num_reg_re); |
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53 | PORT_WRITE(out_BYPASS_WRITE_SPR_DATA [index], (*it)->_data_re ); |
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54 | } |
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55 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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56 | else |
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57 | { |
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58 | if (_param->_have_port_ooo_engine_id) |
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59 | PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], 0); |
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60 | PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG [index], 0); |
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61 | PORT_WRITE(out_BYPASS_WRITE_GPR_DATA [index], 0); |
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62 | PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG [index], 0); |
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63 | PORT_WRITE(out_BYPASS_WRITE_SPR_DATA [index], 0); |
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64 | } |
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65 | #endif |
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66 | |
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67 | PORT_WRITE(out_BYPASS_WRITE_GPR_VAL [index], val and (*it)->_write_rd ); |
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68 | PORT_WRITE(out_BYPASS_WRITE_SPR_VAL [index], val and (*it)->_write_re ); |
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69 | } |
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70 | } |
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71 | |
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72 | // -----[ Interface "Write_queue_in" ]-------------------------------- |
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73 | { |
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74 | internal_WRITE_QUEUE_IN_ACK = _queue->size() < _param->_size_queue; |
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75 | } |
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76 | |
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77 | if (_param->_queue_scheme == WRITE_QUEUE_SCHEME_MOORE) |
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78 | { |
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79 | // -----[ Interface "gpr_write" ]------------------------------------- |
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80 | // -----[ Interface "spr_write" ]------------------------------------- |
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81 | { |
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82 | bool val = not _queue->empty(); |
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83 | |
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84 | internal_GPR_WRITE_VAL = val and _queue->front()->_write_rd; |
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85 | internal_SPR_WRITE_VAL = val and _queue->front()->_write_re; |
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86 | |
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87 | if (val) |
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88 | { |
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89 | if (_param->_have_port_ooo_engine_id) |
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90 | { |
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91 | PORT_WRITE(out_GPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id); |
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92 | PORT_WRITE(out_SPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id); |
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93 | } |
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94 | PORT_WRITE(out_GPR_WRITE_NUM_REG [0], _queue->front()->_num_reg_rd); |
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95 | PORT_WRITE(out_GPR_WRITE_DATA [0], _queue->front()->_data_rd ); |
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96 | PORT_WRITE(out_SPR_WRITE_NUM_REG [0], _queue->front()->_num_reg_re); |
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97 | PORT_WRITE(out_SPR_WRITE_DATA [0], _queue->front()->_data_re ); |
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98 | } |
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99 | } |
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100 | |
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101 | // -----[ Interface "Write_queue_out" ]-------------------------------- |
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102 | { |
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103 | internal_WRITE_QUEUE_OUT_VAL = ((not _queue->empty() ) and |
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104 | (not _queue->front()->_write_rd) and |
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105 | (not _queue->front()->_write_re) and |
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106 | (_queue->front()->_exception != EXCEPTION_MEMORY_LOAD_SPECULATIVE) |
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107 | ); |
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108 | |
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109 | if (internal_WRITE_QUEUE_OUT_VAL) |
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110 | { |
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111 | if (_param->_have_port_context_id) |
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112 | PORT_WRITE(out_WRITE_QUEUE_OUT_CONTEXT_ID , _queue->front()->_context_id ); |
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113 | if (_param->_have_port_front_end_id) |
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114 | PORT_WRITE(out_WRITE_QUEUE_OUT_FRONT_END_ID , _queue->front()->_front_end_id ); |
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115 | if (_param->_have_port_ooo_engine_id) |
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116 | PORT_WRITE(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id); |
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117 | if (_param->_have_port_rob_ptr ) |
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118 | PORT_WRITE(out_WRITE_QUEUE_OUT_PACKET_ID , _queue->front()->_packet_id ); |
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119 | // PORT_WRITE(out_WRITE_QUEUE_OUT_OPERATION , _queue->front()->_operation ); |
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120 | // PORT_WRITE(out_WRITE_QUEUE_OUT_TYPE , _queue->front()->_type ); |
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121 | PORT_WRITE(out_WRITE_QUEUE_OUT_FLAGS , _queue->front()->_data_re ); |
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122 | PORT_WRITE(out_WRITE_QUEUE_OUT_EXCEPTION , _queue->front()->_exception ); |
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123 | PORT_WRITE(out_WRITE_QUEUE_OUT_NO_SEQUENCE , _queue->front()->_no_sequence ); |
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124 | PORT_WRITE(out_WRITE_QUEUE_OUT_ADDRESS , _queue->front()->_address ); |
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125 | PORT_WRITE(out_WRITE_QUEUE_OUT_DATA , _queue->front()->_data_rd ); |
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126 | } |
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127 | } |
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128 | |
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129 | } // end WRITE_QUEUE_SCHEME_MOORE |
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130 | } |
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131 | else |
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132 | { |
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133 | // Reset |
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134 | internal_WRITE_QUEUE_IN_ACK = 0; |
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135 | internal_WRITE_QUEUE_OUT_VAL = 0; |
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136 | internal_GPR_WRITE_VAL = 0; |
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137 | internal_SPR_WRITE_VAL = 0; |
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138 | |
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139 | } |
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140 | |
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141 | // Write output |
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142 | PORT_WRITE(out_WRITE_QUEUE_IN_ACK , internal_WRITE_QUEUE_IN_ACK); |
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143 | PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL); |
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144 | |
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145 | PORT_WRITE(out_GPR_WRITE_VAL [0] , internal_GPR_WRITE_VAL); |
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146 | PORT_WRITE(out_SPR_WRITE_VAL [0] , internal_SPR_WRITE_VAL); |
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147 | |
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148 | log_end(Write_queue,FUNCTION); |
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149 | }; |
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150 | |
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151 | }; // end namespace write_queue |
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152 | }; // end namespace write_unit |
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153 | }; // end namespace multi_write_unit |
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154 | }; // end namespace execute_loop |
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155 | }; // end namespace multi_execute_loop |
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156 | }; // end namespace core |
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157 | |
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158 | }; // end namespace behavioural |
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159 | }; // end namespace morpheo |
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160 | #endif |
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