source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp @ 118

Last change on this file since 118 was 118, checked in by rosiere, 15 years ago

1) Stat List : scan all queue to find free register
2) Write_queue : test "genMealy" add bypass [0]
3) Functionnal_unit : add const parameters to add or not the pipeline_in
4) Load Store Unit : if load make an exception, free nb_check
5) Debug, change test to add model

  • Property svn:keywords set to Id
File size: 5.5 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id: Write_queue_genMoore.cpp 118 2009-05-20 22:01:32Z rosiere $
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_execute_loop {
15namespace execute_loop {
16namespace multi_write_unit {
17namespace write_unit {
18namespace write_queue {
19
20
21#undef  FUNCTION
22#define FUNCTION "Write_queue::genMoore"
23  void Write_queue::genMoore (void)
24  {
25    log_begin(Write_queue,FUNCTION);
26    log_function(Write_queue,FUNCTION,_name.c_str());
27   
28    // -----[ Interface "bypass_write" ]----------------------------------
29    {
30      std::list<write_queue_entry_t *>::iterator it = _queue->begin();
31
32      // first bypass is the write_queue_in
33      uint32_t first_index = ((_param->_bypass_write_scheme == BYPASS_WRITE_FROM_ALU)?1:0);
34      for (uint32_t i=first_index; i<_param->_nb_bypass_write; i++)
35        {
36          // before because first slot is on {GPR|SPR}_WRITE. Also, take next
37          if (it != _queue->end())
38            it++;
39
40          uint32_t index = i;
41//        bool val = (i+1) < _queue->size();
42          bool val = (it != _queue->end());
43
44          if (val)
45            {
46              if (_param->_have_port_ooo_engine_id)
47              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], (*it)->_ooo_engine_id);
48              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [index], (*it)->_num_reg_rd);
49              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [index], (*it)->_data_rd   );
50              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [index], (*it)->_num_reg_re);
51              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [index], (*it)->_data_re   );
52            }
53#ifdef SYSTEMC_VHDL_COMPATIBILITY
54          else
55            {
56              if (_param->_have_port_ooo_engine_id)
57              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], 0);
58              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [index], 0);
59              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [index], 0);
60              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [index], 0);
61              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [index], 0);
62            }
63#endif
64
65          PORT_WRITE(out_BYPASS_WRITE_GPR_VAL       [index], val and (*it)->_write_rd  );
66          PORT_WRITE(out_BYPASS_WRITE_SPR_VAL       [index], val and (*it)->_write_re  );
67        }
68    }
69
70    // -----[ Interface "Write_queue_in" ]--------------------------------
71    {
72      internal_WRITE_QUEUE_IN_ACK = _queue->size() < _param->_size_queue;
73     
74      PORT_WRITE(out_WRITE_QUEUE_IN_ACK, internal_WRITE_QUEUE_IN_ACK);
75    }
76
77    if (_param->_queue_scheme == WRITE_QUEUE_SCHEME_MOORE)
78      {
79    // -----[ Interface "gpr_write" ]-------------------------------------
80    // -----[ Interface "spr_write" ]-------------------------------------
81    {
82      bool val = not _queue->empty();
83
84      internal_GPR_WRITE_VAL = val and _queue->front()->_write_rd;
85      internal_SPR_WRITE_VAL = val and _queue->front()->_write_re;
86     
87      PORT_WRITE(out_GPR_WRITE_VAL [0], internal_GPR_WRITE_VAL);
88      PORT_WRITE(out_SPR_WRITE_VAL [0], internal_SPR_WRITE_VAL);
89
90      if (val)
91        {
92          if (_param->_have_port_ooo_engine_id)
93          {
94          PORT_WRITE(out_GPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
95          PORT_WRITE(out_SPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
96          }
97          PORT_WRITE(out_GPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_rd);
98          PORT_WRITE(out_GPR_WRITE_DATA          [0], _queue->front()->_data_rd   );
99          PORT_WRITE(out_SPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_re);
100          PORT_WRITE(out_SPR_WRITE_DATA          [0], _queue->front()->_data_re   );
101        }
102    }
103
104    // -----[ Interface "Write_queue_out" ]--------------------------------
105    {
106      internal_WRITE_QUEUE_OUT_VAL = ((not _queue->empty()           ) and
107                                      (not _queue->front()->_write_rd) and
108                                      (not _queue->front()->_write_re) and
109                                      (_queue->front()->_exception != EXCEPTION_MEMORY_LOAD_SPECULATIVE)
110                                      );
111     
112      PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL);
113
114      if (internal_WRITE_QUEUE_OUT_VAL)
115        {
116          if (_param->_have_port_context_id)
117          PORT_WRITE(out_WRITE_QUEUE_OUT_CONTEXT_ID   , _queue->front()->_context_id   );
118          if (_param->_have_port_front_end_id)
119          PORT_WRITE(out_WRITE_QUEUE_OUT_FRONT_END_ID , _queue->front()->_front_end_id );
120          if (_param->_have_port_ooo_engine_id)
121          PORT_WRITE(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id);
122          if (_param->_have_port_rob_ptr  )
123          PORT_WRITE(out_WRITE_QUEUE_OUT_PACKET_ID    , _queue->front()->_packet_id    );
124//        PORT_WRITE(out_WRITE_QUEUE_OUT_OPERATION    , _queue->front()->_operation    );
125//        PORT_WRITE(out_WRITE_QUEUE_OUT_TYPE         , _queue->front()->_type         );
126          PORT_WRITE(out_WRITE_QUEUE_OUT_FLAGS        , _queue->front()->_data_re      );
127          PORT_WRITE(out_WRITE_QUEUE_OUT_EXCEPTION    , _queue->front()->_exception    );
128          PORT_WRITE(out_WRITE_QUEUE_OUT_NO_SEQUENCE  , _queue->front()->_no_sequence  );
129          PORT_WRITE(out_WRITE_QUEUE_OUT_ADDRESS      , _queue->front()->_address      );
130          PORT_WRITE(out_WRITE_QUEUE_OUT_DATA         , _queue->front()->_data_rd      );
131        }
132    }
133
134      } // end WRITE_QUEUE_SCHEME_MOORE
135    log_end(Write_queue,FUNCTION);
136  };
137
138}; // end namespace write_queue
139}; // end namespace write_unit
140}; // end namespace multi_write_unit
141}; // end namespace execute_loop
142}; // end namespace multi_execute_loop
143}; // end namespace core
144
145}; // end namespace behavioural
146}; // end namespace morpheo             
147#endif
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