Changeset 118 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp

Timestamp:

May 21, 2009, 12:01:32 AM (15 years ago)

Author:

rosiere

Message:

1) Stat List : scan all queue to find free register
2) Write_queue : test "genMealy" add bypass [0]
3) Functionnal_unit : add const parameters to add or not the pipeline_in
4) Load Store Unit : if load make an exception, free nb_check
5) Debug, change test to add model

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp

@@ -29 +29 @@
     {
       std::list<write_queue_entry_t *>::iterator it = _queue->begin();
-      for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
+
+      // first bypass is the write_queue_in
+      uint32_t first_index = ((_param->_bypass_write_scheme == BYPASS_WRITE_FROM_ALU)?1:0);
+      for (uint32_t i=first_index; i<_param->_nb_bypass_write; i++)
         {
-          bool val     = i < _queue->size();
-          
+          // before because first slot is on {GPR|SPR}_WRITE. Also, take next
+          if (it != _queue->end())
+            it++;
+
+          uint32_t index = i;
+//        bool val = (i+1) < _queue->size();
+          bool val = (it != _queue->end());
+
           if (val)
             {
               if (_param->_have_port_ooo_engine_id)
-              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [i], (*it)->_ooo_engine_id);
-              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [i], (*it)->_num_reg_rd);
-              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [i], (*it)->_data_rd   );
-              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [i], (*it)->_num_reg_re);
-              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [i], (*it)->_data_re   );
+              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], (*it)->_ooo_engine_id);
+              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [index], (*it)->_num_reg_rd);
+              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [index], (*it)->_data_rd   );
+              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [index], (*it)->_num_reg_re);
+              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [index], (*it)->_data_re   );
             }
 #ifdef SYSTEMC_VHDL_COMPATIBILITY
@@ -46 +55 @@
             {
               if (_param->_have_port_ooo_engine_id)
-              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [i], 0);
-              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [i], 0);
-              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [i], 0);
-              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [i], 0);
-              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [i], 0);
+              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], 0);
+              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [index], 0);
+              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [index], 0);
+              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [index], 0);
+              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [index], 0);
             }
 #endif
 
-          PORT_WRITE(out_BYPASS_WRITE_GPR_VAL       [i], val and (*it)->_write_rd  );
-          PORT_WRITE(out_BYPASS_WRITE_SPR_VAL       [i], val and (*it)->_write_re  );
-          
-          if (it != _queue->end())
-            it++;
+          PORT_WRITE(out_BYPASS_WRITE_GPR_VAL       [index], val and (*it)->_write_rd  );
+          PORT_WRITE(out_BYPASS_WRITE_SPR_VAL       [index], val and (*it)->_write_re  );
         }
     }