1 | #ifdef SYSTEMC |
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2 | //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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3 | /* |
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4 | * $Id: Write_queue_transition.cpp 97 2008-12-19 15:34:00Z rosiere $ |
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5 | * |
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6 | * [ Description ] |
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7 | * |
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8 | */ |
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9 | |
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10 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h" |
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11 | |
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12 | namespace morpheo { |
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13 | namespace behavioural { |
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14 | namespace core { |
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15 | namespace multi_execute_loop { |
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16 | namespace execute_loop { |
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17 | namespace multi_write_unit { |
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18 | namespace write_unit { |
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19 | namespace write_queue { |
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20 | |
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21 | |
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22 | #undef FUNCTION |
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23 | #define FUNCTION "Write_queue::transition" |
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24 | void Write_queue::transition (void) |
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25 | { |
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26 | log_printf(FUNC,Write_queue,FUNCTION,"Begin"); |
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27 | |
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28 | if (PORT_READ(in_NRESET) == 0) |
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29 | { |
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30 | // Flush queue |
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31 | // FIXME "queue reset" |
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32 | // > 1) flush one slot by cycle |
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33 | // > 2) flush all slot in one cycle |
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34 | |
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35 | while (_queue->empty() == false) |
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36 | _queue->pop_front(); |
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37 | } |
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38 | else |
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39 | { |
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40 | // Test access at gpr and spr |
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41 | if (internal_GPR_WRITE_VAL and PORT_READ(in_GPR_WRITE_ACK[0])) |
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42 | _queue->front()->_write_rd = 0; |
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43 | if (internal_SPR_WRITE_VAL and PORT_READ(in_SPR_WRITE_ACK[0])) |
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44 | _queue->front()->_write_re = 0; |
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45 | |
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46 | // Test if push |
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47 | if (PORT_READ(in_WRITE_QUEUE_IN_VAL) and internal_WRITE_QUEUE_IN_ACK) |
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48 | { |
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49 | write_queue_entry_t * entry = new write_queue_entry_t |
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50 | ((_param->_have_port_context_id )?PORT_READ(in_WRITE_QUEUE_IN_CONTEXT_ID ):0, |
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51 | (_param->_have_port_front_end_id )?PORT_READ(in_WRITE_QUEUE_IN_FRONT_END_ID ):0, |
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52 | (_param->_have_port_ooo_engine_id)?PORT_READ(in_WRITE_QUEUE_IN_OOO_ENGINE_ID):0, |
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53 | (_param->_have_port_rob_ptr )?PORT_READ(in_WRITE_QUEUE_IN_PACKET_ID ):0, |
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54 | //PORT_READ(in_WRITE_QUEUE_IN_OPERATION ), |
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55 | //PORT_READ(in_WRITE_QUEUE_IN_TYPE ), |
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56 | PORT_READ(in_WRITE_QUEUE_IN_WRITE_RD ), |
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57 | PORT_READ(in_WRITE_QUEUE_IN_NUM_REG_RD ), |
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58 | PORT_READ(in_WRITE_QUEUE_IN_DATA_RD ), |
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59 | PORT_READ(in_WRITE_QUEUE_IN_WRITE_RE ), |
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60 | PORT_READ(in_WRITE_QUEUE_IN_NUM_REG_RE ), |
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61 | PORT_READ(in_WRITE_QUEUE_IN_DATA_RE ), |
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62 | PORT_READ(in_WRITE_QUEUE_IN_EXCEPTION ), |
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63 | PORT_READ(in_WRITE_QUEUE_IN_NO_SEQUENCE ), |
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64 | PORT_READ(in_WRITE_QUEUE_IN_ADDRESS )); |
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65 | |
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66 | _queue->push_back(entry); |
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67 | } |
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68 | |
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69 | // Test if pop : |
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70 | // * transaction on write_queue_out interface |
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71 | // * have a speculative load and all register is write in registerfile |
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72 | if ( (internal_WRITE_QUEUE_OUT_VAL and PORT_READ(in_WRITE_QUEUE_OUT_ACK)) or |
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73 | ((_queue->empty() == false) and |
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74 | // (_queue->front()->_type == TYPE_MEMORY) and |
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75 | (_queue->front()->_exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE) and // this exception code must be uniq |
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76 | (_queue->front()->_write_rd == 0) and |
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77 | (_queue->front()->_write_re == 0))) |
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78 | { |
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79 | delete _queue->front(); |
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80 | _queue->pop_front(); |
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81 | } |
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82 | } |
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83 | |
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84 | #ifdef STATISTICS |
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85 | if (usage_is_set(_usage,USE_STATISTICS)) |
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86 | *(_stat_use_queue) += _queue->size(); |
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87 | #endif |
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88 | |
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89 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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90 | end_cycle (); |
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91 | #endif |
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92 | |
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93 | log_printf(FUNC,Write_queue,FUNCTION,"End"); |
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94 | }; |
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95 | |
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96 | }; // end namespace write_queue |
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97 | }; // end namespace write_unit |
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98 | }; // end namespace multi_write_unit |
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99 | }; // end namespace execute_loop |
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100 | }; // end namespace multi_execute_loop |
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101 | }; // end namespace core |
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102 | |
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103 | }; // end namespace behavioural |
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104 | }; // end namespace morpheo |
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105 | #endif |
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106 | //#endif |
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