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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp @ 112

Last change on this file since 112 was 112, checked in by rosiere, 15 years ago
1) Stat_list : fix retire old and new register bug 2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step) 3) Model : add class Model (cf Morpheo.sim) 4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array. 5) Script : add distexe.sh 6) Add Comparator, Multiplier, Divider. But this component are not implemented 7) Software : add Dhrystone
Property svn:keywords set to `Id`
File size: 23.7 KB

Rev	Line
[74]	1	/*
	2	* $Id: Write_unit_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $
	3	*
	4	* [ Description ]
	5	*
	6	*/
	7
	8	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h"
	9	#include "Behavioural/include/Allocation.h"
	10
	11	namespace morpheo {
	12	namespace behavioural {
	13	namespace core {
	14	namespace multi_execute_loop {
	15	namespace execute_loop {
	16	namespace multi_write_unit {
	17	namespace write_unit {
	18
	19
	20
	21	#undef FUNCTION
	22	#define FUNCTION "Write_unit::allocation"
	23	void Write_unit::allocation (
	24	#ifdef STATISTICS
[88]	25	morpheo::behavioural::Parameters_Statistics * param_statistics
[74]	26	#else
[88]	27	void
[74]	28	#endif
[88]	29	)
[74]	30	{
	31	log_printf(FUNC,Write_unit,FUNCTION,"Begin");
	32
	33	_component = new Component (_usage);
	34
	35	Entity * entity = _component->set_entity (_name
[88]	36	,"Write_unit"
[74]	37	#ifdef POSITION
[88]	38	,COMBINATORY
[74]	39	#endif
[88]	40	);
[74]	41
	42	_interfaces = entity->set_interfaces();
	43
	44	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	45
	46	Interface * interface = _interfaces->set_interface(""
	47	#ifdef POSITION
[88]	48	,IN
	49	,SOUTH,
	50	"Generalist interface"
[74]	51	#endif
[88]	52	);
[74]	53
	54	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
	55	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
	56
	57	// -----[ Interface "write_unit_in" ]--------------------------------
	58	{
[112]	59	ALLOC0_INTERFACE_BEGIN("write_unit_in", IN, WEST, "Input of write_unit");
[74]	60
[112]	61	ALLOC0_VALACK_IN ( in_WRITE_UNIT_IN_VAL,VAL);
	62	ALLOC0_VALACK_OUT(out_WRITE_UNIT_IN_ACK,ACK);
	63	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );
	64	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id );
	65	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
	66	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr );
	67	// ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation );
	68	// ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type );
	69	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 );
	70	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register );
	71	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data );
	72	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 );
	73	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register );
	74	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data );
	75	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception );
	76	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 );
	77	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address);
	78
	79	ALLOC0_INTERFACE_END();
[74]	80	}
	81
	82	// -----[ Interface "write_unit_out" ]-------------------------------
	83	{
[112]	84	ALLOC0_INTERFACE_BEGIN("write_unit_out", OUT, EAST, "Output of write_unit");
[74]	85
[112]	86	ALLOC0_VALACK_OUT(out_WRITE_UNIT_OUT_VAL,VAL);
	87	ALLOC0_VALACK_IN ( in_WRITE_UNIT_OUT_ACK,ACK);
	88	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );
	89	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id );
	90	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id);
	91	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr );
	92	// ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation );
	93	// ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type );
	94	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data );
	95	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception );
	96	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 );
	97	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address);
	98	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data );
	99
	100	ALLOC0_INTERFACE_END();
[74]	101	}
	102
	103	// -----[ Interface "gpr_write" ]-------------------------------------
	104	{
[112]	105	ALLOC1_INTERFACE_BEGIN("gpr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_gpr_write);
[74]	106
[78]	107	ALLOC1_VALACK_OUT(out_GPR_WRITE_VAL,VAL);
	108	ALLOC1_VALACK_IN ( in_GPR_WRITE_ACK,ACK);
[76]	109	ALLOC1_SIGNAL_OUT(out_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
	110	ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register);
	111	ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data );
[112]	112
	113	ALLOC1_INTERFACE_END(_param->_nb_gpr_write);
[74]	114	}
	115
	116	// -----[ Interface "spr_write" ]-------------------------------------
	117	{
[112]	118	ALLOC1_INTERFACE_BEGIN("spr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_spr_write);
[74]	119
[78]	120	ALLOC1_VALACK_OUT(out_SPR_WRITE_VAL,VAL);
	121	ALLOC1_VALACK_IN ( in_SPR_WRITE_ACK,ACK);
[76]	122	ALLOC1_SIGNAL_OUT(out_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
	123	ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register);
	124	ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data );
[112]	125
	126	ALLOC1_INTERFACE_END(_param->_nb_spr_write);
[74]	127	}
	128
	129	// -----[ Interface "bypass_write" ]----------------------------------
	130	{
[112]	131	ALLOC1_INTERFACE_BEGIN("bypass_write", OUT, NORTH ,"Output of internal write_unit", _param->_nb_bypass_write);
[74]	132
[76]	133	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
	134	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1 );
	135	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_register);
	136	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_data );
	137	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1 );
	138	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register);
	139	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data );
[112]	140
	141	ALLOC1_INTERFACE_END(_param->_nb_bypass_write);
[74]	142	}
	143
	144	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	145
[75]	146	std::string name;
[74]	147
	148	{
	149	name = _name+"_write_queue";
[88]	150	log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str());
	151
[82]	152	component_write_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Write_queue
[88]	153	(name.c_str()
[74]	154	#ifdef STATISTICS
[88]	155	,param_statistics
[74]	156	#endif
[88]	157	,_param->_param_write_queue
	158	,_usage);
[74]	159
	160	_component->set_component (component_write_queue->_component
	161	#ifdef POSITION
[88]	162	, 50, 50, 10, 10
[74]	163	#endif
[88]	164	);
[74]	165	}
	166
	167	if (_param->_have_component_execute_queue)
	168	{
	169	name = _name+"_execute_queue";
[88]	170	log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str());
[74]	171
[82]	172	component_execute_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::execute_queue::Execute_queue
[88]	173	(name.c_str()
[74]	174	#ifdef STATISTICS
[88]	175	,param_statistics
[74]	176	#endif
[88]	177	,_param->_param_execute_queue
	178	,_usage);
[74]	179
	180	_component->set_component (component_execute_queue->_component
	181	#ifdef POSITION
[88]	182	, 50, 50, 10, 10
[74]	183	#endif
[88]	184	);
[74]	185	}
	186
	187	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	188	{
	189	name = _name+"_write_queue";
[88]	190	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str());
	191
[74]	192	#ifdef POSITION
	193	_component->interface_map (name ,"",
[88]	194	_name,"");
[74]	195	#endif
	196
	197	_component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
	198	_component->port_map(name,"in_NRESET", _name, "in_NRESET");
	199
	200
	201	#ifdef POSITION
[75]	202	_component->interface_map (name ,"write_queue_in",
[88]	203	_name,"write_unit_in");
[74]	204	#endif
	205
	206	_component->port_map(name, "in_WRITE_QUEUE_IN_VAL" , _name, "in_WRITE_UNIT_IN_VAL" );
	207	_component->port_map(name,"out_WRITE_QUEUE_IN_ACK" , _name,"out_WRITE_UNIT_IN_ACK" );
	208	if (_param->_have_port_context_id)
	209	_component->port_map(name, "in_WRITE_QUEUE_IN_CONTEXT_ID" , _name, "in_WRITE_UNIT_IN_CONTEXT_ID" );
	210	if (_param->_have_port_front_end_id)
	211	_component->port_map(name, "in_WRITE_QUEUE_IN_FRONT_END_ID" , _name, "in_WRITE_UNIT_IN_FRONT_END_ID" );
	212	if (_param->_have_port_ooo_engine_id)
	213	_component->port_map(name, "in_WRITE_QUEUE_IN_OOO_ENGINE_ID", _name, "in_WRITE_UNIT_IN_OOO_ENGINE_ID");
[88]	214	if (_param->_have_port_rob_ptr)
[74]	215	_component->port_map(name, "in_WRITE_QUEUE_IN_PACKET_ID" , _name, "in_WRITE_UNIT_IN_PACKET_ID" );
	216	//_component->port_map(name, "in_WRITE_QUEUE_IN_OPERATION" , _name, "in_WRITE_UNIT_IN_OPERATION" );
[97]	217	//_component->port_map(name, "in_WRITE_QUEUE_IN_TYPE" , _name, "in_WRITE_UNIT_IN_TYPE" );
[74]	218	_component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RD" , _name, "in_WRITE_UNIT_IN_WRITE_RD" );
	219	_component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RD" , _name, "in_WRITE_UNIT_IN_NUM_REG_RD" );
	220	_component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RD" , _name, "in_WRITE_UNIT_IN_DATA_RD" );
	221	_component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RE" , _name, "in_WRITE_UNIT_IN_WRITE_RE" );
	222	_component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RE" , _name, "in_WRITE_UNIT_IN_NUM_REG_RE" );
	223	_component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RE" , _name, "in_WRITE_UNIT_IN_DATA_RE" );
	224	_component->port_map(name, "in_WRITE_QUEUE_IN_EXCEPTION" , _name, "in_WRITE_UNIT_IN_EXCEPTION" );
	225	_component->port_map(name, "in_WRITE_QUEUE_IN_NO_SEQUENCE" , _name, "in_WRITE_UNIT_IN_NO_SEQUENCE" );
	226	_component->port_map(name, "in_WRITE_QUEUE_IN_ADDRESS" , _name, "in_WRITE_UNIT_IN_ADDRESS" );
	227
	228
	229	if (_param->_have_component_execute_queue)
[88]	230	{
[74]	231	#ifdef POSITION
[88]	232	_component->interface_map (name ,"write_queue_out",
	233	_name+"_execute_queue", "execute_queue_in");
[74]	234	#endif
	235
[88]	236	_component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_VAL" );
	237	_component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name+"_execute_queue","out_EXECUTE_QUEUE_IN_ACK" );
	238	if (_param->_have_port_context_id)
	239	_component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_CONTEXT_ID" );
	240	if (_param->_have_port_front_end_id)
	241	_component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FRONT_END_ID" );
	242	if (_param->_have_port_ooo_engine_id)
	243	_component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID");
	244	if (_param->_have_port_rob_ptr)
	245	_component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_PACKET_ID" );
	246	//_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OPERATION" );
	247	//_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_TYPE" );
	248	_component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FLAGS" );
	249	_component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_EXCEPTION" );
	250	_component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_NO_SEQUENCE" );
	251	_component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_ADDRESS" );
	252	_component->port_map(name,"out_WRITE_QUEUE_OUT_DATA" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_DATA" );
	253	}
[74]	254	else
[88]	255	{
[74]	256	#ifdef POSITION
[88]	257	_component->interface_map (name ,"write_queue_out",
	258	_name,"write_unit_out");
[74]	259	#endif
	260
[88]	261	_component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" );
	262	_component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" );
	263	if (_param->_have_port_context_id)
	264	_component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" );
	265	if (_param->_have_port_front_end_id)
	266	_component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
	267	if (_param->_have_port_ooo_engine_id)
	268	_component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
	269	if (_param->_have_port_rob_ptr)
	270	_component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" );
	271	//_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" );
	272	//_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" );
	273	_component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" );
	274	_component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" );
	275	_component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" );
	276	_component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" );
	277	_component->port_map(name,"out_WRITE_QUEUE_OUT_DATA" , _name,"out_WRITE_UNIT_OUT_DATA" );
	278	}
[74]	279
	280	for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
[88]	281	{
[74]	282	#ifdef POSITION
[88]	283	_component->interface_map (name ,"gpr_write_"+toString(i),
	284	_name,"gpr_write_"+toString(i));
	285	#endif
	286
	287	_component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_GPR_WRITE_"+toString(i)+"_VAL" );
	288	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_GPR_WRITE_"+toString(i)+"_ACK" );
	289	if (_param->_have_port_ooo_engine_id)
	290	_component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
	291	_component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" );
	292	_component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_GPR_WRITE_"+toString(i)+"_DATA" );
	293	}
[74]	294
	295	for (uint32_t i=0; i<_param->_nb_spr_write; i++)
[88]	296	{
[74]	297	#ifdef POSITION
[88]	298	_component->interface_map (name ,"spr_write_"+toString(i),
	299	_name,"spr_write_"+toString(i));
	300	#endif
	301
	302	_component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_SPR_WRITE_"+toString(i)+"_VAL" );
	303	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_SPR_WRITE_"+toString(i)+"_ACK" );
	304	if (_param->_have_port_ooo_engine_id)
	305	_component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
	306	_component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" );
	307	_component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_SPR_WRITE_"+toString(i)+"_DATA" );
	308	}
[74]	309
	310
	311	for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
[88]	312	{
[74]	313	#ifdef POSITION
[88]	314	_component->interface_map (name ,"bypass_write_"+toString(i),
	315	_name,"bypass_write_"+toString(i));
	316	#endif
[74]	317
[88]	318	if (_param->_have_port_ooo_engine_id)
	319	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
	320	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" );
	321	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" );
	322	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" );
	323	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" );
	324	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" );
	325	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" );
	326	}
[74]	327	}
	328
	329	if (_param->_have_component_execute_queue)
	330	{
[88]	331	name = _name+"_execute_queue";
	332	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str());
	333
[74]	334	#ifdef POSITION
[88]	335	_component->interface_map (name ,"",
	336	_name,"");
[74]	337	#endif
[88]	338
	339	_component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
	340	_component->port_map(name,"in_NRESET", _name, "in_NRESET");
	341
[74]	342
	343	#ifdef POSITION
[88]	344	_component->interface_map (name ,"execute_queue_in",
	345	_name+"_write_queue","write_queue_in");
[74]	346	#endif
	347
	348	_component->port_map(name, "in_EXECUTE_QUEUE_IN_VAL" , _name+"_write_queue","out_WRITE_QUEUE_OUT_VAL" );
	349	_component->port_map(name,"out_EXECUTE_QUEUE_IN_ACK" , _name+"_write_queue", "in_WRITE_QUEUE_OUT_ACK" );
	350	if (_param->_have_port_context_id)
	351	_component->port_map(name, "in_EXECUTE_QUEUE_IN_CONTEXT_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_CONTEXT_ID" );
	352	if (_param->_have_port_front_end_id)
	353	_component->port_map(name, "in_EXECUTE_QUEUE_IN_FRONT_END_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_FRONT_END_ID" );
	354	if (_param->_have_port_ooo_engine_id)
	355	_component->port_map(name, "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID", _name+"_write_queue","out_WRITE_QUEUE_OUT_OOO_ENGINE_ID");
[88]	356	if (_param->_have_port_rob_ptr)
[74]	357	_component->port_map(name, "in_EXECUTE_QUEUE_IN_PACKET_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_PACKET_ID" );
	358	//_component->port_map(name, "in_EXECUTE_QUEUE_IN_OPERATION" , _name+"_write_queue","out_WRITE_QUEUE_OUT_OPERATION" );
	359	//_component->port_map(name, "in_EXECUTE_QUEUE_IN_TYPE" , _name+"_write_queue","out_WRITE_QUEUE_OUT_TYPE" );
	360	_component->port_map(name, "in_EXECUTE_QUEUE_IN_FLAGS" , _name+"_write_queue","out_WRITE_QUEUE_OUT_FLAGS" );
	361	_component->port_map(name, "in_EXECUTE_QUEUE_IN_EXCEPTION" , _name+"_write_queue","out_WRITE_QUEUE_OUT_EXCEPTION" );
	362	_component->port_map(name, "in_EXECUTE_QUEUE_IN_NO_SEQUENCE" , _name+"_write_queue","out_WRITE_QUEUE_OUT_NO_SEQUENCE" );
	363	_component->port_map(name, "in_EXECUTE_QUEUE_IN_ADDRESS" , _name+"_write_queue","out_WRITE_QUEUE_OUT_ADDRESS" );
[88]	364	_component->port_map(name, "in_EXECUTE_QUEUE_IN_DATA" , _name+"_write_queue","out_WRITE_QUEUE_OUT_DATA" );
[74]	365
	366	#ifdef POSITION
[88]	367	_component->interface_map (name ,"execute_queue_out",
	368	_name,"write_unit_out");
[74]	369	#endif
	370
[88]	371	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" );
	372	_component->port_map(name, "in_EXECUTE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" );
	373	if (_param->_have_port_context_id)
	374	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" );
	375	if (_param->_have_port_front_end_id)
	376	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
	377	if (_param->_have_port_ooo_engine_id)
	378	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
	379	if (_param->_have_port_rob_ptr)
	380	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" );
	381	//_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" );
	382	//_component->port_map(name,"out_EXECUTE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" );
	383	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" );
	384	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" );
	385	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" );
	386	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" );
	387	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_DATA" , _name,"out_WRITE_UNIT_OUT_DATA" );
[74]	388	}
	389
	390	#ifdef POSITION
[88]	391	if (usage_is_set(_usage,USE_POSITION))
	392	_component->generate_file();
[74]	393	#endif
	394
	395	log_printf(FUNC,Write_unit,FUNCTION,"End");
	396	};
	397
	398	}; // end namespace write_unit
	399	}; // end namespace multi_write_unit
	400	}; // end namespace execute_loop
	401	}; // end namespace multi_execute_loop
	402	}; // end namespace core
	403
	404	}; // end namespace behavioural
	405	}; // end namespace morpheo

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