[74] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h" |
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| 9 | #include "Behavioural/include/Allocation.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_execute_loop { |
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| 15 | namespace execute_loop { |
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| 16 | namespace multi_write_unit { |
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| 17 | namespace write_unit { |
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| 18 | |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Write_unit::allocation" |
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| 23 | void Write_unit::allocation ( |
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| 24 | #ifdef STATISTICS |
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| 25 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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| 26 | #else |
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| 27 | void |
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| 28 | #endif |
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| 29 | ) |
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| 30 | { |
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| 31 | log_printf(FUNC,Write_unit,FUNCTION,"Begin"); |
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| 32 | |
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| 33 | _component = new Component (_usage); |
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| 34 | |
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| 35 | Entity * entity = _component->set_entity (_name |
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| 36 | ,"Write_unit" |
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| 37 | #ifdef POSITION |
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| 38 | ,COMBINATORY |
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| 39 | #endif |
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| 40 | ); |
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| 41 | |
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| 42 | _interfaces = entity->set_interfaces(); |
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| 43 | |
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| 44 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 45 | |
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| 46 | Interface * interface = _interfaces->set_interface("" |
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| 47 | #ifdef POSITION |
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| 48 | ,IN |
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| 49 | ,SOUTH, |
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| 50 | "Generalist interface" |
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| 51 | #endif |
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| 52 | ); |
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| 53 | |
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| 54 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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| 55 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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| 56 | |
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| 57 | // -----[ Interface "write_unit_in" ]-------------------------------- |
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| 58 | { |
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| 59 | ALLOC_INTERFACE ("write_unit_in", IN, WEST, "Input of write_unit"); |
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| 60 | |
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| 61 | ALLOC_VAL_IN ( in_WRITE_UNIT_IN_VAL); |
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| 62 | ALLOC_ACK_OUT (out_WRITE_UNIT_IN_ACK); |
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| 63 | if(_param->_have_port_context_id) |
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| 64 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); |
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| 65 | if(_param->_have_port_front_end_id) |
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| 66 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); |
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| 67 | if(_param->_have_port_ooo_engine_id) |
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| 68 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); |
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| 69 | if(_param->_have_port_packet_id) |
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| 70 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); |
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| 71 | // ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); |
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| 72 | // ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); |
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| 73 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); |
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| 74 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); |
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| 75 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); |
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| 76 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); |
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| 77 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); |
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| 78 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); |
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| 79 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); |
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| 80 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); |
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| 81 | ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); |
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| 82 | } |
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| 83 | |
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| 84 | // -----[ Interface "write_unit_out" ]------------------------------- |
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| 85 | { |
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| 86 | ALLOC_INTERFACE ("write_unit_out", OUT, EAST, "Output of write_unit"); |
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| 87 | |
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| 88 | ALLOC_VAL_OUT (out_WRITE_UNIT_OUT_VAL); |
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| 89 | ALLOC_ACK_IN ( in_WRITE_UNIT_OUT_ACK); |
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| 90 | if(_param->_have_port_context_id) |
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| 91 | ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); |
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| 92 | if(_param->_have_port_front_end_id) |
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| 93 | ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); |
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| 94 | if(_param->_have_port_ooo_engine_id) |
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| 95 | ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); |
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| 96 | if(_param->_have_port_packet_id) |
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| 97 | ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); |
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| 98 | // ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); |
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| 99 | // ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); |
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| 100 | ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data ); |
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| 101 | ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); |
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| 102 | ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); |
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| 103 | ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data ); |
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| 104 | } |
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| 105 | |
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| 106 | // -----[ Interface "gpr_write" ]------------------------------------- |
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| 107 | { |
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| 108 | ALLOC1_INTERFACE("gpr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_gpr_write); |
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| 109 | |
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| 110 | ALLOC1_VAL_OUT (out_GPR_WRITE_VAL ,_param->_nb_gpr_write); |
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| 111 | ALLOC1_ACK_IN ( in_GPR_WRITE_ACK ,_param->_nb_gpr_write); |
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| 112 | if(_param->_have_port_ooo_engine_id) |
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| 113 | ALLOC1_SIGNAL_OUT(out_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ,_param->_nb_gpr_write); |
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| 114 | ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_gpr_write); |
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| 115 | ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_gpr_write); |
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| 116 | } |
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| 117 | |
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| 118 | // -----[ Interface "spr_write" ]------------------------------------- |
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| 119 | { |
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| 120 | ALLOC1_INTERFACE("spr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_spr_write); |
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| 121 | |
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| 122 | ALLOC1_VAL_OUT (out_SPR_WRITE_VAL ,_param->_nb_spr_write); |
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| 123 | ALLOC1_ACK_IN ( in_SPR_WRITE_ACK ,_param->_nb_spr_write); |
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| 124 | if(_param->_have_port_ooo_engine_id) |
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| 125 | ALLOC1_SIGNAL_OUT(out_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ,_param->_nb_spr_write); |
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| 126 | ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_spr_write); |
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| 127 | ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data ,_param->_nb_spr_write); |
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| 128 | } |
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| 129 | |
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| 130 | // -----[ Interface "bypass_write" ]---------------------------------- |
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| 131 | { |
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| 132 | ALLOC1_INTERFACE("bypass_write", OUT, NORTH ,"Output of internal write_unit", _param->_nb_bypass_write); |
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| 133 | |
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| 134 | if(_param->_have_port_ooo_engine_id) |
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| 135 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id , _param->_nb_bypass_write); |
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| 136 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1 , _param->_nb_bypass_write); |
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| 137 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_register, _param->_nb_bypass_write); |
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| 138 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_bypass_write); |
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| 139 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1 , _param->_nb_bypass_write); |
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| 140 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register, _param->_nb_bypass_write); |
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| 141 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data , _param->_nb_bypass_write); |
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| 142 | } |
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| 143 | |
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| 144 | |
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| 145 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 146 | |
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| 147 | string name; |
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| 148 | |
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| 149 | { |
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| 150 | name = _name+"_write_queue"; |
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| 151 | |
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| 152 | component_write_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Write_queue (name.c_str() |
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| 153 | #ifdef STATISTICS |
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| 154 | ,param_statistics |
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| 155 | #endif |
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| 156 | ,_param->_param_write_queue); |
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| 157 | |
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| 158 | _component->set_component (component_write_queue->_component |
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| 159 | #ifdef POSITION |
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| 160 | , 50, 50, 10, 10 |
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| 161 | #endif |
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| 162 | ); |
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| 163 | } |
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| 164 | |
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| 165 | if (_param->_have_component_execute_queue) |
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| 166 | { |
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| 167 | name = _name+"_execute_queue"; |
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| 168 | |
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| 169 | component_execute_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::execute_queue::Execute_queue (name.c_str() |
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| 170 | #ifdef STATISTICS |
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| 171 | ,param_statistics |
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| 172 | #endif |
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| 173 | ,_param->_param_execute_queue); |
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| 174 | |
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| 175 | _component->set_component (component_execute_queue->_component |
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| 176 | #ifdef POSITION |
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| 177 | , 50, 50, 10, 10 |
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| 178 | #endif |
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| 179 | ); |
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| 180 | } |
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| 181 | |
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| 182 | // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 183 | |
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| 184 | { |
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| 185 | name = _name+"_write_queue"; |
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| 186 | cout << "Instance : " << name << endl; |
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| 187 | |
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| 188 | #ifdef POSITION |
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| 189 | _component->interface_map (name ,"", |
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| 190 | _name,""); |
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| 191 | #endif |
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| 192 | |
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| 193 | _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK"); |
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| 194 | _component->port_map(name,"in_NRESET", _name, "in_NRESET"); |
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| 195 | |
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| 196 | |
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| 197 | #ifdef POSITION |
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| 198 | _component->interface_map (name ,"WRITE_QUEUE_IN", |
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| 199 | _name,"WRITE_UNIT_IN"); |
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| 200 | #endif |
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| 201 | |
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| 202 | _component->port_map(name, "in_WRITE_QUEUE_IN_VAL" , _name, "in_WRITE_UNIT_IN_VAL" ); |
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| 203 | _component->port_map(name,"out_WRITE_QUEUE_IN_ACK" , _name,"out_WRITE_UNIT_IN_ACK" ); |
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| 204 | if (_param->_have_port_context_id) |
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| 205 | _component->port_map(name, "in_WRITE_QUEUE_IN_CONTEXT_ID" , _name, "in_WRITE_UNIT_IN_CONTEXT_ID" ); |
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| 206 | if (_param->_have_port_front_end_id) |
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| 207 | _component->port_map(name, "in_WRITE_QUEUE_IN_FRONT_END_ID" , _name, "in_WRITE_UNIT_IN_FRONT_END_ID" ); |
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| 208 | if (_param->_have_port_ooo_engine_id) |
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| 209 | _component->port_map(name, "in_WRITE_QUEUE_IN_OOO_ENGINE_ID", _name, "in_WRITE_UNIT_IN_OOO_ENGINE_ID"); |
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| 210 | if (_param->_have_port_packet_id) |
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| 211 | _component->port_map(name, "in_WRITE_QUEUE_IN_PACKET_ID" , _name, "in_WRITE_UNIT_IN_PACKET_ID" ); |
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| 212 | //_component->port_map(name, "in_WRITE_QUEUE_IN_OPERATION" , _name, "in_WRITE_UNIT_IN_OPERATION" ); |
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| 213 | //_component->port_map(name, "in_WRITE_QUEUE_IN_TYPE" , _name, "in_WRITE_UNIT_IN_TYPE" ); |
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| 214 | _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RD" , _name, "in_WRITE_UNIT_IN_WRITE_RD" ); |
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| 215 | _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RD" , _name, "in_WRITE_UNIT_IN_NUM_REG_RD" ); |
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| 216 | _component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RD" , _name, "in_WRITE_UNIT_IN_DATA_RD" ); |
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| 217 | _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RE" , _name, "in_WRITE_UNIT_IN_WRITE_RE" ); |
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| 218 | _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RE" , _name, "in_WRITE_UNIT_IN_NUM_REG_RE" ); |
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| 219 | _component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RE" , _name, "in_WRITE_UNIT_IN_DATA_RE" ); |
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| 220 | _component->port_map(name, "in_WRITE_QUEUE_IN_EXCEPTION" , _name, "in_WRITE_UNIT_IN_EXCEPTION" ); |
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| 221 | _component->port_map(name, "in_WRITE_QUEUE_IN_NO_SEQUENCE" , _name, "in_WRITE_UNIT_IN_NO_SEQUENCE" ); |
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| 222 | _component->port_map(name, "in_WRITE_QUEUE_IN_ADDRESS" , _name, "in_WRITE_UNIT_IN_ADDRESS" ); |
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| 223 | |
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| 224 | |
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| 225 | if (_param->_have_component_execute_queue) |
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| 226 | { |
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| 227 | #ifdef POSITION |
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| 228 | _component->interface_map (name ,"WRITE_QUEUE_OUT", |
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| 229 | _name+"_execute_queue", "EXECUTE_QUEUE_IN"); |
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| 230 | #endif |
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| 231 | |
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| 232 | _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_VAL" ); |
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| 233 | _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name+"_execute_queue","out_EXECUTE_QUEUE_IN_ACK" ); |
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| 234 | if (_param->_have_port_context_id) |
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| 235 | _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_CONTEXT_ID" ); |
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| 236 | if (_param->_have_port_front_end_id) |
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| 237 | _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FRONT_END_ID" ); |
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| 238 | if (_param->_have_port_ooo_engine_id) |
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| 239 | _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID"); |
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| 240 | if (_param->_have_port_packet_id) |
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| 241 | _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_PACKET_ID" ); |
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| 242 | //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OPERATION" ); |
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| 243 | //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_TYPE" ); |
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| 244 | _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FLAGS" ); |
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| 245 | _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_EXCEPTION" ); |
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| 246 | _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_NO_SEQUENCE" ); |
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| 247 | _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_ADDRESS" ); |
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| 248 | } |
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| 249 | else |
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| 250 | { |
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| 251 | #ifdef POSITION |
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| 252 | _component->interface_map (name ,"WRITE_QUEUE_OUT", |
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| 253 | _name,"WRITE_UNIT_OUT"); |
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| 254 | #endif |
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| 255 | |
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| 256 | _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" ); |
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| 257 | _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" ); |
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| 258 | if (_param->_have_port_context_id) |
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| 259 | _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" ); |
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| 260 | if (_param->_have_port_front_end_id) |
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| 261 | _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" ); |
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| 262 | if (_param->_have_port_ooo_engine_id) |
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| 263 | _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID"); |
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| 264 | if (_param->_have_port_packet_id) |
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| 265 | _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" ); |
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| 266 | //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" ); |
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| 267 | //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" ); |
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| 268 | _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" ); |
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| 269 | _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" ); |
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| 270 | _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" ); |
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| 271 | _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" ); |
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| 272 | } |
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| 273 | |
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| 274 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
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| 275 | { |
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| 276 | #ifdef POSITION |
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| 277 | _component->interface_map (name ,"GPR_WRITE_"+toString(i), |
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| 278 | _name,"GPR_WRITE_"+toString(i)); |
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| 279 | #endif |
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| 280 | |
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| 281 | _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_GPR_WRITE_"+toString(i)+"_VAL" ); |
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| 282 | _component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_GPR_WRITE_"+toString(i)+"_ACK" ); |
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| 283 | if (_param->_have_port_ooo_engine_id) |
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| 284 | _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); |
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| 285 | _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" ); |
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| 286 | _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_GPR_WRITE_"+toString(i)+"_DATA" ); |
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| 287 | } |
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| 288 | |
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| 289 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
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| 290 | { |
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| 291 | #ifdef POSITION |
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| 292 | _component->interface_map (name ,"SPR_WRITE_"+toString(i), |
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| 293 | _name,"SPR_WRITE_"+toString(i)); |
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| 294 | #endif |
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| 295 | |
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| 296 | _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_SPR_WRITE_"+toString(i)+"_VAL" ); |
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| 297 | _component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_SPR_WRITE_"+toString(i)+"_ACK" ); |
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| 298 | if (_param->_have_port_ooo_engine_id) |
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| 299 | _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); |
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| 300 | _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" ); |
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| 301 | _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_SPR_WRITE_"+toString(i)+"_DATA" ); |
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| 302 | } |
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| 303 | |
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| 304 | |
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| 305 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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| 306 | { |
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| 307 | #ifdef POSITION |
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| 308 | _component->interface_map (name ,"BYPASS_WRITE_"+toString(i), |
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| 309 | _name,"BYPASS_WRITE_"+toString(i)); |
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| 310 | #endif |
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| 311 | |
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| 312 | if (_param->_have_port_ooo_engine_id) |
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| 313 | _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); |
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| 314 | _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" ); |
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| 315 | _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" ); |
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| 316 | _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" ); |
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| 317 | _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" ); |
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| 318 | _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" ); |
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| 319 | _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" ); |
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| 320 | } |
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| 321 | } |
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| 322 | |
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| 323 | if (_param->_have_component_execute_queue) |
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| 324 | { |
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| 325 | name = _name+"_execute_queue"; |
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| 326 | cout << "Instance : " << name << endl; |
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| 327 | |
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| 328 | #ifdef POSITION |
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| 329 | _component->interface_map (name ,"", |
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| 330 | _name,""); |
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| 331 | #endif |
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| 332 | |
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| 333 | _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK"); |
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| 334 | _component->port_map(name,"in_NRESET", _name, "in_NRESET"); |
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| 335 | |
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| 336 | |
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| 337 | #ifdef POSITION |
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| 338 | _component->interface_map (name ,"WRITE_QUEUE_IN", |
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| 339 | _name+"_write_queue","WRITE_UNIT_IN"); |
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| 340 | #endif |
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| 341 | |
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| 342 | _component->port_map(name, "in_EXECUTE_QUEUE_IN_VAL" , _name+"_write_queue","out_WRITE_QUEUE_OUT_VAL" ); |
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| 343 | _component->port_map(name,"out_EXECUTE_QUEUE_IN_ACK" , _name+"_write_queue", "in_WRITE_QUEUE_OUT_ACK" ); |
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| 344 | if (_param->_have_port_context_id) |
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| 345 | _component->port_map(name, "in_EXECUTE_QUEUE_IN_CONTEXT_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_CONTEXT_ID" ); |
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| 346 | if (_param->_have_port_front_end_id) |
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| 347 | _component->port_map(name, "in_EXECUTE_QUEUE_IN_FRONT_END_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_FRONT_END_ID" ); |
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| 348 | if (_param->_have_port_ooo_engine_id) |
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| 349 | _component->port_map(name, "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID", _name+"_write_queue","out_WRITE_QUEUE_OUT_OOO_ENGINE_ID"); |
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| 350 | if (_param->_have_port_packet_id) |
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| 351 | _component->port_map(name, "in_EXECUTE_QUEUE_IN_PACKET_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_PACKET_ID" ); |
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| 352 | //_component->port_map(name, "in_EXECUTE_QUEUE_IN_OPERATION" , _name+"_write_queue","out_WRITE_QUEUE_OUT_OPERATION" ); |
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| 353 | //_component->port_map(name, "in_EXECUTE_QUEUE_IN_TYPE" , _name+"_write_queue","out_WRITE_QUEUE_OUT_TYPE" ); |
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| 354 | _component->port_map(name, "in_EXECUTE_QUEUE_IN_FLAGS" , _name+"_write_queue","out_WRITE_QUEUE_OUT_FLAGS" ); |
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| 355 | _component->port_map(name, "in_EXECUTE_QUEUE_IN_EXCEPTION" , _name+"_write_queue","out_WRITE_QUEUE_OUT_EXCEPTION" ); |
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| 356 | _component->port_map(name, "in_EXECUTE_QUEUE_IN_NO_SEQUENCE" , _name+"_write_queue","out_WRITE_QUEUE_OUT_NO_SEQUENCE" ); |
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| 357 | _component->port_map(name, "in_EXECUTE_QUEUE_IN_ADDRESS" , _name+"_write_queue","out_WRITE_QUEUE_OUT_ADDRESS" ); |
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| 358 | |
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| 359 | #ifdef POSITION |
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| 360 | _component->interface_map (name ,"EXECUTE_QUEUE_OUT", |
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| 361 | _name,"WRITE_UNIT_OUT_"); |
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| 362 | #endif |
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| 363 | |
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| 364 | _component->port_map(name,"out_EXECUTE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" ); |
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| 365 | _component->port_map(name, "in_EXECUTE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" ); |
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| 366 | if (_param->_have_port_context_id) |
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| 367 | _component->port_map(name,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" ); |
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| 368 | if (_param->_have_port_front_end_id) |
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| 369 | _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" ); |
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| 370 | if (_param->_have_port_ooo_engine_id) |
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| 371 | _component->port_map(name,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID"); |
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| 372 | if (_param->_have_port_packet_id) |
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| 373 | _component->port_map(name,"out_EXECUTE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" ); |
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| 374 | //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" ); |
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| 375 | //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" ); |
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| 376 | _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" ); |
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| 377 | _component->port_map(name,"out_EXECUTE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" ); |
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| 378 | _component->port_map(name,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" ); |
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| 379 | _component->port_map(name,"out_EXECUTE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" ); |
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| 380 | } |
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| 381 | |
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| 382 | #ifdef POSITION |
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| 383 | _component->generate_file(); |
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| 384 | #endif |
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| 385 | |
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| 386 | log_printf(FUNC,Write_unit,FUNCTION,"End"); |
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| 387 | }; |
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| 388 | |
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| 389 | }; // end namespace write_unit |
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| 390 | }; // end namespace multi_write_unit |
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| 391 | }; // end namespace execute_loop |
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| 392 | }; // end namespace multi_execute_loop |
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| 393 | }; // end namespace core |
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| 394 | |
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| 395 | }; // end namespace behavioural |
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| 396 | }; // end namespace morpheo |
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