source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp @ 82

Last change on this file since 82 was 82, checked in by rosiere, 16 years ago
  • support locale (now must "just" translate)
  • update all component with new test format
  • update all component with usage
  • New component : decod queue and prediction_unit
  • Property svn:keywords set to Id
File size: 21.2 KB
Line 
1/*
2 * $Id: Write_unit_allocation.cpp 82 2008-05-01 16:48:45Z rosiere $
3 *
4 * [ Description ]
5 *
6 */
7
8#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h"
9#include "Behavioural/include/Allocation.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_execute_loop {
15namespace execute_loop {
16namespace multi_write_unit {
17namespace write_unit {
18
19
20
21#undef  FUNCTION
22#define FUNCTION "Write_unit::allocation"
23  void Write_unit::allocation (
24#ifdef STATISTICS
25                               morpheo::behavioural::Parameters_Statistics * param_statistics
26#else
27                               void
28#endif
29                               )
30  {
31    log_printf(FUNC,Write_unit,FUNCTION,"Begin");
32
33    _component   = new Component (_usage);
34
35    Entity * entity = _component->set_entity (_name       
36                                              ,"Write_unit"
37#ifdef POSITION
38                                              ,COMBINATORY
39#endif
40                                              );
41
42    _interfaces = entity->set_interfaces();
43
44    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
45
46      Interface * interface = _interfaces->set_interface(""
47#ifdef POSITION
48                                                         ,IN
49                                                         ,SOUTH,
50                                                         "Generalist interface"
51#endif
52                                                         );
53
54     in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
55     in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
56
57    // -----[ Interface "write_unit_in" ]--------------------------------   
58     {
59       ALLOC_INTERFACE ("write_unit_in", IN, WEST, "Input of write_unit");
60       
61       ALLOC_VALACK_IN ( in_WRITE_UNIT_IN_VAL,VAL);
62       ALLOC_VALACK_OUT(out_WRITE_UNIT_IN_ACK,ACK);
63       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_CONTEXT_ID   ,"context_id"   ,Tcontext_t        ,_param->_size_context_id       );
64       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t        ,_param->_size_front_end_id     );
65       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id    );
66       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID    ,"packet_id"    ,Tpacket_t         ,_param->_size_packet_id        );
67//     ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION    ,"operation"    ,Toperation_t      ,_param->_size_operation        );
68       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE         ,"type"         ,Ttype_t           ,_param->_size_type             );
69       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD     ,"write_rd"     ,Tcontrol_t        ,1                              );
70       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD   ,"num_reg_rd"   ,Tgeneral_address_t,_param->_size_general_register );
71       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RD      ,"data_rd"      ,Tgeneral_data_t   ,_param->_size_general_data     );
72       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RE     ,"write_re"     ,Tcontrol_t        ,1                              );
73       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RE   ,"num_reg_re"   ,Tspecial_address_t,_param->_size_special_register );
74       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RE      ,"data_re"      ,Tspecial_data_t   ,_param->_size_special_data     );
75       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION    ,"exception"    ,Texception_t      ,_param->_size_exception        );
76       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE  ,"no_sequence"  ,Tcontrol_t        ,1                              );
77       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS      ,"address"      ,Tgeneral_data_t   ,_param->_size_general_data     );
78     }
79
80    // -----[ Interface "write_unit_out" ]-------------------------------
81     {
82       ALLOC_INTERFACE ("write_unit_out", OUT, EAST, "Output of write_unit");
83       
84       ALLOC_VALACK_OUT(out_WRITE_UNIT_OUT_VAL,VAL);
85       ALLOC_VALACK_IN ( in_WRITE_UNIT_OUT_ACK,ACK);
86       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_CONTEXT_ID   ,"context_id"   ,Tcontext_t     ,_param->_size_context_id   );
87       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t     ,_param->_size_front_end_id );
88       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t     ,_param->_size_ooo_engine_id);
89       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID    ,"packet_id"    ,Tpacket_t      ,_param->_size_packet_id    );
90//     ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OPERATION    ,"operation"    ,Toperation_t   ,_param->_size_operation    );
91//     ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_TYPE         ,"type"         ,Ttype_t        ,_param->_size_type         );
92       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FLAGS        ,"flags"        ,Tspecial_data_t,_param->_size_special_data );
93       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION    ,"exception"    ,Texception_t   ,_param->_size_exception    );
94       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE  ,"no_sequence"  ,Tcontrol_t     ,1                          );
95       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS      ,"address"      ,Tgeneral_data_t,_param->_size_general_data );
96     }
97
98    // -----[ Interface "gpr_write" ]-------------------------------------
99     {
100       ALLOC1_INTERFACE("gpr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_gpr_write);
101
102       ALLOC1_VALACK_OUT(out_GPR_WRITE_VAL,VAL);
103       ALLOC1_VALACK_IN ( in_GPR_WRITE_ACK,ACK);
104       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   );
105       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG      ,"num_reg"      ,Tgeneral_address_t,_param->_size_general_register);
106       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA         ,"data"         ,Tgeneral_data_t   ,_param->_size_general_data    );
107     }
108
109    // -----[ Interface "spr_write" ]-------------------------------------
110     {
111       ALLOC1_INTERFACE("spr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_spr_write);
112
113       ALLOC1_VALACK_OUT(out_SPR_WRITE_VAL,VAL);
114       ALLOC1_VALACK_IN ( in_SPR_WRITE_ACK,ACK);
115       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   );
116       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG      ,"num_reg"      ,Tspecial_address_t,_param->_size_special_register);
117       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA         ,"data"         ,Tspecial_data_t   ,_param->_size_special_data    );
118     }
119
120    // -----[ Interface "bypass_write" ]----------------------------------
121     {
122       ALLOC1_INTERFACE("bypass_write", OUT, NORTH ,"Output of internal write_unit", _param->_nb_bypass_write);
123       
124       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   );
125       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_VAL      ,"gpr_val"      ,Tcontrol_t        ,1                             );
126       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_NUM_REG  ,"gpr_num_reg"  ,Tgeneral_address_t,_param->_size_general_register);
127       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_DATA     ,"gpr_data"     ,Tgeneral_data_t   ,_param->_size_general_data    );
128       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_VAL      ,"spr_val"      ,Tcontrol_t        ,1                             );
129       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG  ,"spr_num_reg"  ,Tspecial_address_t,_param->_size_special_register);
130       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA     ,"spr_data"     ,Tspecial_data_t   ,_param->_size_special_data    );
131     }
132
133
134    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
135
136     std::string name;
137
138     {
139       name = _name+"_write_queue";
140       
141       component_write_queue  = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Write_queue
142         (name.c_str()
143#ifdef STATISTICS
144          ,param_statistics
145#endif
146          ,_param->_param_write_queue
147          ,_usage);
148       
149       _component->set_component (component_write_queue->_component
150#ifdef POSITION
151                                  , 50, 50, 10, 10
152#endif
153                                  );
154     }
155
156     if (_param->_have_component_execute_queue)
157     {
158       name = _name+"_execute_queue";
159       
160       component_execute_queue  = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::execute_queue::Execute_queue
161         (name.c_str()
162#ifdef STATISTICS
163          ,param_statistics
164#endif
165          ,_param->_param_execute_queue
166          ,_usage);
167       
168       _component->set_component (component_execute_queue->_component
169#ifdef POSITION
170                                  , 50, 50, 10, 10
171#endif
172                                  );
173     }
174
175    // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
176     {
177       name = _name+"_write_queue";
178       std::cout << "Instance : " << name << std::endl;
179       
180#ifdef POSITION
181       _component->interface_map (name ,"",
182                                  _name,"");
183#endif
184
185       _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
186       _component->port_map(name,"in_NRESET", _name, "in_NRESET");
187
188
189#ifdef POSITION
190       _component->interface_map (name ,"write_queue_in",
191                                  _name,"write_unit_in");
192#endif
193
194       _component->port_map(name, "in_WRITE_QUEUE_IN_VAL"          , _name, "in_WRITE_UNIT_IN_VAL"          );
195       _component->port_map(name,"out_WRITE_QUEUE_IN_ACK"          , _name,"out_WRITE_UNIT_IN_ACK"          );
196       if (_param->_have_port_context_id)
197       _component->port_map(name, "in_WRITE_QUEUE_IN_CONTEXT_ID"   , _name, "in_WRITE_UNIT_IN_CONTEXT_ID"   );
198       if (_param->_have_port_front_end_id)
199       _component->port_map(name, "in_WRITE_QUEUE_IN_FRONT_END_ID" , _name, "in_WRITE_UNIT_IN_FRONT_END_ID" );
200       if (_param->_have_port_ooo_engine_id)
201       _component->port_map(name, "in_WRITE_QUEUE_IN_OOO_ENGINE_ID", _name, "in_WRITE_UNIT_IN_OOO_ENGINE_ID");
202       if (_param->_have_port_packet_id)
203       _component->port_map(name, "in_WRITE_QUEUE_IN_PACKET_ID"    , _name, "in_WRITE_UNIT_IN_PACKET_ID"    );
204     //_component->port_map(name, "in_WRITE_QUEUE_IN_OPERATION"    , _name, "in_WRITE_UNIT_IN_OPERATION"    );
205       _component->port_map(name, "in_WRITE_QUEUE_IN_TYPE"         , _name, "in_WRITE_UNIT_IN_TYPE"         );
206       _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RD"     , _name, "in_WRITE_UNIT_IN_WRITE_RD"     );
207       _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RD"   , _name, "in_WRITE_UNIT_IN_NUM_REG_RD"   );
208       _component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RD"      , _name, "in_WRITE_UNIT_IN_DATA_RD"      );
209       _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RE"     , _name, "in_WRITE_UNIT_IN_WRITE_RE"     );
210       _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RE"   , _name, "in_WRITE_UNIT_IN_NUM_REG_RE"   );
211       _component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RE"      , _name, "in_WRITE_UNIT_IN_DATA_RE"      );
212       _component->port_map(name, "in_WRITE_QUEUE_IN_EXCEPTION"    , _name, "in_WRITE_UNIT_IN_EXCEPTION"    );
213       _component->port_map(name, "in_WRITE_QUEUE_IN_NO_SEQUENCE"  , _name, "in_WRITE_UNIT_IN_NO_SEQUENCE"  );
214       _component->port_map(name, "in_WRITE_QUEUE_IN_ADDRESS"      , _name, "in_WRITE_UNIT_IN_ADDRESS"      );
215
216
217       if (_param->_have_component_execute_queue)
218         {
219#ifdef POSITION
220           _component->interface_map (name ,"write_queue_out",
221                                      _name+"_execute_queue", "execute_queue_in");
222#endif
223
224           _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL"          , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_VAL"          );
225           _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK"          , _name+"_execute_queue","out_EXECUTE_QUEUE_IN_ACK"          );
226           if (_param->_have_port_context_id)
227           _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID"   , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_CONTEXT_ID"   );
228           if (_param->_have_port_front_end_id)
229           _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FRONT_END_ID" );
230           if (_param->_have_port_ooo_engine_id)
231           _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID");
232           if (_param->_have_port_packet_id)
233           _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID"    , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_PACKET_ID"    );
234         //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION"    , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OPERATION"    );
235         //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE"         , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_TYPE"         );
236           _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS"        , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FLAGS"        );
237           _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION"    , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_EXCEPTION"    );
238           _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE"  , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_NO_SEQUENCE"  );
239           _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS"      , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_ADDRESS"      );
240         }
241       else
242         {
243#ifdef POSITION
244           _component->interface_map (name ,"write_queue_out",
245                                      _name,"write_unit_out");
246#endif
247
248           _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL"          , _name,"out_WRITE_UNIT_OUT_VAL"          );
249           _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK"          , _name, "in_WRITE_UNIT_OUT_ACK"          );
250           if (_param->_have_port_context_id)
251           _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID"   , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID"   );
252           if (_param->_have_port_front_end_id)
253           _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
254           if (_param->_have_port_ooo_engine_id)
255           _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
256           if (_param->_have_port_packet_id)
257           _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID"    , _name,"out_WRITE_UNIT_OUT_PACKET_ID"    );
258         //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION"    , _name,"out_WRITE_UNIT_OUT_OPERATION"    );
259         //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE"         , _name,"out_WRITE_UNIT_OUT_TYPE"         );
260           _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS"        , _name,"out_WRITE_UNIT_OUT_FLAGS"        );
261           _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION"    , _name,"out_WRITE_UNIT_OUT_EXCEPTION"    );
262           _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE"  , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE"  );
263           _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS"      , _name,"out_WRITE_UNIT_OUT_ADDRESS"      );
264         }       
265
266       for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
267         {
268#ifdef POSITION
269           _component->interface_map (name ,"gpr_write_"+toString(i),
270                                      _name,"gpr_write_"+toString(i));
271#endif     
272           
273           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_VAL"          ,_name,"out_GPR_WRITE_"+toString(i)+"_VAL"          );
274           _component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_ACK"          ,_name, "in_GPR_WRITE_"+toString(i)+"_ACK"          );
275           if (_param->_have_port_ooo_engine_id)
276           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
277           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG"      ,_name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG"      );
278           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_DATA"         ,_name,"out_GPR_WRITE_"+toString(i)+"_DATA"         );
279         }
280
281       for (uint32_t i=0; i<_param->_nb_spr_write; i++)
282         {
283#ifdef POSITION
284           _component->interface_map (name ,"spr_write_"+toString(i),
285                                      _name,"spr_write_"+toString(i));
286#endif     
287           
288           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_VAL"          ,_name,"out_SPR_WRITE_"+toString(i)+"_VAL"          );
289           _component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_ACK"          ,_name, "in_SPR_WRITE_"+toString(i)+"_ACK"          );
290           if (_param->_have_port_ooo_engine_id)
291           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
292           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG"      ,_name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG"      );
293           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_DATA"         ,_name,"out_SPR_WRITE_"+toString(i)+"_DATA"         );
294         }
295
296
297       for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
298         {
299#ifdef POSITION
300           _component->interface_map (name ,"bypass_write_"+toString(i),
301                                      _name,"bypass_write_"+toString(i));
302#endif     
303
304           if (_param->_have_port_ooo_engine_id)
305           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
306           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL"      ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL"      );
307           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG"  ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG"  );
308           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA"     ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA"     );
309           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL"      ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL"      );
310           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG"  ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG"  );
311           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA"     ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA"     );
312         }
313     }
314
315     if (_param->_have_component_execute_queue)
316       {
317         name = _name+"_execute_queue";
318         std::cout << "Instance : " << name << std::endl;
319         
320#ifdef POSITION
321         _component->interface_map (name ,"",
322                                    _name,"");
323#endif
324         
325         _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
326         _component->port_map(name,"in_NRESET", _name, "in_NRESET");
327         
328
329#ifdef POSITION
330         _component->interface_map (name ,"execute_queue_in",
331                                    _name+"_write_queue","write_queue_in");
332#endif
333
334         _component->port_map(name, "in_EXECUTE_QUEUE_IN_VAL"          , _name+"_write_queue","out_WRITE_QUEUE_OUT_VAL"          );
335         _component->port_map(name,"out_EXECUTE_QUEUE_IN_ACK"          , _name+"_write_queue", "in_WRITE_QUEUE_OUT_ACK"          );
336         if (_param->_have_port_context_id)
337         _component->port_map(name, "in_EXECUTE_QUEUE_IN_CONTEXT_ID"   , _name+"_write_queue","out_WRITE_QUEUE_OUT_CONTEXT_ID"   );
338         if (_param->_have_port_front_end_id)
339         _component->port_map(name, "in_EXECUTE_QUEUE_IN_FRONT_END_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_FRONT_END_ID" );
340         if (_param->_have_port_ooo_engine_id)
341         _component->port_map(name, "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID", _name+"_write_queue","out_WRITE_QUEUE_OUT_OOO_ENGINE_ID");
342         if (_param->_have_port_packet_id)
343         _component->port_map(name, "in_EXECUTE_QUEUE_IN_PACKET_ID"    , _name+"_write_queue","out_WRITE_QUEUE_OUT_PACKET_ID"    );
344       //_component->port_map(name, "in_EXECUTE_QUEUE_IN_OPERATION"    , _name+"_write_queue","out_WRITE_QUEUE_OUT_OPERATION"    );
345       //_component->port_map(name, "in_EXECUTE_QUEUE_IN_TYPE"         , _name+"_write_queue","out_WRITE_QUEUE_OUT_TYPE"         );
346         _component->port_map(name, "in_EXECUTE_QUEUE_IN_FLAGS"        , _name+"_write_queue","out_WRITE_QUEUE_OUT_FLAGS"        );
347         _component->port_map(name, "in_EXECUTE_QUEUE_IN_EXCEPTION"    , _name+"_write_queue","out_WRITE_QUEUE_OUT_EXCEPTION"    );
348         _component->port_map(name, "in_EXECUTE_QUEUE_IN_NO_SEQUENCE"  , _name+"_write_queue","out_WRITE_QUEUE_OUT_NO_SEQUENCE"  );
349         _component->port_map(name, "in_EXECUTE_QUEUE_IN_ADDRESS"      , _name+"_write_queue","out_WRITE_QUEUE_OUT_ADDRESS"      );
350
351#ifdef POSITION
352           _component->interface_map (name ,"execute_queue_out",
353                                      _name,"write_unit_out");
354#endif
355
356           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_VAL"          , _name,"out_WRITE_UNIT_OUT_VAL"          );
357           _component->port_map(name, "in_EXECUTE_QUEUE_OUT_ACK"          , _name, "in_WRITE_UNIT_OUT_ACK"          );
358           if (_param->_have_port_context_id)
359           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID"   , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID"   );
360           if (_param->_have_port_front_end_id)
361           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
362           if (_param->_have_port_ooo_engine_id)
363           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
364           if (_param->_have_port_packet_id)
365           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_PACKET_ID"    , _name,"out_WRITE_UNIT_OUT_PACKET_ID"    );
366         //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OPERATION"    , _name,"out_WRITE_UNIT_OUT_OPERATION"    );
367         //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_TYPE"         , _name,"out_WRITE_UNIT_OUT_TYPE"         );
368           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FLAGS"        , _name,"out_WRITE_UNIT_OUT_FLAGS"        );
369           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_EXCEPTION"    , _name,"out_WRITE_UNIT_OUT_EXCEPTION"    );
370           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE"  , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE"  );
371           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_ADDRESS"      , _name,"out_WRITE_UNIT_OUT_ADDRESS"      );
372       }
373
374#ifdef POSITION
375    _component->generate_file();
376#endif
377
378    log_printf(FUNC,Write_unit,FUNCTION,"End");
379  };
380
381}; // end namespace write_unit
382}; // end namespace multi_write_unit
383}; // end namespace execute_loop
384}; // end namespace multi_execute_loop
385}; // end namespace core
386
387}; // end namespace behavioural
388}; // end namespace morpheo             
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