1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Context_State_genMoore.cpp 111 2009-02-27 18:37:40Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace context_state { |
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17 | |
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18 | |
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19 | #undef FUNCTION |
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20 | #define FUNCTION "Context_State::genMoore" |
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21 | void Context_State::genMoore (void) |
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22 | { |
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23 | log_begin(Context_State,FUNCTION); |
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24 | log_function(Context_State,FUNCTION,_name.c_str()); |
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25 | |
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26 | // ------------------------------------------------------------------- |
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27 | // -----[ EVENT ]----------------------------------------------------- |
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28 | // ------------------------------------------------------------------- |
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29 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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30 | { |
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31 | context_state_t state = reg_STATE [i]; |
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32 | |
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33 | Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR ) or |
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34 | (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or |
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35 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR) or |
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36 | (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or |
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37 | (state == CONTEXT_STATE_KO_PSYNC_ADDR ) or |
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38 | (state == CONTEXT_STATE_KO_CSYNC_ADDR)); |
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39 | |
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40 | // SR can't change in this cycle |
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41 | // Exception Prefix High |
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42 | Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0); |
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43 | Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i]; |
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44 | Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]); |
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45 | Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_IS_DS_TAKE [i]); |
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46 | // excep : address exception |
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47 | // miss : address delay_slot, and address dest |
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48 | // psync : address next |
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49 | // csync : address next |
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50 | Tevent_type_t type ;//[nb_context] |
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51 | Tdepth_t depth = reg_EVENT_DEPTH [i]; |
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52 | |
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53 | switch (state) |
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54 | { |
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55 | case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; |
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56 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: |
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57 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break; |
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58 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : (type = EVENT_TYPE_LOAD_MISS_SPECULATION ); break; |
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59 | case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break; |
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60 | case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break; |
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61 | default : (type = EVENT_TYPE_NONE ); break; |
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62 | } |
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63 | // (type = EVENT_TYPE_SPR_ACCESS ); |
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64 | // (type = EVENT_TYPE_MSYNC ); |
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65 | // (type = EVENT_TYPE_BRANCH_NO_ACCURATE); |
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66 | |
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67 | internal_EVENT_VAL [i] = val; |
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68 | PORT_WRITE(out_EVENT_VAL [i], val); |
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69 | PORT_WRITE(out_EVENT_ADDRESS [i], address); |
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70 | PORT_WRITE(out_EVENT_ADDRESS_NEXT [i], address_next); |
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71 | PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val); |
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72 | PORT_WRITE(out_EVENT_IS_DS_TAKE [i], is_ds_take); |
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73 | PORT_WRITE(out_EVENT_TYPE [i], type); |
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74 | if (_param->_have_port_depth) |
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75 | PORT_WRITE(out_EVENT_DEPTH [i], depth); |
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76 | |
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77 | log_printf(TRACE,Context_State,FUNCTION," * EVENT Context : %d", i); |
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78 | log_printf(TRACE,Context_State,FUNCTION," * VAL : %d", val); |
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79 | log_printf(TRACE,Context_State,FUNCTION," * ADDRESS : %.8x (%.8x)", address , address <<2); |
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80 | log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)", address_next, address_next<<2); |
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81 | log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT_VAL : %d", address_next_val); |
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82 | log_printf(TRACE,Context_State,FUNCTION," * IS_DS_TAKE : %d", is_ds_take); |
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83 | log_printf(TRACE,Context_State,FUNCTION," * TYPE : %d", type); |
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84 | log_printf(TRACE,Context_State,FUNCTION," * DEPTH : %d", depth); |
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85 | } |
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86 | |
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87 | // ------------------------------------------------------------------- |
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88 | // -----[ SPR_EVENT ]------------------------------------------------- |
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89 | // ------------------------------------------------------------------- |
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90 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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91 | { |
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92 | context_state_t state = reg_STATE [i]; |
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93 | |
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94 | internal_SPR_EVENT_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR ); |
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95 | |
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96 | PORT_WRITE(out_SPR_EVENT_VAL [i], internal_SPR_EVENT_VAL [i]); |
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97 | PORT_WRITE(out_SPR_EVENT_EPCR [i], reg_EVENT_ADDRESS_EPCR [i]); |
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98 | PORT_WRITE(out_SPR_EVENT_EEAR [i], reg_EVENT_ADDRESS_EEAR [i]); |
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99 | PORT_WRITE(out_SPR_EVENT_EEAR_WEN [i], reg_EVENT_ADDRESS_EEAR_VAL [i]); |
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100 | PORT_WRITE(out_SPR_EVENT_SR_DSX [i], reg_EVENT_IS_DELAY_SLOT [i]); |
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101 | PORT_WRITE(out_SPR_EVENT_SR_TO_ESR [i], 1); |
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102 | } |
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103 | |
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104 | // ------------------------------------------------------------------- |
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105 | // -----[ CONTEXT ]--------------------------------------------------- |
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106 | // ------------------------------------------------------------------- |
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107 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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108 | { |
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109 | context_state_t state = reg_STATE [i]; |
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110 | |
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111 | // PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK ) or |
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112 | // (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or |
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113 | // (state==CONTEXT_STATE_KO_SPR_ISSUE ))); |
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114 | PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], (state==CONTEXT_STATE_OK)); |
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115 | } |
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116 | |
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117 | log_end(Context_State,FUNCTION); |
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118 | }; |
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119 | |
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120 | }; // end namespace context_state |
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121 | }; // end namespace front_end |
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122 | }; // end namespace multi_front_end |
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123 | }; // end namespace core |
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124 | |
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125 | }; // end namespace behavioural |
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126 | }; // end namespace morpheo |
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127 | #endif |
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