1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Context_State_transition.cpp 128 2009-06-26 08:43:23Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace context_state { |
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17 | |
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18 | // #define MANAGE_EVENT MANAGE_EVENT_WAIT_ALL |
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19 | // #define MANAGE_EVENT MANAGE_EVENT_WAIT_DECODE |
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20 | #define MANAGE_EVENT MANAGE_EVENT_NO_WAIT |
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21 | |
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22 | #define PRIORITY_MISS_LOAD 3 |
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23 | #define PRIORITY_MISS_BRANCH 2 |
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24 | #define PRIORITY_EXCEPTION 1 |
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25 | #define PRIORITY_NONE 0 |
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26 | |
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27 | #define get_priority(x) \ |
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28 | (((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or \ |
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29 | (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or \ |
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30 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or \ |
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31 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND ) or \ |
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32 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?PRIORITY_MISS_LOAD: \ |
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33 | (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or \ |
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34 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or \ |
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35 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ))?PRIORITY_MISS_BRANCH: \ |
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36 | ((state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION: \ |
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37 | 0))) |
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38 | |
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39 | #undef FUNCTION |
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40 | #define FUNCTION "Context_State::transition" |
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41 | void Context_State::transition (void) |
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42 | { |
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43 | log_begin(Context_State,FUNCTION); |
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44 | log_function(Context_State,FUNCTION,_name.c_str()); |
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45 | |
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46 | if (PORT_READ(in_NRESET) == 0) |
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47 | { |
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48 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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49 | { |
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50 | reg_STATE [i] = CONTEXT_STATE_OK; |
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51 | reg_INTERRUPT_ENABLE [i] = 0; |
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52 | |
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53 | reg_EVENT_ADDRESS [i] = 0; // not necessary |
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54 | reg_EVENT_ADDRESS_EPCR [i] = 0; // not necessary |
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55 | reg_EVENT_ADDRESS_EPCR_VAL [i] = 0; // not necessary |
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56 | reg_EVENT_ADDRESS_EEAR [i] = 0; // not necessary |
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57 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; // not necessary |
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58 | reg_EVENT_IS_DELAY_SLOT [i] = 0; // not necessary |
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59 | reg_EVENT_IS_DS_TAKE [i] = 0; // not necessary |
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60 | reg_EVENT_DEPTH [i] = 0; // not necessary |
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61 | reg_EVENT_FLUSH_ONLY [i] = 0; // not necessary |
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62 | } |
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63 | } |
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64 | else |
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65 | { |
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66 | // ------------------------------------------------------------------- |
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67 | // -----[ next state ]------------------------------------------------ |
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68 | // ------------------------------------------------------------------- |
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69 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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70 | { |
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71 | // uint32_t x = _param->_link_context_to_decod_unit [i]; |
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72 | |
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73 | Tcounter_t inst_commit_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]); |
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74 | // Tcounter_t inst_commit_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]); |
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75 | Tcounter_t inst_decod_all = PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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76 | Tcounter_t inst_all = inst_commit_all + inst_decod_all; |
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77 | // Tcounter_t inst_mem = inst_commit_mem + inst_decod_all; |
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78 | bool condition = ( (MANAGE_EVENT == MANAGE_EVENT_WAIT_ALL )?(inst_all == 0): |
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79 | ((MANAGE_EVENT == MANAGE_EVENT_WAIT_DECODE)?(inst_decod_all == 0): |
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80 | true)); |
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81 | |
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82 | context_state_t state = reg_STATE [i]; |
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83 | |
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84 | switch (state) |
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85 | { |
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86 | case CONTEXT_STATE_OK : |
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87 | { |
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88 | // nothing, wait an event |
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89 | break; |
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90 | } |
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91 | case CONTEXT_STATE_KO_EXCEP : |
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92 | { |
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93 | // Wait end of all instruction |
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94 | if (inst_all == 0) |
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95 | // if (inst_decod_all == 0) |
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96 | state = CONTEXT_STATE_KO_EXCEP_ADDR; |
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97 | break; |
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98 | } |
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99 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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100 | { |
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101 | // nothing, wait the update of internal register (pc) |
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102 | break; |
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103 | } |
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104 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
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105 | { |
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106 | // nothing : wait end of update upt |
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107 | break; |
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108 | } |
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109 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
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110 | { |
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111 | if (condition) |
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112 | // state = CONTEXT_STATE_OK; |
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113 | state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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114 | break; |
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115 | } |
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116 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : |
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117 | { |
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118 | // Wait end of all instruction |
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119 | if (condition) |
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120 | state = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
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121 | |
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122 | break; |
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123 | } |
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124 | case CONTEXT_STATE_KO_EXCEP_SPR : |
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125 | { |
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126 | // nothing, wait the update of internal register (epcr, eear, sr, esr) |
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127 | break; |
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128 | } |
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129 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
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130 | { |
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131 | // nothing, wait the update of internal register (pc) |
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132 | break; |
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133 | } |
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134 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
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135 | { |
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136 | // nothing, wait the update of internal register (pc) |
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137 | break; |
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138 | } |
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139 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE : |
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140 | { |
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141 | // nothing : wait end of update upt |
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142 | break; |
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143 | } |
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144 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
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145 | { |
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146 | // nothing, wait the update of internal register (pc) |
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147 | break; |
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148 | } |
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149 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
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150 | { |
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151 | // Wait end of all instruction |
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152 | if (condition) |
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153 | // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) |
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154 | state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
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155 | break; |
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156 | } |
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157 | // case CONTEXT_STATE_KO_PSYNC : |
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158 | // { |
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159 | // // Wait end of all instruction |
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160 | // if (inst_all == 0) |
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161 | // state = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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162 | // break; |
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163 | // } |
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164 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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165 | { |
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166 | // nothing, wait end of flush (ifetch) |
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167 | if (inst_all == 0) |
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168 | // state = CONTEXT_STATE_KO_PSYNC_ADDR; |
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169 | state = CONTEXT_STATE_OK; |
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170 | |
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171 | break; |
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172 | } |
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173 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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174 | { |
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175 | // nothing, wait the pc write |
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176 | break; |
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177 | } |
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178 | // case CONTEXT_STATE_KO_CSYNC : |
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179 | // { |
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180 | // // Wait end of all instruction |
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181 | // if (inst_all == 0) |
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182 | // state = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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183 | // break; |
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184 | // } |
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185 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
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186 | { |
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187 | // nothing, wait end of flush (all internal structure) |
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188 | if (inst_all == 0) |
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189 | state = CONTEXT_STATE_KO_CSYNC_ADDR; |
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190 | break; |
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191 | } |
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192 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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193 | { |
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194 | // nothing, wait the pc write |
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195 | break; |
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196 | } |
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197 | // case CONTEXT_STATE_KO_MSYNC : |
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198 | // { |
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199 | // // Wait end of memory instruction |
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200 | // if (inst_mem == 0) |
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201 | // state = CONTEXT_STATE_KO_MSYNC_ISSUE; |
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202 | // break; |
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203 | // } |
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204 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
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205 | // { |
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206 | // // Wait the msync issue |
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207 | // if (inst_mem != 0) |
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208 | // state = CONTEXT_STATE_KO_MSYNC_EXEC; |
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209 | // break; |
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210 | // } |
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211 | case CONTEXT_STATE_KO_MSYNC_EXEC : |
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212 | { |
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213 | // Wait the end of msync |
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214 | if (inst_all == 0) |
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215 | state = CONTEXT_STATE_OK; |
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216 | break; |
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217 | } |
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218 | // case CONTEXT_STATE_KO_SPR : |
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219 | // { |
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220 | // // Wait end of all instruction |
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221 | // if (inst_all == 0) |
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222 | // state = CONTEXT_STATE_KO_SPR_ISSUE; |
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223 | // break; |
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224 | // } |
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225 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
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226 | // { |
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227 | // // Wait the spr_access issue |
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228 | // if (inst_all != 0) |
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229 | // state = CONTEXT_STATE_KO_SPR_EXEC; |
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230 | // break; |
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231 | // } |
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232 | case CONTEXT_STATE_KO_SPR_EXEC : |
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233 | { |
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234 | // Wait the spr_access execution |
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235 | if (inst_all == 0) |
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236 | state = CONTEXT_STATE_OK; |
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237 | break; |
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238 | } |
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239 | |
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240 | default : |
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241 | { |
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242 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); |
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243 | } |
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244 | } |
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245 | reg_STATE [i] = state; |
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246 | } |
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247 | |
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248 | // ------------------------------------------------------------------- |
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249 | // -----[ BRANCH_EVENT ]---------------------------------------------- |
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250 | // ------------------------------------------------------------------- |
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251 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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252 | if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) |
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253 | { |
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254 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); |
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255 | |
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256 | context_state_t state = reg_STATE [i]; |
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257 | |
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258 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; |
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259 | Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; |
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260 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; |
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261 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; |
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262 | |
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263 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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264 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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265 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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266 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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267 | |
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268 | // priority : miss_load > miss_branch > excep > spr/sync |
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269 | uint8_t priority0 = get_priority(state); |
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270 | uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss |
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271 | |
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272 | // is_valid = can modify local information |
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273 | // if context_state_ok : yes |
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274 | // if context_state_ko : test the depth, and the priority of event |
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275 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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276 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or |
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277 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or |
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278 | (depth1< depth0) or |
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279 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
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280 | |
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281 | bool is_invalid = priority0 == PRIORITY_MISS_LOAD; |
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282 | |
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283 | #ifdef DEBUG_TEST |
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284 | if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and |
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285 | (depth0 != depth1)) |
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286 | throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str())); |
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287 | #endif |
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288 | |
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289 | log_printf(TRACE,Context_State,FUNCTION," * state : %s",toString(state).c_str()); |
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290 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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291 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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292 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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293 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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294 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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295 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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296 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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297 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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298 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
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299 | log_printf(TRACE,Context_State,FUNCTION," * is_invalid : %d",is_invalid); |
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300 | |
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301 | if (is_valid and not is_invalid) |
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302 | { |
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303 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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304 | |
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305 | if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) |
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306 | { |
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307 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
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308 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
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309 | // #else |
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310 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
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311 | // #endif |
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312 | } |
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313 | else |
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314 | { |
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315 | Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE [i]); |
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316 | Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); |
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317 | |
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318 | log_printf(TRACE,Context_State,FUNCTION," * dest_val : %d",dest_val ); |
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319 | log_printf(TRACE,Context_State,FUNCTION," * can_continue: %d",can_continue); |
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320 | |
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321 | if (can_continue) |
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322 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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323 | else |
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324 | { |
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325 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
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326 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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327 | // #else |
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328 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; |
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329 | // #endif |
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330 | } |
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331 | |
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332 | reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot |
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333 | reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next |
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334 | reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; |
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335 | //reg_EVENT_ADDRESS_EEAR [i] = 0; |
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336 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; |
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337 | reg_EVENT_IS_DELAY_SLOT [i] = 1; |
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338 | reg_EVENT_IS_DS_TAKE [i] = dest_val; |
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339 | reg_EVENT_DEPTH [i] = depth; |
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340 | reg_EVENT_FLUSH_ONLY [i] = can_continue; |
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341 | } |
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342 | } |
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343 | } |
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344 | |
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345 | // ------------------------------------------------------------------- |
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346 | // -----[ DECOD_EVENT ]----------------------------------------------- |
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347 | // ------------------------------------------------------------------- |
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348 | |
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349 | for (uint32_t i=0; i<_param->_nb_decod_unit; i++) |
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350 | if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) |
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351 | { |
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352 | log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); |
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353 | |
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354 | Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; |
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355 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; |
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356 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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357 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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358 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
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359 | |
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360 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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361 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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362 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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363 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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364 | |
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365 | context_state_t state = reg_STATE [context]; |
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366 | Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); |
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367 | |
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368 | // miss_load > miss_branch > excep > spr/sync |
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369 | uint8_t priority0 = get_priority(state); |
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370 | uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE; |
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371 | |
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372 | // is_valid = can modify local information |
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373 | // if context_state_ok : yes |
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374 | // if context_state_ko : test the depth, and the priority of envent |
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375 | |
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376 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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377 | (depth1< depth0) or |
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378 | ((depth1==depth0) and (priority1>=priority0))); |
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379 | |
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380 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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381 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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382 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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383 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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384 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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385 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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386 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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387 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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388 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
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389 | |
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390 | if (is_valid) |
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391 | { |
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392 | log_printf(TRACE,Context_State,FUNCTION," * is_valid"); |
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393 | |
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394 | // decod : |
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395 | // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) |
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396 | context_state_t state_next = state; |
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397 | Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); |
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398 | Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); |
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399 | |
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400 | switch (type) |
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401 | { |
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402 | case EVENT_TYPE_EXCEPTION : |
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403 | { |
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404 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); |
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405 | |
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406 | state_next = CONTEXT_STATE_KO_EXCEP; |
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407 | |
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408 | break; |
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409 | } |
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410 | case EVENT_TYPE_SPR_ACCESS : |
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411 | { |
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412 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); |
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413 | |
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414 | // state_next = CONTEXT_STATE_KO_SPR ; |
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415 | state_next = CONTEXT_STATE_KO_SPR_EXEC; |
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416 | address++; // take next address |
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417 | // if (is_delay_slot) |
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418 | // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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419 | break; |
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420 | } |
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421 | case EVENT_TYPE_MSYNC : |
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422 | { |
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423 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); |
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424 | |
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425 | // state_next = CONTEXT_STATE_KO_MSYNC; |
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426 | state_next = CONTEXT_STATE_KO_MSYNC_EXEC; |
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427 | address++; // take next address |
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428 | // if (is_delay_slot) |
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429 | // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); |
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430 | break; |
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431 | } |
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432 | case EVENT_TYPE_PSYNC : |
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433 | { |
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434 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); |
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435 | |
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436 | // state_next = CONTEXT_STATE_KO_PSYNC; |
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437 | state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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438 | address++; // take next address |
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439 | if (is_delay_slot) |
---|
440 | throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); |
---|
441 | break; |
---|
442 | } |
---|
443 | case EVENT_TYPE_CSYNC : |
---|
444 | { |
---|
445 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); |
---|
446 | |
---|
447 | // state_next = CONTEXT_STATE_KO_CSYNC; |
---|
448 | state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; |
---|
449 | address++; // take next address |
---|
450 | if (is_delay_slot) |
---|
451 | throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); |
---|
452 | break; |
---|
453 | } |
---|
454 | case EVENT_TYPE_NONE : |
---|
455 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
456 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
457 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
458 | default : |
---|
459 | { |
---|
460 | throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); |
---|
461 | } |
---|
462 | } |
---|
463 | |
---|
464 | reg_STATE [context] = state_next; |
---|
465 | reg_EVENT_ADDRESS [context] = address; |
---|
466 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); |
---|
467 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
---|
468 | //reg_EVENT_ADDRESS_EEAR [context] |
---|
469 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
---|
470 | reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; |
---|
471 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
472 | reg_EVENT_DEPTH [context] = depth; |
---|
473 | reg_EVENT_FLUSH_ONLY [context] = false; |
---|
474 | } |
---|
475 | } |
---|
476 | |
---|
477 | // ------------------------------------------------------------------- |
---|
478 | // -----[ EVENT ]----------------------------------------------------- |
---|
479 | // ------------------------------------------------------------------- |
---|
480 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
481 | if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) |
---|
482 | { |
---|
483 | log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); |
---|
484 | // Write pc |
---|
485 | context_state_t state = reg_STATE [i]; |
---|
486 | |
---|
487 | switch (state) |
---|
488 | { |
---|
489 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
---|
490 | { |
---|
491 | reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; |
---|
492 | break; |
---|
493 | } |
---|
494 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: |
---|
495 | |
---|
496 | // { |
---|
497 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) |
---|
498 | // break; |
---|
499 | // } |
---|
500 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
---|
501 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
---|
502 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
---|
503 | { |
---|
504 | reg_STATE [i] = CONTEXT_STATE_OK; |
---|
505 | break; |
---|
506 | } |
---|
507 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: |
---|
508 | { |
---|
509 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
---|
510 | break; |
---|
511 | } |
---|
512 | default : |
---|
513 | { |
---|
514 | #ifdef DEBUG_TEST |
---|
515 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
---|
516 | #endif |
---|
517 | break; |
---|
518 | } |
---|
519 | } |
---|
520 | } |
---|
521 | |
---|
522 | // ------------------------------------------------------------------- |
---|
523 | // -----[ BRANCH_COMPLETE ]---------------------------------------------- |
---|
524 | // ------------------------------------------------------------------- |
---|
525 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
---|
526 | if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i] |
---|
527 | and PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) |
---|
528 | { |
---|
529 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
---|
530 | |
---|
531 | Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
---|
532 | |
---|
533 | context_state_t state = reg_STATE [context_id]; |
---|
534 | |
---|
535 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
---|
536 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context_id]; |
---|
537 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context_id]):0; |
---|
538 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context_id]; |
---|
539 | |
---|
540 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
541 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
---|
542 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
---|
543 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
---|
544 | |
---|
545 | // priority : miss_load > miss_branch > excep > spr/sync |
---|
546 | uint8_t priority0 = get_priority(state); |
---|
547 | uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss |
---|
548 | |
---|
549 | // is_valid = can modify local information |
---|
550 | // if context_state_ok : yes |
---|
551 | // if context_state_ko : test the depth, and the priority of event |
---|
552 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
---|
553 | (depth1< depth0) or |
---|
554 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
---|
555 | |
---|
556 | log_printf(TRACE,Context_State,FUNCTION," * context_id: %d",context_id); |
---|
557 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
558 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
559 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
560 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
561 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
562 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
563 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
564 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
565 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
566 | |
---|
567 | if (is_valid) |
---|
568 | { |
---|
569 | // reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
---|
570 | reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE; |
---|
571 | reg_EVENT_DEPTH [context_id] = depth; |
---|
572 | reg_EVENT_FLUSH_ONLY [context_id] = false; |
---|
573 | } |
---|
574 | } |
---|
575 | |
---|
576 | // ------------------------------------------------------------------- |
---|
577 | // -----[ COMMIT_EVENT ]---------------------------------------------- |
---|
578 | // ------------------------------------------------------------------- |
---|
579 | |
---|
580 | if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) |
---|
581 | { |
---|
582 | log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); |
---|
583 | |
---|
584 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; |
---|
585 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; |
---|
586 | // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
---|
587 | // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
---|
588 | // Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
---|
589 | |
---|
590 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
591 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
---|
592 | // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
---|
593 | // // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
---|
594 | |
---|
595 | context_state_t state = reg_STATE [context]; |
---|
596 | Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); |
---|
597 | |
---|
598 | // // miss > excep > spr/sync |
---|
599 | // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or |
---|
600 | // (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or |
---|
601 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or |
---|
602 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or |
---|
603 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ) or |
---|
604 | // (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or |
---|
605 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
---|
606 | // uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) |
---|
607 | |
---|
608 | // // is_valid = can modify local information |
---|
609 | // // if context_state_ok : yes |
---|
610 | // // if context_state_ko : test the depth, and the priority of envent |
---|
611 | |
---|
612 | // bool is_valid = ((state == CONTEXT_STATE_OK) or |
---|
613 | // (depth1< depth0) or |
---|
614 | // ((depth1==depth0) and (priority1>=priority0))); |
---|
615 | |
---|
616 | // if commit send an event, also they have not yet event previous this instruction |
---|
617 | bool is_valid = true; |
---|
618 | |
---|
619 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
620 | // log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
621 | // log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
622 | // log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
623 | // log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
624 | // log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
625 | // log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
626 | // log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
627 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
628 | |
---|
629 | if (is_valid) |
---|
630 | { |
---|
631 | // commit |
---|
632 | // type : exception |
---|
633 | context_state_t state_next = state; |
---|
634 | switch (type) |
---|
635 | { |
---|
636 | case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} |
---|
637 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
638 | { |
---|
639 | // Test if previous branch occure |
---|
640 | switch (state) |
---|
641 | { |
---|
642 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
---|
643 | { |
---|
644 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE; |
---|
645 | break; |
---|
646 | } |
---|
647 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
---|
648 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
---|
649 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
---|
650 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
---|
651 | { |
---|
652 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
---|
653 | // state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
---|
654 | // #else |
---|
655 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
---|
656 | // #endif |
---|
657 | break; |
---|
658 | } |
---|
659 | default : |
---|
660 | { |
---|
661 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
---|
662 | // state_next = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
---|
663 | // #else |
---|
664 | state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; |
---|
665 | // #endif |
---|
666 | break; |
---|
667 | } |
---|
668 | } |
---|
669 | |
---|
670 | depth = (depth+1)%_param->_nb_inst_branch_speculated[context]; |
---|
671 | |
---|
672 | break; |
---|
673 | } |
---|
674 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
675 | case EVENT_TYPE_SPR_ACCESS : |
---|
676 | case EVENT_TYPE_MSYNC : |
---|
677 | case EVENT_TYPE_PSYNC : |
---|
678 | case EVENT_TYPE_CSYNC : |
---|
679 | case EVENT_TYPE_NONE : |
---|
680 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
681 | default : |
---|
682 | { |
---|
683 | throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); |
---|
684 | } |
---|
685 | } |
---|
686 | reg_STATE [context] = state_next; |
---|
687 | reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); |
---|
688 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); |
---|
689 | reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); |
---|
690 | reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); |
---|
691 | reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
---|
692 | reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); |
---|
693 | reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
694 | reg_EVENT_DEPTH [context] = depth; |
---|
695 | reg_EVENT_FLUSH_ONLY [context] = false; |
---|
696 | } |
---|
697 | } |
---|
698 | |
---|
699 | // ------------------------------------------------------------------- |
---|
700 | // -----[ SPR_EVENT ]------------------------------------------------- |
---|
701 | // ------------------------------------------------------------------- |
---|
702 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
703 | if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) |
---|
704 | { |
---|
705 | log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); |
---|
706 | |
---|
707 | // Write spr |
---|
708 | #ifdef DEBUG_TEST |
---|
709 | context_state_t state = reg_STATE [i]; |
---|
710 | |
---|
711 | if (state != CONTEXT_STATE_KO_EXCEP_SPR) |
---|
712 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
---|
713 | #endif |
---|
714 | |
---|
715 | reg_STATE [i] = CONTEXT_STATE_OK; |
---|
716 | } |
---|
717 | |
---|
718 | // ------------------------------------------------------------------- |
---|
719 | // -----[ INTERRUPT ]------------------------------------------------- |
---|
720 | // ------------------------------------------------------------------- |
---|
721 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
722 | { |
---|
723 | reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); |
---|
724 | |
---|
725 | if (reg_INTERRUPT_ENABLE [i]) |
---|
726 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); |
---|
727 | } |
---|
728 | |
---|
729 | |
---|
730 | #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
---|
731 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
732 | switch (reg_STATE [i]) |
---|
733 | { |
---|
734 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR ; break; |
---|
735 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR ; break; |
---|
736 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; break; |
---|
737 | default : break; |
---|
738 | } |
---|
739 | #endif |
---|
740 | } |
---|
741 | |
---|
742 | |
---|
743 | #ifdef STATISTICS |
---|
744 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
745 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
746 | switch(reg_STATE[i]) |
---|
747 | { |
---|
748 | case CONTEXT_STATE_OK : (*_stat_nb_cycle_state_ok [i])++; break; |
---|
749 | |
---|
750 | case CONTEXT_STATE_KO_EXCEP : |
---|
751 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
---|
752 | case CONTEXT_STATE_KO_EXCEP_SPR : (*_stat_nb_cycle_state_ko_excep [i])++; break; |
---|
753 | |
---|
754 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
---|
755 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
---|
756 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : (*_stat_nb_cycle_state_ko_miss_branch [i])++; break; |
---|
757 | |
---|
758 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
---|
759 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : (*_stat_nb_cycle_state_ko_miss_load [i])++; break; |
---|
760 | |
---|
761 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE: |
---|
762 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
---|
763 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : (*_stat_nb_cycle_state_ko_miss_load_and_branch [i])++; break; |
---|
764 | |
---|
765 | // case CONTEXT_STATE_KO_MSYNC : |
---|
766 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
---|
767 | case CONTEXT_STATE_KO_MSYNC_EXEC : (*_stat_nb_cycle_state_ko_msync [i])++; break; |
---|
768 | |
---|
769 | // case CONTEXT_STATE_KO_PSYNC : |
---|
770 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
---|
771 | case CONTEXT_STATE_KO_PSYNC_ADDR : (*_stat_nb_cycle_state_ko_psync [i])++; break; |
---|
772 | |
---|
773 | // case CONTEXT_STATE_KO_CSYNC : |
---|
774 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
---|
775 | case CONTEXT_STATE_KO_CSYNC_ADDR : (*_stat_nb_cycle_state_ko_csync [i])++; break; |
---|
776 | |
---|
777 | // case CONTEXT_STATE_KO_SPR : |
---|
778 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
---|
779 | case CONTEXT_STATE_KO_SPR_EXEC : (*_stat_nb_cycle_state_ko_spr [i])++; break; |
---|
780 | } |
---|
781 | #endif |
---|
782 | |
---|
783 | |
---|
784 | |
---|
785 | #if DEBUG >= DEBUG_TRACE |
---|
786 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
787 | { |
---|
788 | log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); |
---|
789 | log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); |
---|
790 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); |
---|
791 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); |
---|
792 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); |
---|
793 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); |
---|
794 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); |
---|
795 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); |
---|
796 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); |
---|
797 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
---|
798 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_FLUSH_ONLY : %d" ,reg_EVENT_FLUSH_ONLY [i]); |
---|
799 | } |
---|
800 | #endif |
---|
801 | |
---|
802 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
803 | end_cycle (); |
---|
804 | #endif |
---|
805 | |
---|
806 | log_end(Context_State,FUNCTION); |
---|
807 | }; |
---|
808 | |
---|
809 | }; // end namespace context_state |
---|
810 | }; // end namespace front_end |
---|
811 | }; // end namespace multi_front_end |
---|
812 | }; // end namespace core |
---|
813 | |
---|
814 | }; // end namespace behavioural |
---|
815 | }; // end namespace morpheo |
---|
816 | #endif |
---|