Changeset 128 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
- Timestamp:
- Jun 26, 2009, 10:43:23 AM (15 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r124 r128 50 50 reg_STATE [i] = CONTEXT_STATE_OK; 51 51 reg_INTERRUPT_ENABLE [i] = 0; 52 reg_EVENT_DEPTH [i] = 0; // unacessary 52 53 reg_EVENT_ADDRESS [i] = 0; // not necessary 54 reg_EVENT_ADDRESS_EPCR [i] = 0; // not necessary 55 reg_EVENT_ADDRESS_EPCR_VAL [i] = 0; // not necessary 56 reg_EVENT_ADDRESS_EEAR [i] = 0; // not necessary 57 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; // not necessary 58 reg_EVENT_IS_DELAY_SLOT [i] = 0; // not necessary 59 reg_EVENT_IS_DS_TAKE [i] = 0; // not necessary 60 reg_EVENT_DEPTH [i] = 0; // not necessary 61 reg_EVENT_FLUSH_ONLY [i] = 0; // not necessary 53 62 } 54 63 } … … 236 245 reg_STATE [i] = state; 237 246 } 247 248 // ------------------------------------------------------------------- 249 // -----[ BRANCH_EVENT ]---------------------------------------------- 250 // ------------------------------------------------------------------- 251 for (uint32_t i=0; i<_param->_nb_context; ++i) 252 if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) 253 { 254 log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); 255 256 context_state_t state = reg_STATE [i]; 257 258 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; 259 Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; 260 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; 261 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; 262 263 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 264 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 265 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 266 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 267 268 // priority : miss_load > miss_branch > excep > spr/sync 269 uint8_t priority0 = get_priority(state); 270 uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss 271 272 // is_valid = can modify local information 273 // if context_state_ok : yes 274 // if context_state_ko : test the depth, and the priority of event 275 bool is_valid = ((state == CONTEXT_STATE_OK) or 276 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or 277 // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or 278 (depth1< depth0) or 279 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth 280 281 bool is_invalid = priority0 == PRIORITY_MISS_LOAD; 282 283 #ifdef DEBUG_TEST 284 if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and 285 (depth0 != depth1)) 286 throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str())); 287 #endif 288 289 log_printf(TRACE,Context_State,FUNCTION," * state : %s",toString(state).c_str()); 290 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 291 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); 292 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); 293 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); 294 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); 295 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); 296 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); 297 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); 298 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); 299 log_printf(TRACE,Context_State,FUNCTION," * is_invalid : %d",is_invalid); 300 301 if (is_valid and not is_invalid) 302 { 303 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 304 305 if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) 306 { 307 // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) 308 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; 309 // #else 310 reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; 311 // #endif 312 } 313 else 314 { 315 Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE [i]); 316 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); 317 318 log_printf(TRACE,Context_State,FUNCTION," * dest_val : %d",dest_val ); 319 log_printf(TRACE,Context_State,FUNCTION," * can_continue: %d",can_continue); 320 321 if (can_continue) 322 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 323 else 324 { 325 // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) 326 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 327 // #else 328 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; 329 // #endif 330 } 331 332 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 333 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next 334 reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; 335 //reg_EVENT_ADDRESS_EEAR [i] = 0; 336 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; 337 reg_EVENT_IS_DELAY_SLOT [i] = 1; 338 reg_EVENT_IS_DS_TAKE [i] = dest_val; 339 reg_EVENT_DEPTH [i] = depth; 340 reg_EVENT_FLUSH_ONLY [i] = can_continue; 341 } 342 } 343 } 344 345 // ------------------------------------------------------------------- 346 // -----[ DECOD_EVENT ]----------------------------------------------- 347 // ------------------------------------------------------------------- 348 349 for (uint32_t i=0; i<_param->_nb_decod_unit; i++) 350 if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) 351 { 352 log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); 353 354 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; 355 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; 356 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 357 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 358 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; 359 360 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 361 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 362 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 363 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 364 365 context_state_t state = reg_STATE [context]; 366 Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); 367 368 // miss_load > miss_branch > excep > spr/sync 369 uint8_t priority0 = get_priority(state); 370 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE; 371 372 // is_valid = can modify local information 373 // if context_state_ok : yes 374 // if context_state_ko : test the depth, and the priority of envent 375 376 bool is_valid = ((state == CONTEXT_STATE_OK) or 377 (depth1< depth0) or 378 ((depth1==depth0) and (priority1>=priority0))); 379 380 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 381 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); 382 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); 383 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); 384 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); 385 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); 386 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); 387 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); 388 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); 389 390 if (is_valid) 391 { 392 log_printf(TRACE,Context_State,FUNCTION," * is_valid"); 393 394 // decod : 395 // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) 396 context_state_t state_next = state; 397 Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); 398 Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); 399 400 switch (type) 401 { 402 case EVENT_TYPE_EXCEPTION : 403 { 404 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); 405 406 state_next = CONTEXT_STATE_KO_EXCEP; 407 408 break; 409 } 410 case EVENT_TYPE_SPR_ACCESS : 411 { 412 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); 413 414 // state_next = CONTEXT_STATE_KO_SPR ; 415 state_next = CONTEXT_STATE_KO_SPR_EXEC; 416 address++; // take next address 417 // if (is_delay_slot) 418 // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 419 break; 420 } 421 case EVENT_TYPE_MSYNC : 422 { 423 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); 424 425 // state_next = CONTEXT_STATE_KO_MSYNC; 426 state_next = CONTEXT_STATE_KO_MSYNC_EXEC; 427 address++; // take next address 428 // if (is_delay_slot) 429 // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); 430 break; 431 } 432 case EVENT_TYPE_PSYNC : 433 { 434 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); 435 436 // state_next = CONTEXT_STATE_KO_PSYNC; 437 state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; 438 address++; // take next address 439 if (is_delay_slot) 440 throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); 441 break; 442 } 443 case EVENT_TYPE_CSYNC : 444 { 445 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); 446 447 // state_next = CONTEXT_STATE_KO_CSYNC; 448 state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; 449 address++; // take next address 450 if (is_delay_slot) 451 throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); 452 break; 453 } 454 case EVENT_TYPE_NONE : 455 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 456 case EVENT_TYPE_LOAD_MISS_SPECULATION : 457 // case EVENT_TYPE_BRANCH_NO_ACCURATE : 458 default : 459 { 460 throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); 461 } 462 } 463 464 reg_STATE [context] = state_next; 465 reg_EVENT_ADDRESS [context] = address; 466 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); 467 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; 468 //reg_EVENT_ADDRESS_EEAR [context] 469 reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; 470 reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; 471 //reg_EVENT_IS_DS_TAKE [context] = 0; 472 reg_EVENT_DEPTH [context] = depth; 473 reg_EVENT_FLUSH_ONLY [context] = false; 474 } 475 } 238 476 239 477 // ------------------------------------------------------------------- … … 283 521 284 522 // ------------------------------------------------------------------- 285 // -----[ BRANCH_EVENT ]----------------------------------------------286 // -------------------------------------------------------------------287 for (uint32_t i=0; i<_param->_nb_context; ++i)288 if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])289 {290 log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i);291 292 context_state_t state = reg_STATE [i];293 294 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;295 Tdepth_t depth_cur = reg_EVENT_DEPTH [i];296 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;297 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i];298 299 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));300 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));301 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));302 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));303 304 // priority : miss_load > miss_branch > excep > spr/sync305 uint8_t priority0 = get_priority(state);306 uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss307 308 // is_valid = can modify local information309 // if context_state_ok : yes310 // if context_state_ko : test the depth, and the priority of event311 bool is_valid = ((state == CONTEXT_STATE_OK) or312 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or313 // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or314 (depth1< depth0) or315 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth316 317 bool is_invalid = priority0 == PRIORITY_MISS_LOAD;318 319 #ifdef DEBUG_TEST320 if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and321 (depth0 != depth1))322 throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str()));323 #endif324 325 log_printf(TRACE,Context_State,FUNCTION," * state : %s",toString(state).c_str());326 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );327 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );328 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );329 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );330 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );331 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );332 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );333 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );334 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );335 336 if (is_valid and not is_invalid)337 {338 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;339 340 if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE)341 {342 // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)343 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;344 // #else345 reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;346 // #endif347 }348 else349 {350 Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE [i]);351 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);352 353 log_printf(TRACE,Context_State,FUNCTION," * dest_val : %d",dest_val );354 log_printf(TRACE,Context_State,FUNCTION," * can_continue: %d",can_continue);355 356 if (can_continue)357 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;358 else359 {360 // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)361 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;362 // #else363 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;364 // #endif365 }366 367 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot368 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next369 reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;370 //reg_EVENT_ADDRESS_EEAR [i] = 0;371 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;372 reg_EVENT_IS_DELAY_SLOT [i] = 1;373 reg_EVENT_IS_DS_TAKE [i] = dest_val;374 reg_EVENT_DEPTH [i] = depth;375 reg_EVENT_FLUSH_ONLY [i] = can_continue;376 }377 }378 }379 380 // -------------------------------------------------------------------381 523 // -----[ BRANCH_COMPLETE ]---------------------------------------------- 382 524 // ------------------------------------------------------------------- … … 429 571 reg_EVENT_DEPTH [context_id] = depth; 430 572 reg_EVENT_FLUSH_ONLY [context_id] = false; 431 }432 }433 434 // -------------------------------------------------------------------435 // -----[ DECOD_EVENT ]-----------------------------------------------436 // -------------------------------------------------------------------437 438 for (uint32_t i=0; i<_param->_nb_decod_unit; i++)439 if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])440 {441 log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i);442 443 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;444 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0;445 Tdepth_t depth_cur = reg_EVENT_DEPTH [context];446 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;447 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context];448 449 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));450 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));451 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));452 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));453 454 context_state_t state = reg_STATE [context];455 Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]);456 457 // miss_load > miss_branch > excep > spr/sync458 uint8_t priority0 = get_priority(state);459 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE;460 461 // is_valid = can modify local information462 // if context_state_ok : yes463 // if context_state_ko : test the depth, and the priority of envent464 465 bool is_valid = ((state == CONTEXT_STATE_OK) or466 (depth1< depth0) or467 ((depth1==depth0) and (priority1>=priority0)));468 469 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );470 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );471 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );472 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );473 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );474 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );475 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );476 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );477 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );478 479 if (is_valid)480 {481 log_printf(TRACE,Context_State,FUNCTION," * is_valid");482 483 // decod :484 // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)485 context_state_t state_next = state;486 Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]);487 Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);488 489 switch (type)490 {491 case EVENT_TYPE_EXCEPTION :492 {493 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION");494 495 state_next = CONTEXT_STATE_KO_EXCEP;496 497 break;498 }499 case EVENT_TYPE_SPR_ACCESS :500 {501 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS");502 503 // state_next = CONTEXT_STATE_KO_SPR ;504 state_next = CONTEXT_STATE_KO_SPR_EXEC;505 address++; // take next address506 // if (is_delay_slot)507 // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");508 break;509 }510 case EVENT_TYPE_MSYNC :511 {512 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC");513 514 // state_next = CONTEXT_STATE_KO_MSYNC;515 state_next = CONTEXT_STATE_KO_MSYNC_EXEC;516 address++; // take next address517 // if (is_delay_slot)518 // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");519 break;520 }521 case EVENT_TYPE_PSYNC :522 {523 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC");524 525 // state_next = CONTEXT_STATE_KO_PSYNC;526 state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;527 address++; // take next address528 if (is_delay_slot)529 throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");530 break;531 }532 case EVENT_TYPE_CSYNC :533 {534 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC");535 536 // state_next = CONTEXT_STATE_KO_CSYNC;537 state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;538 address++; // take next address539 if (is_delay_slot)540 throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");541 break;542 }543 case EVENT_TYPE_NONE :544 case EVENT_TYPE_BRANCH_MISS_SPECULATION :545 case EVENT_TYPE_LOAD_MISS_SPECULATION :546 // case EVENT_TYPE_BRANCH_NO_ACCURATE :547 default :548 {549 throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));550 }551 }552 553 reg_STATE [context] = state_next;554 reg_EVENT_ADDRESS [context] = address;555 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]);556 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;557 //reg_EVENT_ADDRESS_EEAR [context]558 reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;559 reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot;560 //reg_EVENT_IS_DS_TAKE [context] = 0;561 reg_EVENT_DEPTH [context] = depth;562 reg_EVENT_FLUSH_ONLY [context] = false;563 573 } 564 574 } … … 706 716 } 707 717 718 // ------------------------------------------------------------------- 719 // -----[ INTERRUPT ]------------------------------------------------- 720 // ------------------------------------------------------------------- 708 721 for (uint32_t i=0; i<_param->_nb_context; ++i) 709 722 {
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